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14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/io.h>
17#include <linux/delay.h>
18#include <linux/slab.h>
19#include <linux/dma-mapping.h>
20#include <linux/errno.h>
21#include <linux/fs.h>
22#include <linux/gcd.h>
23#include <linux/interrupt.h>
24#include <linux/kernel.h>
25#include <linux/math64.h>
26#include <linux/mm.h>
27#include <linux/moduleparam.h>
28#include <linux/time.h>
29#include <linux/device.h>
30#include <linux/platform_device.h>
31#include <linux/clk.h>
32
33#include <media/v4l2-common.h>
34#include <media/v4l2-dev.h>
35#include <media/videobuf2-v4l2.h>
36#include <media/videobuf2-dma-contig.h>
37#include <media/soc_camera.h>
38#include <media/drv-intf/soc_mediabus.h>
39
40#include <linux/videodev2.h>
41
42#include <linux/platform_data/media/camera-mx2.h>
43
44#include <asm/dma.h>
45
46#define MX2_CAM_DRV_NAME "mx2-camera"
47#define MX2_CAM_VERSION "0.0.6"
48#define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
49
50
51#define CSICR1_RESET_VAL 0x40000800
52#define CSICR2_RESET_VAL 0x0
53#define CSICR3_RESET_VAL 0x0
54
55
56#define CSICR1_SWAP16_EN (1 << 31)
57#define CSICR1_EXT_VSYNC (1 << 30)
58#define CSICR1_EOF_INTEN (1 << 29)
59#define CSICR1_PRP_IF_EN (1 << 28)
60#define CSICR1_CCIR_MODE (1 << 27)
61#define CSICR1_COF_INTEN (1 << 26)
62#define CSICR1_SF_OR_INTEN (1 << 25)
63#define CSICR1_RF_OR_INTEN (1 << 24)
64#define CSICR1_STATFF_LEVEL (3 << 22)
65#define CSICR1_STATFF_INTEN (1 << 21)
66#define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19)
67#define CSICR1_RXFF_INTEN (1 << 18)
68#define CSICR1_SOF_POL (1 << 17)
69#define CSICR1_SOF_INTEN (1 << 16)
70#define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12)
71#define CSICR1_HSYNC_POL (1 << 11)
72#define CSICR1_CCIR_EN (1 << 10)
73#define CSICR1_MCLKEN (1 << 9)
74#define CSICR1_FCC (1 << 8)
75#define CSICR1_PACK_DIR (1 << 7)
76#define CSICR1_CLR_STATFIFO (1 << 6)
77#define CSICR1_CLR_RXFIFO (1 << 5)
78#define CSICR1_GCLK_MODE (1 << 4)
79#define CSICR1_INV_DATA (1 << 3)
80#define CSICR1_INV_PCLK (1 << 2)
81#define CSICR1_REDGE (1 << 1)
82#define CSICR1_FMT_MASK (CSICR1_PACK_DIR | CSICR1_SWAP16_EN)
83
84#define SHIFT_STATFF_LEVEL 22
85#define SHIFT_RXFF_LEVEL 19
86#define SHIFT_MCLKDIV 12
87
88#define SHIFT_FRMCNT 16
89
90#define CSICR1 0x00
91#define CSICR2 0x04
92#define CSISR 0x08
93#define CSISTATFIFO 0x0c
94#define CSIRFIFO 0x10
95#define CSIRXCNT 0x14
96#define CSICR3 0x1c
97#define CSIDMASA_STATFIFO 0x20
98#define CSIDMATA_STATFIFO 0x24
99#define CSIDMASA_FB1 0x28
100#define CSIDMASA_FB2 0x2c
101#define CSIFBUF_PARA 0x30
102#define CSIIMAG_PARA 0x34
103
104
105#define PRP_CNTL 0x00
106#define PRP_INTR_CNTL 0x04
107#define PRP_INTRSTATUS 0x08
108#define PRP_SOURCE_Y_PTR 0x0c
109#define PRP_SOURCE_CB_PTR 0x10
110#define PRP_SOURCE_CR_PTR 0x14
111#define PRP_DEST_RGB1_PTR 0x18
112#define PRP_DEST_RGB2_PTR 0x1c
113#define PRP_DEST_Y_PTR 0x20
114#define PRP_DEST_CB_PTR 0x24
115#define PRP_DEST_CR_PTR 0x28
116#define PRP_SRC_FRAME_SIZE 0x2c
117#define PRP_DEST_CH1_LINE_STRIDE 0x30
118#define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
119#define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
120#define PRP_CH1_OUT_IMAGE_SIZE 0x3c
121#define PRP_CH2_OUT_IMAGE_SIZE 0x40
122#define PRP_SRC_LINE_STRIDE 0x44
123#define PRP_CSC_COEF_012 0x48
124#define PRP_CSC_COEF_345 0x4c
125#define PRP_CSC_COEF_678 0x50
126#define PRP_CH1_RZ_HORI_COEF1 0x54
127#define PRP_CH1_RZ_HORI_COEF2 0x58
128#define PRP_CH1_RZ_HORI_VALID 0x5c
129#define PRP_CH1_RZ_VERT_COEF1 0x60
130#define PRP_CH1_RZ_VERT_COEF2 0x64
131#define PRP_CH1_RZ_VERT_VALID 0x68
132#define PRP_CH2_RZ_HORI_COEF1 0x6c
133#define PRP_CH2_RZ_HORI_COEF2 0x70
134#define PRP_CH2_RZ_HORI_VALID 0x74
135#define PRP_CH2_RZ_VERT_COEF1 0x78
136#define PRP_CH2_RZ_VERT_COEF2 0x7c
137#define PRP_CH2_RZ_VERT_VALID 0x80
138
139#define PRP_CNTL_CH1EN (1 << 0)
140#define PRP_CNTL_CH2EN (1 << 1)
141#define PRP_CNTL_CSIEN (1 << 2)
142#define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
143#define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
144#define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
145#define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
146#define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
147#define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
148#define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
149#define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
150#define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
151#define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
152#define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
153#define PRP_CNTL_CH1_LEN (1 << 9)
154#define PRP_CNTL_CH2_LEN (1 << 10)
155#define PRP_CNTL_SKIP_FRAME (1 << 11)
156#define PRP_CNTL_SWRST (1 << 12)
157#define PRP_CNTL_CLKEN (1 << 13)
158#define PRP_CNTL_WEN (1 << 14)
159#define PRP_CNTL_CH1BYP (1 << 15)
160#define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
161#define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
162#define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
163#define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
164#define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
165#define PRP_CNTL_CH2B1EN (1 << 29)
166#define PRP_CNTL_CH2B2EN (1 << 30)
167#define PRP_CNTL_CH2FEN (1 << 31)
168
169
170#define PRP_INTR_RDERR (1 << 0)
171#define PRP_INTR_CH1WERR (1 << 1)
172#define PRP_INTR_CH2WERR (1 << 2)
173#define PRP_INTR_CH1FC (1 << 3)
174#define PRP_INTR_CH2FC (1 << 5)
175#define PRP_INTR_LBOVF (1 << 7)
176#define PRP_INTR_CH2OVF (1 << 8)
177
178
179#define PRP_RZ_VALID_TBL_LEN(x) ((x) << 24)
180#define PRP_RZ_VALID_BILINEAR (1 << 31)
181
182#define MAX_VIDEO_MEM 16
183
184#define RESIZE_NUM_MIN 1
185#define RESIZE_NUM_MAX 20
186#define BC_COEF 3
187#define SZ_COEF (1 << BC_COEF)
188
189#define RESIZE_DIR_H 0
190#define RESIZE_DIR_V 1
191
192#define RESIZE_ALGO_BILINEAR 0
193#define RESIZE_ALGO_AVERAGING 1
194
195struct mx2_prp_cfg {
196 int channel;
197 u32 in_fmt;
198 u32 out_fmt;
199 u32 src_pixel;
200 u32 ch1_pixel;
201 u32 irq_flags;
202 u32 csicr1;
203};
204
205
206struct emma_prp_resize {
207 int algo;
208 int len;
209 unsigned char s[RESIZE_NUM_MAX];
210};
211
212
213struct mx2_fmt_cfg {
214 u32 in_fmt;
215 u32 out_fmt;
216 struct mx2_prp_cfg cfg;
217};
218
219struct mx2_buf_internal {
220 struct list_head queue;
221 int bufnum;
222 bool discard;
223};
224
225
226struct mx2_buffer {
227
228 struct vb2_v4l2_buffer vb;
229 struct mx2_buf_internal internal;
230};
231
232enum mx2_camera_type {
233 IMX27_CAMERA,
234};
235
236struct mx2_camera_dev {
237 struct device *dev;
238 struct soc_camera_host soc_host;
239 struct clk *clk_emma_ahb, *clk_emma_ipg;
240 struct clk *clk_csi_ahb, *clk_csi_per;
241
242 void __iomem *base_csi, *base_emma;
243
244 struct mx2_camera_platform_data *pdata;
245 unsigned long platform_flags;
246
247 struct list_head capture;
248 struct list_head active_bufs;
249 struct list_head discard;
250
251 spinlock_t lock;
252
253 int dma;
254 struct mx2_buffer *active;
255 struct mx2_buffer *fb1_active;
256 struct mx2_buffer *fb2_active;
257
258 u32 csicr1;
259 enum mx2_camera_type devtype;
260
261 struct mx2_buf_internal buf_discard[2];
262 void *discard_buffer;
263 dma_addr_t discard_buffer_dma;
264 size_t discard_size;
265 struct mx2_fmt_cfg *emma_prp;
266 struct emma_prp_resize resizing[2];
267 unsigned int s_width, s_height;
268 u32 frame_count;
269 struct vb2_alloc_ctx *alloc_ctx;
270};
271
272static struct platform_device_id mx2_camera_devtype[] = {
273 {
274 .name = "imx27-camera",
275 .driver_data = IMX27_CAMERA,
276 }, {
277
278 }
279};
280MODULE_DEVICE_TABLE(platform, mx2_camera_devtype);
281
282static struct mx2_buffer *mx2_ibuf_to_buf(struct mx2_buf_internal *int_buf)
283{
284 return container_of(int_buf, struct mx2_buffer, internal);
285}
286
287static struct mx2_fmt_cfg mx27_emma_prp_table[] = {
288
289
290
291
292
293
294
295
296
297 {
298 .in_fmt = 0,
299 .out_fmt = 0,
300 .cfg = {
301 .channel = 1,
302 .in_fmt = PRP_CNTL_DATA_IN_RGB16,
303 .out_fmt = PRP_CNTL_CH1_OUT_RGB16,
304 .src_pixel = 0x2ca00565,
305 .ch1_pixel = 0x2ca00565,
306 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
307 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
308 .csicr1 = 0,
309 }
310 },
311 {
312 .in_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
313 .out_fmt = V4L2_PIX_FMT_YUYV,
314 .cfg = {
315 .channel = 1,
316 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
317 .out_fmt = PRP_CNTL_CH1_OUT_YUV422,
318 .src_pixel = 0x22000888,
319 .ch1_pixel = 0x62000888,
320 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
321 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
322 .csicr1 = CSICR1_SWAP16_EN,
323 }
324 },
325 {
326 .in_fmt = MEDIA_BUS_FMT_YUYV8_2X8,
327 .out_fmt = V4L2_PIX_FMT_YUYV,
328 .cfg = {
329 .channel = 1,
330 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
331 .out_fmt = PRP_CNTL_CH1_OUT_YUV422,
332 .src_pixel = 0x22000888,
333 .ch1_pixel = 0x62000888,
334 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
335 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
336 .csicr1 = CSICR1_PACK_DIR,
337 }
338 },
339 {
340 .in_fmt = MEDIA_BUS_FMT_YUYV8_2X8,
341 .out_fmt = V4L2_PIX_FMT_YUV420,
342 .cfg = {
343 .channel = 2,
344 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
345 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
346 .src_pixel = 0x22000888,
347 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
348 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
349 PRP_INTR_CH2OVF,
350 .csicr1 = CSICR1_PACK_DIR,
351 }
352 },
353 {
354 .in_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
355 .out_fmt = V4L2_PIX_FMT_YUV420,
356 .cfg = {
357 .channel = 2,
358 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
359 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
360 .src_pixel = 0x22000888,
361 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
362 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
363 PRP_INTR_CH2OVF,
364 .csicr1 = CSICR1_SWAP16_EN,
365 }
366 },
367};
368
369static struct mx2_fmt_cfg *mx27_emma_prp_get_format(u32 in_fmt, u32 out_fmt)
370{
371 int i;
372
373 for (i = 1; i < ARRAY_SIZE(mx27_emma_prp_table); i++)
374 if ((mx27_emma_prp_table[i].in_fmt == in_fmt) &&
375 (mx27_emma_prp_table[i].out_fmt == out_fmt)) {
376 return &mx27_emma_prp_table[i];
377 }
378
379 return &mx27_emma_prp_table[0];
380};
381
382static void mx27_update_emma_buf(struct mx2_camera_dev *pcdev,
383 unsigned long phys, int bufnum)
384{
385 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
386
387 if (prp->cfg.channel == 1) {
388 writel(phys, pcdev->base_emma +
389 PRP_DEST_RGB1_PTR + 4 * bufnum);
390 } else {
391 writel(phys, pcdev->base_emma +
392 PRP_DEST_Y_PTR - 0x14 * bufnum);
393 if (prp->out_fmt == V4L2_PIX_FMT_YUV420) {
394 u32 imgsize = pcdev->soc_host.icd->user_height *
395 pcdev->soc_host.icd->user_width;
396
397 writel(phys + imgsize, pcdev->base_emma +
398 PRP_DEST_CB_PTR - 0x14 * bufnum);
399 writel(phys + ((5 * imgsize) / 4), pcdev->base_emma +
400 PRP_DEST_CR_PTR - 0x14 * bufnum);
401 }
402 }
403}
404
405static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
406{
407 clk_disable_unprepare(pcdev->clk_csi_ahb);
408 clk_disable_unprepare(pcdev->clk_csi_per);
409 writel(0, pcdev->base_csi + CSICR1);
410 writel(0, pcdev->base_emma + PRP_CNTL);
411}
412
413static int mx2_camera_add_device(struct soc_camera_device *icd)
414{
415 dev_info(icd->parent, "Camera driver attached to camera %d\n",
416 icd->devnum);
417
418 return 0;
419}
420
421static void mx2_camera_remove_device(struct soc_camera_device *icd)
422{
423 dev_info(icd->parent, "Camera driver detached from camera %d\n",
424 icd->devnum);
425}
426
427
428
429
430
431static int mx2_camera_clock_start(struct soc_camera_host *ici)
432{
433 struct mx2_camera_dev *pcdev = ici->priv;
434 int ret;
435 u32 csicr1;
436
437 ret = clk_prepare_enable(pcdev->clk_csi_ahb);
438 if (ret < 0)
439 return ret;
440
441 ret = clk_prepare_enable(pcdev->clk_csi_per);
442 if (ret < 0)
443 goto exit_csi_ahb;
444
445 csicr1 = CSICR1_MCLKEN | CSICR1_PRP_IF_EN | CSICR1_FCC |
446 CSICR1_RXFF_LEVEL(0);
447
448 pcdev->csicr1 = csicr1;
449 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
450
451 pcdev->frame_count = 0;
452
453 return 0;
454
455exit_csi_ahb:
456 clk_disable_unprepare(pcdev->clk_csi_ahb);
457
458 return ret;
459}
460
461static void mx2_camera_clock_stop(struct soc_camera_host *ici)
462{
463 struct mx2_camera_dev *pcdev = ici->priv;
464
465 mx2_camera_deactivate(pcdev);
466}
467
468
469
470
471static int mx2_videobuf_setup(struct vb2_queue *vq,
472 unsigned int *count, unsigned int *num_planes,
473 unsigned int sizes[], void *alloc_ctxs[])
474{
475 struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
476 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
477 struct mx2_camera_dev *pcdev = ici->priv;
478
479 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, sizes[0]);
480
481 alloc_ctxs[0] = pcdev->alloc_ctx;
482
483 sizes[0] = icd->sizeimage;
484
485 if (0 == *count)
486 *count = 32;
487 if (!*num_planes &&
488 sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024)
489 *count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0];
490
491 *num_planes = 1;
492
493 return 0;
494}
495
496static int mx2_videobuf_prepare(struct vb2_buffer *vb)
497{
498 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
499 int ret = 0;
500
501 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
502 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
503
504#ifdef DEBUG
505
506
507
508
509 memset((void *)vb2_plane_vaddr(vb, 0),
510 0xaa, vb2_get_plane_payload(vb, 0));
511#endif
512
513 vb2_set_plane_payload(vb, 0, icd->sizeimage);
514 if (vb2_plane_vaddr(vb, 0) &&
515 vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) {
516 ret = -EINVAL;
517 goto out;
518 }
519
520 return 0;
521
522out:
523 return ret;
524}
525
526static void mx2_videobuf_queue(struct vb2_buffer *vb)
527{
528 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
529 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
530 struct soc_camera_host *ici =
531 to_soc_camera_host(icd->parent);
532 struct mx2_camera_dev *pcdev = ici->priv;
533 struct mx2_buffer *buf = container_of(vbuf, struct mx2_buffer, vb);
534 unsigned long flags;
535
536 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
537 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
538
539 spin_lock_irqsave(&pcdev->lock, flags);
540
541 list_add_tail(&buf->internal.queue, &pcdev->capture);
542
543 spin_unlock_irqrestore(&pcdev->lock, flags);
544}
545
546static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
547 int bytesperline)
548{
549 struct soc_camera_host *ici =
550 to_soc_camera_host(icd->parent);
551 struct mx2_camera_dev *pcdev = ici->priv;
552 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
553
554 writel((pcdev->s_width << 16) | pcdev->s_height,
555 pcdev->base_emma + PRP_SRC_FRAME_SIZE);
556 writel(prp->cfg.src_pixel,
557 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
558 if (prp->cfg.channel == 1) {
559 writel((icd->user_width << 16) | icd->user_height,
560 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
561 writel(bytesperline,
562 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
563 writel(prp->cfg.ch1_pixel,
564 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
565 } else {
566 writel((icd->user_width << 16) | icd->user_height,
567 pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE);
568 }
569
570
571 writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL);
572}
573
574static void mx2_prp_resize_commit(struct mx2_camera_dev *pcdev)
575{
576 int dir;
577
578 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
579 unsigned char *s = pcdev->resizing[dir].s;
580 int len = pcdev->resizing[dir].len;
581 unsigned int coeff[2] = {0, 0};
582 unsigned int valid = 0;
583 int i;
584
585 if (len == 0)
586 continue;
587
588 for (i = RESIZE_NUM_MAX - 1; i >= 0; i--) {
589 int j;
590
591 j = i > 9 ? 1 : 0;
592 coeff[j] = (coeff[j] << BC_COEF) |
593 (s[i] & (SZ_COEF - 1));
594
595 if (i == 5 || i == 15)
596 coeff[j] <<= 1;
597
598 valid = (valid << 1) | (s[i] >> BC_COEF);
599 }
600
601 valid |= PRP_RZ_VALID_TBL_LEN(len);
602
603 if (pcdev->resizing[dir].algo == RESIZE_ALGO_BILINEAR)
604 valid |= PRP_RZ_VALID_BILINEAR;
605
606 if (pcdev->emma_prp->cfg.channel == 1) {
607 if (dir == RESIZE_DIR_H) {
608 writel(coeff[0], pcdev->base_emma +
609 PRP_CH1_RZ_HORI_COEF1);
610 writel(coeff[1], pcdev->base_emma +
611 PRP_CH1_RZ_HORI_COEF2);
612 writel(valid, pcdev->base_emma +
613 PRP_CH1_RZ_HORI_VALID);
614 } else {
615 writel(coeff[0], pcdev->base_emma +
616 PRP_CH1_RZ_VERT_COEF1);
617 writel(coeff[1], pcdev->base_emma +
618 PRP_CH1_RZ_VERT_COEF2);
619 writel(valid, pcdev->base_emma +
620 PRP_CH1_RZ_VERT_VALID);
621 }
622 } else {
623 if (dir == RESIZE_DIR_H) {
624 writel(coeff[0], pcdev->base_emma +
625 PRP_CH2_RZ_HORI_COEF1);
626 writel(coeff[1], pcdev->base_emma +
627 PRP_CH2_RZ_HORI_COEF2);
628 writel(valid, pcdev->base_emma +
629 PRP_CH2_RZ_HORI_VALID);
630 } else {
631 writel(coeff[0], pcdev->base_emma +
632 PRP_CH2_RZ_VERT_COEF1);
633 writel(coeff[1], pcdev->base_emma +
634 PRP_CH2_RZ_VERT_COEF2);
635 writel(valid, pcdev->base_emma +
636 PRP_CH2_RZ_VERT_VALID);
637 }
638 }
639 }
640}
641
642static int mx2_start_streaming(struct vb2_queue *q, unsigned int count)
643{
644 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
645 struct soc_camera_host *ici =
646 to_soc_camera_host(icd->parent);
647 struct mx2_camera_dev *pcdev = ici->priv;
648 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
649 struct vb2_buffer *vb;
650 struct mx2_buffer *buf;
651 unsigned long phys;
652 int bytesperline;
653 unsigned long flags;
654
655 if (count < 2)
656 return -ENOBUFS;
657
658 spin_lock_irqsave(&pcdev->lock, flags);
659
660 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
661 internal.queue);
662 buf->internal.bufnum = 0;
663 vb = &buf->vb.vb2_buf;
664
665 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
666 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
667 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
668
669 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
670 internal.queue);
671 buf->internal.bufnum = 1;
672 vb = &buf->vb.vb2_buf;
673
674 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
675 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
676 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
677
678 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
679 icd->current_fmt->host_fmt);
680 if (bytesperline < 0) {
681 spin_unlock_irqrestore(&pcdev->lock, flags);
682 return bytesperline;
683 }
684
685
686
687
688
689
690
691
692 pcdev->discard_size = icd->user_height * bytesperline;
693 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
694 pcdev->discard_size,
695 &pcdev->discard_buffer_dma, GFP_ATOMIC);
696 if (!pcdev->discard_buffer) {
697 spin_unlock_irqrestore(&pcdev->lock, flags);
698 return -ENOMEM;
699 }
700
701 pcdev->buf_discard[0].discard = true;
702 list_add_tail(&pcdev->buf_discard[0].queue,
703 &pcdev->discard);
704
705 pcdev->buf_discard[1].discard = true;
706 list_add_tail(&pcdev->buf_discard[1].queue,
707 &pcdev->discard);
708
709 mx2_prp_resize_commit(pcdev);
710
711 mx27_camera_emma_buf_init(icd, bytesperline);
712
713 if (prp->cfg.channel == 1) {
714 writel(PRP_CNTL_CH1EN |
715 PRP_CNTL_CSIEN |
716 prp->cfg.in_fmt |
717 prp->cfg.out_fmt |
718 PRP_CNTL_CH1_LEN |
719 PRP_CNTL_CH1BYP |
720 PRP_CNTL_CH1_TSKIP(0) |
721 PRP_CNTL_IN_TSKIP(0),
722 pcdev->base_emma + PRP_CNTL);
723 } else {
724 writel(PRP_CNTL_CH2EN |
725 PRP_CNTL_CSIEN |
726 prp->cfg.in_fmt |
727 prp->cfg.out_fmt |
728 PRP_CNTL_CH2_LEN |
729 PRP_CNTL_CH2_TSKIP(0) |
730 PRP_CNTL_IN_TSKIP(0),
731 pcdev->base_emma + PRP_CNTL);
732 }
733 spin_unlock_irqrestore(&pcdev->lock, flags);
734
735 return 0;
736}
737
738static void mx2_stop_streaming(struct vb2_queue *q)
739{
740 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
741 struct soc_camera_host *ici =
742 to_soc_camera_host(icd->parent);
743 struct mx2_camera_dev *pcdev = ici->priv;
744 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
745 unsigned long flags;
746 void *b;
747 u32 cntl;
748
749 spin_lock_irqsave(&pcdev->lock, flags);
750
751 cntl = readl(pcdev->base_emma + PRP_CNTL);
752 if (prp->cfg.channel == 1) {
753 writel(cntl & ~PRP_CNTL_CH1EN,
754 pcdev->base_emma + PRP_CNTL);
755 } else {
756 writel(cntl & ~PRP_CNTL_CH2EN,
757 pcdev->base_emma + PRP_CNTL);
758 }
759 INIT_LIST_HEAD(&pcdev->capture);
760 INIT_LIST_HEAD(&pcdev->active_bufs);
761 INIT_LIST_HEAD(&pcdev->discard);
762
763 b = pcdev->discard_buffer;
764 pcdev->discard_buffer = NULL;
765
766 spin_unlock_irqrestore(&pcdev->lock, flags);
767
768 dma_free_coherent(ici->v4l2_dev.dev,
769 pcdev->discard_size, b, pcdev->discard_buffer_dma);
770}
771
772static struct vb2_ops mx2_videobuf_ops = {
773 .queue_setup = mx2_videobuf_setup,
774 .buf_prepare = mx2_videobuf_prepare,
775 .buf_queue = mx2_videobuf_queue,
776 .start_streaming = mx2_start_streaming,
777 .stop_streaming = mx2_stop_streaming,
778};
779
780static int mx2_camera_init_videobuf(struct vb2_queue *q,
781 struct soc_camera_device *icd)
782{
783 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
784 q->io_modes = VB2_MMAP | VB2_USERPTR;
785 q->drv_priv = icd;
786 q->ops = &mx2_videobuf_ops;
787 q->mem_ops = &vb2_dma_contig_memops;
788 q->buf_struct_size = sizeof(struct mx2_buffer);
789 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
790
791 return vb2_queue_init(q);
792}
793
794#define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \
795 V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
796 V4L2_MBUS_VSYNC_ACTIVE_LOW | \
797 V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
798 V4L2_MBUS_HSYNC_ACTIVE_LOW | \
799 V4L2_MBUS_PCLK_SAMPLE_RISING | \
800 V4L2_MBUS_PCLK_SAMPLE_FALLING | \
801 V4L2_MBUS_DATA_ACTIVE_HIGH | \
802 V4L2_MBUS_DATA_ACTIVE_LOW)
803
804static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
805{
806 int count = 0;
807
808 readl(pcdev->base_emma + PRP_CNTL);
809 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
810 while (count++ < 100) {
811 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
812 return 0;
813 barrier();
814 udelay(1);
815 }
816
817 return -ETIMEDOUT;
818}
819
820static int mx2_camera_set_bus_param(struct soc_camera_device *icd)
821{
822 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
823 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
824 struct mx2_camera_dev *pcdev = ici->priv;
825 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
826 unsigned long common_flags;
827 int ret;
828 int bytesperline;
829 u32 csicr1 = pcdev->csicr1;
830
831 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
832 if (!ret) {
833 common_flags = soc_mbus_config_compatible(&cfg, MX2_BUS_FLAGS);
834 if (!common_flags) {
835 dev_warn(icd->parent,
836 "Flags incompatible: camera 0x%x, host 0x%x\n",
837 cfg.flags, MX2_BUS_FLAGS);
838 return -EINVAL;
839 }
840 } else if (ret != -ENOIOCTLCMD) {
841 return ret;
842 } else {
843 common_flags = MX2_BUS_FLAGS;
844 }
845
846 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
847 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
848 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
849 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
850 else
851 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
852 }
853
854 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
855 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
856 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
857 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
858 else
859 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
860 }
861
862 cfg.flags = common_flags;
863 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
864 if (ret < 0 && ret != -ENOIOCTLCMD) {
865 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
866 common_flags, ret);
867 return ret;
868 }
869
870 csicr1 = (csicr1 & ~CSICR1_FMT_MASK) | pcdev->emma_prp->cfg.csicr1;
871
872 if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
873 csicr1 |= CSICR1_REDGE;
874 if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
875 csicr1 |= CSICR1_SOF_POL;
876 if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
877 csicr1 |= CSICR1_HSYNC_POL;
878 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
879 csicr1 |= CSICR1_EXT_VSYNC;
880 if (pcdev->platform_flags & MX2_CAMERA_CCIR)
881 csicr1 |= CSICR1_CCIR_EN;
882 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
883 csicr1 |= CSICR1_CCIR_MODE;
884 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
885 csicr1 |= CSICR1_GCLK_MODE;
886 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
887 csicr1 |= CSICR1_INV_DATA;
888
889 pcdev->csicr1 = csicr1;
890
891 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
892 icd->current_fmt->host_fmt);
893 if (bytesperline < 0)
894 return bytesperline;
895
896 ret = mx27_camera_emma_prp_reset(pcdev);
897 if (ret)
898 return ret;
899
900 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
901
902 return 0;
903}
904
905static int mx2_camera_set_crop(struct soc_camera_device *icd,
906 const struct v4l2_crop *a)
907{
908 struct v4l2_crop a_writable = *a;
909 struct v4l2_rect *rect = &a_writable.c;
910 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
911 struct v4l2_subdev_format fmt = {
912 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
913 };
914 struct v4l2_mbus_framefmt *mf = &fmt.format;
915 int ret;
916
917 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
918 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
919
920 ret = v4l2_subdev_call(sd, video, s_crop, a);
921 if (ret < 0)
922 return ret;
923
924
925 ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt);
926 if (ret < 0)
927 return ret;
928
929 dev_dbg(icd->parent, "Sensor cropped %dx%d\n",
930 mf->width, mf->height);
931
932 icd->user_width = mf->width;
933 icd->user_height = mf->height;
934
935 return ret;
936}
937
938static int mx2_camera_get_formats(struct soc_camera_device *icd,
939 unsigned int idx,
940 struct soc_camera_format_xlate *xlate)
941{
942 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
943 const struct soc_mbus_pixelfmt *fmt;
944 struct device *dev = icd->parent;
945 struct v4l2_subdev_mbus_code_enum code = {
946 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
947 .index = idx,
948 };
949 int ret, formats = 0;
950
951 ret = v4l2_subdev_call(sd, pad, enum_mbus_code, NULL, &code);
952 if (ret < 0)
953
954 return 0;
955
956 fmt = soc_mbus_get_fmtdesc(code.code);
957 if (!fmt) {
958 dev_err(dev, "Invalid format code #%u: %d\n", idx, code.code);
959 return 0;
960 }
961
962 if (code.code == MEDIA_BUS_FMT_YUYV8_2X8 ||
963 code.code == MEDIA_BUS_FMT_UYVY8_2X8) {
964 formats++;
965 if (xlate) {
966
967
968
969
970 xlate->host_fmt =
971 soc_mbus_get_fmtdesc(MEDIA_BUS_FMT_YUYV8_1_5X8);
972 xlate->code = code.code;
973 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
974 xlate->host_fmt->name, code.code);
975 xlate++;
976 }
977 }
978
979 if (code.code == MEDIA_BUS_FMT_UYVY8_2X8) {
980 formats++;
981 if (xlate) {
982 xlate->host_fmt =
983 soc_mbus_get_fmtdesc(MEDIA_BUS_FMT_YUYV8_2X8);
984 xlate->code = code.code;
985 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
986 xlate->host_fmt->name, code.code);
987 xlate++;
988 }
989 }
990
991
992 formats++;
993 if (xlate) {
994 xlate->host_fmt = fmt;
995 xlate->code = code.code;
996 xlate++;
997 }
998 return formats;
999}
1000
1001static int mx2_emmaprp_resize(struct mx2_camera_dev *pcdev,
1002 struct v4l2_mbus_framefmt *mf_in,
1003 struct v4l2_pix_format *pix_out, bool apply)
1004{
1005 unsigned int num, den;
1006 unsigned long m;
1007 int i, dir;
1008
1009 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
1010 struct emma_prp_resize tmprsz;
1011 unsigned char *s = tmprsz.s;
1012 int len = 0;
1013 int in, out;
1014
1015 if (dir == RESIZE_DIR_H) {
1016 in = mf_in->width;
1017 out = pix_out->width;
1018 } else {
1019 in = mf_in->height;
1020 out = pix_out->height;
1021 }
1022
1023 if (in < out)
1024 return -EINVAL;
1025 else if (in == out)
1026 continue;
1027
1028
1029 m = gcd(in, out);
1030 num = in / m;
1031 den = out / m;
1032 if (num > RESIZE_NUM_MAX)
1033 return -EINVAL;
1034
1035 if ((num >= 2 * den) && (den == 1) &&
1036 (num < 9) && (!(num & 0x01))) {
1037 int sum = 0;
1038 int j;
1039
1040
1041
1042
1043 tmprsz.algo = RESIZE_ALGO_AVERAGING;
1044 len = num;
1045
1046 for (i = 0; i < (len / 2); i++)
1047 s[i] = 8;
1048
1049 do {
1050 for (i = 0; i < (len / 2); i++) {
1051 s[i] = s[i] >> 1;
1052 sum = 0;
1053 for (j = 0; j < (len / 2); j++)
1054 sum += s[j];
1055 if (sum == 4)
1056 break;
1057 }
1058 } while (sum != 4);
1059
1060 for (i = (len / 2); i < len; i++)
1061 s[i] = s[len - i - 1];
1062
1063 s[len - 1] |= SZ_COEF;
1064 } else {
1065
1066 int v;
1067 int coeff, nxt;
1068 int in_pos_inc = 2 * den;
1069 int out_pos = num;
1070 int out_pos_inc = 2 * num;
1071 int init_carry = num - den;
1072 int carry = init_carry;
1073
1074 tmprsz.algo = RESIZE_ALGO_BILINEAR;
1075 v = den + in_pos_inc;
1076 do {
1077 coeff = v - out_pos;
1078 out_pos += out_pos_inc;
1079 carry += out_pos_inc;
1080 for (nxt = 0; v < out_pos; nxt++) {
1081 v += in_pos_inc;
1082 carry -= in_pos_inc;
1083 }
1084
1085 if (len > RESIZE_NUM_MAX)
1086 return -EINVAL;
1087
1088 coeff = ((coeff << BC_COEF) +
1089 (in_pos_inc >> 1)) / in_pos_inc;
1090
1091 if (coeff >= (SZ_COEF - 1))
1092 coeff--;
1093
1094 coeff |= SZ_COEF;
1095 s[len] = (unsigned char)coeff;
1096 len++;
1097
1098 for (i = 1; i < nxt; i++) {
1099 if (len >= RESIZE_NUM_MAX)
1100 return -EINVAL;
1101 s[len] = 0;
1102 len++;
1103 }
1104 } while (carry != init_carry);
1105 }
1106 tmprsz.len = len;
1107 if (dir == RESIZE_DIR_H)
1108 mf_in->width = pix_out->width;
1109 else
1110 mf_in->height = pix_out->height;
1111
1112 if (apply)
1113 memcpy(&pcdev->resizing[dir], &tmprsz, sizeof(tmprsz));
1114 }
1115 return 0;
1116}
1117
1118static int mx2_camera_set_fmt(struct soc_camera_device *icd,
1119 struct v4l2_format *f)
1120{
1121 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1122 struct mx2_camera_dev *pcdev = ici->priv;
1123 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1124 const struct soc_camera_format_xlate *xlate;
1125 struct v4l2_pix_format *pix = &f->fmt.pix;
1126 struct v4l2_subdev_format format = {
1127 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1128 };
1129 struct v4l2_mbus_framefmt *mf = &format.format;
1130 int ret;
1131
1132 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1133 __func__, pix->width, pix->height);
1134
1135 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1136 if (!xlate) {
1137 dev_warn(icd->parent, "Format %x not found\n",
1138 pix->pixelformat);
1139 return -EINVAL;
1140 }
1141
1142 mf->width = pix->width;
1143 mf->height = pix->height;
1144 mf->field = pix->field;
1145 mf->colorspace = pix->colorspace;
1146 mf->code = xlate->code;
1147
1148 ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &format);
1149 if (ret < 0 && ret != -ENOIOCTLCMD)
1150 return ret;
1151
1152
1153 pcdev->s_width = mf->width;
1154 pcdev->s_height = mf->height;
1155 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1156 __func__, pcdev->s_width, pcdev->s_height);
1157
1158 pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code,
1159 xlate->host_fmt->fourcc);
1160
1161 memset(pcdev->resizing, 0, sizeof(pcdev->resizing));
1162 if ((mf->width != pix->width || mf->height != pix->height) &&
1163 pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1164 if (mx2_emmaprp_resize(pcdev, mf, pix, true) < 0)
1165 dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1166 }
1167
1168 if (mf->code != xlate->code)
1169 return -EINVAL;
1170
1171 pix->width = mf->width;
1172 pix->height = mf->height;
1173 pix->field = mf->field;
1174 pix->colorspace = mf->colorspace;
1175 icd->current_fmt = xlate;
1176
1177 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1178 __func__, pix->width, pix->height);
1179
1180 return 0;
1181}
1182
1183static int mx2_camera_try_fmt(struct soc_camera_device *icd,
1184 struct v4l2_format *f)
1185{
1186 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1187 const struct soc_camera_format_xlate *xlate;
1188 struct v4l2_pix_format *pix = &f->fmt.pix;
1189 struct v4l2_subdev_pad_config pad_cfg;
1190 struct v4l2_subdev_format format = {
1191 .which = V4L2_SUBDEV_FORMAT_TRY,
1192 };
1193 struct v4l2_mbus_framefmt *mf = &format.format;
1194 __u32 pixfmt = pix->pixelformat;
1195 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1196 struct mx2_camera_dev *pcdev = ici->priv;
1197 struct mx2_fmt_cfg *emma_prp;
1198 int ret;
1199
1200 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1201 __func__, pix->width, pix->height);
1202
1203 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1204 if (pixfmt && !xlate) {
1205 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1206 return -EINVAL;
1207 }
1208
1209
1210
1211
1212
1213 pix->width &= ~0x7;
1214
1215
1216 mf->width = pix->width;
1217 mf->height = pix->height;
1218 mf->field = pix->field;
1219 mf->colorspace = pix->colorspace;
1220 mf->code = xlate->code;
1221
1222 ret = v4l2_subdev_call(sd, pad, set_fmt, &pad_cfg, &format);
1223 if (ret < 0)
1224 return ret;
1225
1226 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1227 __func__, pcdev->s_width, pcdev->s_height);
1228
1229
1230 emma_prp = mx27_emma_prp_get_format(xlate->code,
1231 xlate->host_fmt->fourcc);
1232
1233 if ((mf->width != pix->width || mf->height != pix->height) &&
1234 emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1235 if (mx2_emmaprp_resize(pcdev, mf, pix, false) < 0)
1236 dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1237 }
1238
1239 if (mf->field == V4L2_FIELD_ANY)
1240 mf->field = V4L2_FIELD_NONE;
1241
1242
1243
1244
1245
1246 if (mf->field != V4L2_FIELD_NONE && !V4L2_FIELD_HAS_BOTH(mf->field)) {
1247 dev_err(icd->parent, "Field type %d unsupported.\n",
1248 mf->field);
1249 return -EINVAL;
1250 }
1251
1252 pix->width = mf->width;
1253 pix->height = mf->height;
1254 pix->field = mf->field;
1255 pix->colorspace = mf->colorspace;
1256
1257 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1258 __func__, pix->width, pix->height);
1259
1260 return 0;
1261}
1262
1263static int mx2_camera_querycap(struct soc_camera_host *ici,
1264 struct v4l2_capability *cap)
1265{
1266
1267 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
1268 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1269 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
1270
1271 return 0;
1272}
1273
1274static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
1275{
1276 struct soc_camera_device *icd = file->private_data;
1277
1278 return vb2_poll(&icd->vb2_vidq, file, pt);
1279}
1280
1281static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
1282 .owner = THIS_MODULE,
1283 .add = mx2_camera_add_device,
1284 .remove = mx2_camera_remove_device,
1285 .clock_start = mx2_camera_clock_start,
1286 .clock_stop = mx2_camera_clock_stop,
1287 .set_fmt = mx2_camera_set_fmt,
1288 .set_crop = mx2_camera_set_crop,
1289 .get_formats = mx2_camera_get_formats,
1290 .try_fmt = mx2_camera_try_fmt,
1291 .init_videobuf2 = mx2_camera_init_videobuf,
1292 .poll = mx2_camera_poll,
1293 .querycap = mx2_camera_querycap,
1294 .set_bus_param = mx2_camera_set_bus_param,
1295};
1296
1297static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
1298 int bufnum, bool err)
1299{
1300#ifdef DEBUG
1301 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
1302#endif
1303 struct mx2_buf_internal *ibuf;
1304 struct mx2_buffer *buf;
1305 struct vb2_buffer *vb;
1306 struct vb2_v4l2_buffer *vbuf;
1307 unsigned long phys;
1308
1309 ibuf = list_first_entry(&pcdev->active_bufs, struct mx2_buf_internal,
1310 queue);
1311
1312 BUG_ON(ibuf->bufnum != bufnum);
1313
1314 if (ibuf->discard) {
1315
1316
1317
1318
1319 list_move_tail(pcdev->active_bufs.next, &pcdev->discard);
1320 } else {
1321 buf = mx2_ibuf_to_buf(ibuf);
1322
1323 vb = &buf->vb.vb2_buf;
1324 vbuf = to_vb2_v4l2_buffer(vb);
1325#ifdef DEBUG
1326 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1327 if (prp->cfg.channel == 1) {
1328 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR +
1329 4 * bufnum) != phys) {
1330 dev_err(pcdev->dev, "%lx != %x\n", phys,
1331 readl(pcdev->base_emma +
1332 PRP_DEST_RGB1_PTR + 4 * bufnum));
1333 }
1334 } else {
1335 if (readl(pcdev->base_emma + PRP_DEST_Y_PTR -
1336 0x14 * bufnum) != phys) {
1337 dev_err(pcdev->dev, "%lx != %x\n", phys,
1338 readl(pcdev->base_emma +
1339 PRP_DEST_Y_PTR - 0x14 * bufnum));
1340 }
1341 }
1342#endif
1343 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb,
1344 vb2_plane_vaddr(vb, 0),
1345 vb2_get_plane_payload(vb, 0));
1346
1347 list_del_init(&buf->internal.queue);
1348 vb->timestamp = ktime_get_ns();
1349 vbuf->sequence = pcdev->frame_count;
1350 if (err)
1351 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
1352 else
1353 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1354 }
1355
1356 pcdev->frame_count++;
1357
1358 if (list_empty(&pcdev->capture)) {
1359 if (list_empty(&pcdev->discard)) {
1360 dev_warn(pcdev->dev, "%s: trying to access empty discard list\n",
1361 __func__);
1362 return;
1363 }
1364
1365 ibuf = list_first_entry(&pcdev->discard,
1366 struct mx2_buf_internal, queue);
1367 ibuf->bufnum = bufnum;
1368
1369 list_move_tail(pcdev->discard.next, &pcdev->active_bufs);
1370 mx27_update_emma_buf(pcdev, pcdev->discard_buffer_dma, bufnum);
1371 return;
1372 }
1373
1374 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
1375 internal.queue);
1376
1377 buf->internal.bufnum = bufnum;
1378
1379 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
1380
1381 vb = &buf->vb.vb2_buf;
1382
1383 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1384 mx27_update_emma_buf(pcdev, phys, bufnum);
1385}
1386
1387static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
1388{
1389 struct mx2_camera_dev *pcdev = data;
1390 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
1391 struct mx2_buf_internal *ibuf;
1392
1393 spin_lock(&pcdev->lock);
1394
1395 if (list_empty(&pcdev->active_bufs)) {
1396 dev_warn(pcdev->dev, "%s: called while active list is empty\n",
1397 __func__);
1398
1399 if (!status) {
1400 spin_unlock(&pcdev->lock);
1401 return IRQ_NONE;
1402 }
1403 }
1404
1405 if (status & (1 << 7)) {
1406 u32 cntl = readl(pcdev->base_emma + PRP_CNTL);
1407 writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN),
1408 pcdev->base_emma + PRP_CNTL);
1409 writel(cntl, pcdev->base_emma + PRP_CNTL);
1410
1411 ibuf = list_first_entry(&pcdev->active_bufs,
1412 struct mx2_buf_internal, queue);
1413 mx27_camera_frame_done_emma(pcdev,
1414 ibuf->bufnum, true);
1415
1416 status &= ~(1 << 7);
1417 } else if (((status & (3 << 5)) == (3 << 5)) ||
1418 ((status & (3 << 3)) == (3 << 3))) {
1419
1420
1421
1422
1423 ibuf = list_first_entry(&pcdev->active_bufs,
1424 struct mx2_buf_internal, queue);
1425 mx27_camera_frame_done_emma(pcdev, ibuf->bufnum, false);
1426 status &= ~(1 << (6 - ibuf->bufnum));
1427 } else if ((status & (1 << 6)) || (status & (1 << 4))) {
1428 mx27_camera_frame_done_emma(pcdev, 0, false);
1429 } else if ((status & (1 << 5)) || (status & (1 << 3))) {
1430 mx27_camera_frame_done_emma(pcdev, 1, false);
1431 }
1432
1433 spin_unlock(&pcdev->lock);
1434 writel(status, pcdev->base_emma + PRP_INTRSTATUS);
1435
1436 return IRQ_HANDLED;
1437}
1438
1439static int mx27_camera_emma_init(struct platform_device *pdev)
1440{
1441 struct mx2_camera_dev *pcdev = platform_get_drvdata(pdev);
1442 struct resource *res_emma;
1443 int irq_emma;
1444 int err = 0;
1445
1446 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1447 irq_emma = platform_get_irq(pdev, 1);
1448 if (!res_emma || !irq_emma) {
1449 dev_err(pcdev->dev, "no EMMA resources\n");
1450 err = -ENODEV;
1451 goto out;
1452 }
1453
1454 pcdev->base_emma = devm_ioremap_resource(pcdev->dev, res_emma);
1455 if (IS_ERR(pcdev->base_emma)) {
1456 err = PTR_ERR(pcdev->base_emma);
1457 goto out;
1458 }
1459
1460 err = devm_request_irq(pcdev->dev, irq_emma, mx27_camera_emma_irq, 0,
1461 MX2_CAM_DRV_NAME, pcdev);
1462 if (err) {
1463 dev_err(pcdev->dev, "Camera EMMA interrupt register failed\n");
1464 goto out;
1465 }
1466
1467 pcdev->clk_emma_ipg = devm_clk_get(pcdev->dev, "emma-ipg");
1468 if (IS_ERR(pcdev->clk_emma_ipg)) {
1469 err = PTR_ERR(pcdev->clk_emma_ipg);
1470 goto out;
1471 }
1472
1473 clk_prepare_enable(pcdev->clk_emma_ipg);
1474
1475 pcdev->clk_emma_ahb = devm_clk_get(pcdev->dev, "emma-ahb");
1476 if (IS_ERR(pcdev->clk_emma_ahb)) {
1477 err = PTR_ERR(pcdev->clk_emma_ahb);
1478 goto exit_clk_emma_ipg;
1479 }
1480
1481 clk_prepare_enable(pcdev->clk_emma_ahb);
1482
1483 err = mx27_camera_emma_prp_reset(pcdev);
1484 if (err)
1485 goto exit_clk_emma_ahb;
1486
1487 return err;
1488
1489exit_clk_emma_ahb:
1490 clk_disable_unprepare(pcdev->clk_emma_ahb);
1491exit_clk_emma_ipg:
1492 clk_disable_unprepare(pcdev->clk_emma_ipg);
1493out:
1494 return err;
1495}
1496
1497static int mx2_camera_probe(struct platform_device *pdev)
1498{
1499 struct mx2_camera_dev *pcdev;
1500 struct resource *res_csi;
1501 int irq_csi;
1502 int err = 0;
1503
1504 dev_dbg(&pdev->dev, "initialising\n");
1505
1506 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1507 irq_csi = platform_get_irq(pdev, 0);
1508 if (res_csi == NULL || irq_csi < 0) {
1509 dev_err(&pdev->dev, "Missing platform resources data\n");
1510 err = -ENODEV;
1511 goto exit;
1512 }
1513
1514 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
1515 if (!pcdev) {
1516 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1517 err = -ENOMEM;
1518 goto exit;
1519 }
1520
1521 pcdev->clk_csi_ahb = devm_clk_get(&pdev->dev, "ahb");
1522 if (IS_ERR(pcdev->clk_csi_ahb)) {
1523 dev_err(&pdev->dev, "Could not get csi ahb clock\n");
1524 err = PTR_ERR(pcdev->clk_csi_ahb);
1525 goto exit;
1526 }
1527
1528 pcdev->clk_csi_per = devm_clk_get(&pdev->dev, "per");
1529 if (IS_ERR(pcdev->clk_csi_per)) {
1530 dev_err(&pdev->dev, "Could not get csi per clock\n");
1531 err = PTR_ERR(pcdev->clk_csi_per);
1532 goto exit;
1533 }
1534
1535 pcdev->pdata = pdev->dev.platform_data;
1536 if (pcdev->pdata) {
1537 long rate;
1538
1539 pcdev->platform_flags = pcdev->pdata->flags;
1540
1541 rate = clk_round_rate(pcdev->clk_csi_per,
1542 pcdev->pdata->clk * 2);
1543 if (rate <= 0) {
1544 err = -ENODEV;
1545 goto exit;
1546 }
1547 err = clk_set_rate(pcdev->clk_csi_per, rate);
1548 if (err < 0)
1549 goto exit;
1550 }
1551
1552 INIT_LIST_HEAD(&pcdev->capture);
1553 INIT_LIST_HEAD(&pcdev->active_bufs);
1554 INIT_LIST_HEAD(&pcdev->discard);
1555 spin_lock_init(&pcdev->lock);
1556
1557 pcdev->base_csi = devm_ioremap_resource(&pdev->dev, res_csi);
1558 if (IS_ERR(pcdev->base_csi)) {
1559 err = PTR_ERR(pcdev->base_csi);
1560 goto exit;
1561 }
1562
1563 pcdev->dev = &pdev->dev;
1564 platform_set_drvdata(pdev, pcdev);
1565
1566 err = mx27_camera_emma_init(pdev);
1567 if (err)
1568 goto exit;
1569
1570
1571
1572
1573
1574 platform_set_drvdata(pdev, NULL);
1575
1576 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME,
1577 pcdev->soc_host.ops = &mx2_soc_camera_host_ops,
1578 pcdev->soc_host.priv = pcdev;
1579 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1580 pcdev->soc_host.nr = pdev->id;
1581
1582 pcdev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1583 if (IS_ERR(pcdev->alloc_ctx)) {
1584 err = PTR_ERR(pcdev->alloc_ctx);
1585 goto eallocctx;
1586 }
1587 err = soc_camera_host_register(&pcdev->soc_host);
1588 if (err)
1589 goto exit_free_emma;
1590
1591 dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1592 clk_get_rate(pcdev->clk_csi_per));
1593
1594 return 0;
1595
1596exit_free_emma:
1597 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1598eallocctx:
1599 clk_disable_unprepare(pcdev->clk_emma_ipg);
1600 clk_disable_unprepare(pcdev->clk_emma_ahb);
1601exit:
1602 return err;
1603}
1604
1605static int mx2_camera_remove(struct platform_device *pdev)
1606{
1607 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1608 struct mx2_camera_dev *pcdev = container_of(soc_host,
1609 struct mx2_camera_dev, soc_host);
1610
1611 soc_camera_host_unregister(&pcdev->soc_host);
1612
1613 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1614
1615 clk_disable_unprepare(pcdev->clk_emma_ipg);
1616 clk_disable_unprepare(pcdev->clk_emma_ahb);
1617
1618 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
1619
1620 return 0;
1621}
1622
1623static struct platform_driver mx2_camera_driver = {
1624 .driver = {
1625 .name = MX2_CAM_DRV_NAME,
1626 },
1627 .id_table = mx2_camera_devtype,
1628 .remove = mx2_camera_remove,
1629};
1630
1631module_platform_driver_probe(mx2_camera_driver, mx2_camera_probe);
1632
1633MODULE_DESCRIPTION("i.MX27 SoC Camera Host driver");
1634MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1635MODULE_LICENSE("GPL");
1636MODULE_VERSION(MX2_CAM_VERSION);
1637