LXR linux/drivers/staging/rts5208/rtsx

   1/* Driver for Realtek PCI-Express card reader
   2 * Header file
   3 *
   4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms of the GNU General Public License as published by the
   8 * Free Software Foundation; either version 2, or (at your option) any
   9 * later version.
  10 *
  11 * This program is distributed in the hope that it will be useful, but
  12 * WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License along
  17 * with this program; if not, see <http://www.gnu.org/licenses/>.
  18 *
  19 * Author:
  20 *   Wei WANG (wei_wang@realsil.com.cn)
  21 *   Micky Ching (micky_ching@realsil.com.cn)
  22 */
  23
  24#ifndef __REALTEK_RTSX_CHIP_H
  25#define __REALTEK_RTSX_CHIP_H
  26
  27#include "rtsx.h"
  28
  29#define SUPPORT_CPRM
  30#define SUPPORT_OCP
  31#define SUPPORT_SDIO_ASPM
  32#define SUPPORT_MAGIC_GATE
  33#define SUPPORT_MSXC
  34#define SUPPORT_SD_LOCK
  35/* Hardware switch bus_ctl and cd_ctl automatically */
  36#define HW_AUTO_SWITCH_SD_BUS
  37/* Enable hardware interrupt write clear */
  38#define HW_INT_WRITE_CLR
  39/* #define LED_AUTO_BLINK */
  40/* #define DISABLE_CARD_INT */
  41
  42#ifdef SUPPORT_MAGIC_GATE
  43        /* Using NORMAL_WRITE instead of AUTO_WRITE to set ICV */
  44        #define MG_SET_ICV_SLOW
  45        /* HW may miss ERR/CMDNK signal when sampling INT status. */
  46        #define MS_SAMPLE_INT_ERR
  47        /* HW DO NOT support Wait_INT function during READ_BYTES
  48         * transfer mode */
  49        #define READ_BYTES_WAIT_INT
  50#endif
  51
  52#ifdef SUPPORT_MSXC
  53#define XC_POWERCLASS
  54#define SUPPORT_PCGL_1P18
  55#endif
  56
  57#ifndef LED_AUTO_BLINK
  58#define REGULAR_BLINK
  59#endif
  60
  61#define LED_BLINK_SPEED         5
  62#define LED_TOGGLE_INTERVAL     6
  63#define GPIO_TOGGLE_THRESHOLD   1024
  64#define LED_GPIO                0
  65
  66#define POLLING_INTERVAL        30
  67
  68#define TRACE_ITEM_CNT          64
  69
  70#ifndef STATUS_SUCCESS
  71#define STATUS_SUCCESS          0
  72#endif
  73#ifndef STATUS_FAIL
  74#define STATUS_FAIL             1
  75#endif
  76#ifndef STATUS_TIMEDOUT
  77#define STATUS_TIMEDOUT         2
  78#endif
  79#ifndef STATUS_NOMEM
  80#define STATUS_NOMEM            3
  81#endif
  82#ifndef STATUS_READ_FAIL
  83#define STATUS_READ_FAIL        4
  84#endif
  85#ifndef STATUS_WRITE_FAIL
  86#define STATUS_WRITE_FAIL       5
  87#endif
  88#ifndef STATUS_ERROR
  89#define STATUS_ERROR            10
  90#endif
  91
  92#define PM_S1                   1
  93#define PM_S3                   3
  94
  95/*
  96 * Transport return codes
  97 */
  98
  99#define TRANSPORT_GOOD          0   /* Transport good, command good        */
 100#define TRANSPORT_FAILED        1   /* Transport good, command failed   */
 101#define TRANSPORT_NO_SENSE      2  /* Command failed, no auto-sense    */
 102#define TRANSPORT_ERROR         3   /* Transport bad (i.e. device dead) */
 103
 104
 105/*-----------------------------------
 106    Start-Stop-Unit
 107-----------------------------------*/
 108#define STOP_MEDIUM                     0x00    /* access disable         */
 109#define MAKE_MEDIUM_READY               0x01    /* access enable          */
 110#define UNLOAD_MEDIUM                   0x02    /* unload                 */
 111#define LOAD_MEDIUM                     0x03    /* load                   */
 112
 113/*-----------------------------------
 114    STANDARD_INQUIRY
 115-----------------------------------*/
 116#define QULIFIRE                0x00
 117#define AENC_FNC                0x00
 118#define TRML_IOP                0x00
 119#define REL_ADR                 0x00
 120#define WBUS_32                 0x00
 121#define WBUS_16                 0x00
 122#define SYNC                    0x00
 123#define LINKED                  0x00
 124#define CMD_QUE                 0x00
 125#define SFT_RE                  0x00
 126
 127#define VEN_ID_LEN              8               /* Vendor ID Length         */
 128#define PRDCT_ID_LEN            16              /* Product ID Length        */
 129#define PRDCT_REV_LEN           4               /* Product LOT Length       */
 130
 131/* Dynamic flag definitions: used in set_bit() etc. */
 132#define RTSX_FLIDX_TRANS_ACTIVE         18  /* 0x00040000  transfer is active */
 133#define RTSX_FLIDX_ABORTING             20  /* 0x00100000 abort is in
 134                                             * progress */
 135#define RTSX_FLIDX_DISCONNECTING        21  /* 0x00200000 disconnect
 136                                             * in progress */
 137#define ABORTING_OR_DISCONNECTING       ((1UL << US_FLIDX_ABORTING) | \
 138                                         (1UL << US_FLIDX_DISCONNECTING))
 139#define RTSX_FLIDX_RESETTING            22  /* 0x00400000 device reset
 140                                             * in progress */
 141#define RTSX_FLIDX_TIMED_OUT            23  /* 0x00800000 SCSI
 142                                             * midlayer timed out */
 143
 144#define DRCT_ACCESS_DEV         0x00    /* Direct Access Device      */
 145#define RMB_DISC                0x80    /* The Device is Removable   */
 146#define ANSI_SCSI2              0x02    /* Based on ANSI-SCSI2       */
 147
 148#define SCSI                    0x00    /* Interface ID              */
 149
 150#define WRITE_PROTECTED_MEDIA 0x07
 151
 152/*---- sense key ----*/
 153#define ILI                     0x20    /* ILI bit is on                    */
 154
 155#define NO_SENSE                0x00    /* not exist sense key              */
 156#define RECOVER_ERR             0x01    /* Target/Logical unit is recoverd  */
 157#define NOT_READY               0x02    /* Logical unit is not ready        */
 158#define MEDIA_ERR               0x03    /* medium/data error                */
 159#define HARDWARE_ERR            0x04    /* hardware error                   */
 160#define ILGAL_REQ               0x05    /* CDB/parameter/identify msg error */
 161#define UNIT_ATTENTION          0x06    /* unit attention condition occur   */
 162#define DAT_PRTCT               0x07    /* read/write is desable            */
 163#define BLNC_CHK                0x08    /* find blank/DOF in read           */
 164                                        /* write to unblank area            */
 165#define CPY_ABRT                0x0a    /* Copy/Compare/Copy&Verify illgal  */
 166#define ABRT_CMD                0x0b    /* Target make the command in error */
 167#define EQUAL                   0x0c    /* Search Data end with Equal       */
 168#define VLM_OVRFLW              0x0d    /* Some data are left in buffer     */
 169#define MISCMP                  0x0e    /* find inequality                  */
 170
 171#define READ_ERR                -1
 172#define WRITE_ERR               -2
 173
 174#define FIRST_RESET             0x01
 175#define USED_EXIST              0x02
 176
 177/*-----------------------------------
 178    SENSE_DATA
 179-----------------------------------*/
 180/*---- valid ----*/
 181#define SENSE_VALID             0x80    /* Sense data is valid as SCSI2     */
 182#define SENSE_INVALID           0x00    /* Sense data is invalid as SCSI2   */
 183
 184/*---- error code ----*/
 185#define CUR_ERR                 0x70    /* current error                    */
 186#define DEF_ERR                 0x71    /* specific command error           */
 187
 188/*---- sense key Information ----*/
 189#define SNSKEYINFO_LEN          3       /* length of sense key information   */
 190
 191#define SKSV                    0x80
 192#define CDB_ILLEGAL             0x40
 193#define DAT_ILLEGAL             0x00
 194#define BPV                     0x08
 195#define BIT_ILLEGAL0            0       /* bit0 is illegal                  */
 196#define BIT_ILLEGAL1            1       /* bit1 is illegal                  */
 197#define BIT_ILLEGAL2            2       /* bit2 is illegal                  */
 198#define BIT_ILLEGAL3            3       /* bit3 is illegal                  */
 199#define BIT_ILLEGAL4            4       /* bit4 is illegal                  */
 200#define BIT_ILLEGAL5            5       /* bit5 is illegal                  */
 201#define BIT_ILLEGAL6            6       /* bit6 is illegal                  */
 202#define BIT_ILLEGAL7            7       /* bit7 is illegal                  */
 203
 204/*---- ASC ----*/
 205#define ASC_NO_INFO             0x00
 206#define ASC_MISCMP              0x1d
 207#define ASC_INVLD_CDB           0x24
 208#define ASC_INVLD_PARA          0x26
 209#define ASC_LU_NOT_READY        0x04
 210#define ASC_WRITE_ERR           0x0c
 211#define ASC_READ_ERR            0x11
 212#define ASC_LOAD_EJCT_ERR       0x53
 213#define ASC_MEDIA_NOT_PRESENT   0x3A
 214#define ASC_MEDIA_CHANGED       0x28
 215#define ASC_MEDIA_IN_PROCESS    0x04
 216#define ASC_WRITE_PROTECT       0x27
 217#define ASC_LUN_NOT_SUPPORTED   0x25
 218
 219/*---- ASQC ----*/
 220#define ASCQ_NO_INFO            0x00
 221#define ASCQ_MEDIA_IN_PROCESS   0x01
 222#define ASCQ_MISCMP             0x00
 223#define ASCQ_INVLD_CDB          0x00
 224#define ASCQ_INVLD_PARA         0x02
 225#define ASCQ_LU_NOT_READY       0x02
 226#define ASCQ_WRITE_ERR          0x02
 227#define ASCQ_READ_ERR           0x00
 228#define ASCQ_LOAD_EJCT_ERR      0x00
 229#define ASCQ_WRITE_PROTECT      0x00
 230
 231
 232struct sense_data_t {
 233        unsigned char   err_code;       /* error code */
 234        /* bit7 : valid */
 235        /*   (1 : SCSI2) */
 236        /*   (0 : Vendor * specific) */
 237        /* bit6-0 : error * code */
 238        /*  (0x70 : current * error) */
 239        /*  (0x71 : specific command error) */
 240        unsigned char   seg_no;         /* segment No.                      */
 241        unsigned char   sense_key;      /* byte5 : ILI                      */
 242        /* bit3-0 : sense key              */
 243        unsigned char   info[4];        /* information                       */
 244        unsigned char   ad_sense_len;   /* additional sense data length     */
 245        unsigned char   cmd_info[4];    /* command specific information      */
 246        unsigned char   asc;            /* ASC                              */
 247        unsigned char   ascq;           /* ASCQ                             */
 248        unsigned char   rfu;            /* FRU                              */
 249        unsigned char   sns_key_info[3];/* sense key specific information    */
 250};
 251
 252/* PCI Operation Register Address */
 253#define RTSX_HCBAR              0x00
 254#define RTSX_HCBCTLR            0x04
 255#define RTSX_HDBAR              0x08
 256#define RTSX_HDBCTLR            0x0C
 257#define RTSX_HAIMR              0x10
 258#define RTSX_BIPR               0x14
 259#define RTSX_BIER               0x18
 260
 261/* Host command buffer control register */
 262#define STOP_CMD                (0x01 << 28)
 263
 264/* Host data buffer control register */
 265#define SDMA_MODE               0x00
 266#define ADMA_MODE               (0x02 << 26)
 267#define STOP_DMA                (0x01 << 28)
 268#define TRIG_DMA                (0x01 << 31)
 269
 270/* Bus interrupt pending register */
 271#define CMD_DONE_INT            (1 << 31)
 272#define DATA_DONE_INT           (1 << 30)
 273#define TRANS_OK_INT            (1 << 29)
 274#define TRANS_FAIL_INT          (1 << 28)
 275#define XD_INT                  (1 << 27)
 276#define MS_INT                  (1 << 26)
 277#define SD_INT                  (1 << 25)
 278#define GPIO0_INT               (1 << 24)
 279#define OC_INT                  (1 << 23)
 280#define SD_WRITE_PROTECT        (1 << 19)
 281#define XD_EXIST                (1 << 18)
 282#define MS_EXIST                (1 << 17)
 283#define SD_EXIST                (1 << 16)
 284#define DELINK_INT              GPIO0_INT
 285#define MS_OC_INT               (1 << 23)
 286#define SD_OC_INT               (1 << 22)
 287
 288#define CARD_INT                (XD_INT | MS_INT | SD_INT)
 289#define NEED_COMPLETE_INT       (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
 290#define RTSX_INT                (CMD_DONE_INT | NEED_COMPLETE_INT | CARD_INT | GPIO0_INT | OC_INT)
 291
 292#define CARD_EXIST              (XD_EXIST | MS_EXIST | SD_EXIST)
 293
 294/* Bus interrupt enable register */
 295#define CMD_DONE_INT_EN         (1 << 31)
 296#define DATA_DONE_INT_EN        (1 << 30)
 297#define TRANS_OK_INT_EN         (1 << 29)
 298#define TRANS_FAIL_INT_EN       (1 << 28)
 299#define XD_INT_EN               (1 << 27)
 300#define MS_INT_EN               (1 << 26)
 301#define SD_INT_EN               (1 << 25)
 302#define GPIO0_INT_EN            (1 << 24)
 303#define OC_INT_EN               (1 << 23)
 304#define DELINK_INT_EN           GPIO0_INT_EN
 305#define MS_OC_INT_EN            (1 << 23)
 306#define SD_OC_INT_EN            (1 << 22)
 307
 308
 309#define READ_REG_CMD            0
 310#define WRITE_REG_CMD           1
 311#define CHECK_REG_CMD           2
 312
 313#define HOST_TO_DEVICE          0
 314#define DEVICE_TO_HOST          1
 315
 316
 317#define RTSX_RESV_BUF_LEN       4096
 318#define HOST_CMDS_BUF_LEN       1024
 319#define HOST_SG_TBL_BUF_LEN     (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
 320
 321#define SD_NR           2
 322#define MS_NR           3
 323#define XD_NR           4
 324#define SPI_NR          7
 325#define SD_CARD         (1 << SD_NR)
 326#define MS_CARD         (1 << MS_NR)
 327#define XD_CARD         (1 << XD_NR)
 328#define SPI_CARD        (1 << SPI_NR)
 329
 330#define MAX_ALLOWED_LUN_CNT     8
 331
 332#define XD_FREE_TABLE_CNT       1200
 333#define MS_FREE_TABLE_CNT       512
 334
 335
 336/* Bit Operation */
 337#define SET_BIT(data, idx)      ((data) |= 1 << (idx))
 338#define CLR_BIT(data, idx)      ((data) &= ~(1 << (idx)))
 339#define CHK_BIT(data, idx)      ((data) & (1 << (idx)))
 340
 341/* SG descriptor */
 342#define SG_INT                  0x04
 343#define SG_END                  0x02
 344#define SG_VALID                0x01
 345
 346#define SG_NO_OP                0x00
 347#define SG_TRANS_DATA           (0x02 << 4)
 348#define SG_LINK_DESC            (0x03 << 4)
 349
 350struct rtsx_chip;
 351
 352typedef int (*card_rw_func)(struct scsi_cmnd *srb, struct rtsx_chip *chip,
 353                        u32 sec_addr, u16 sec_cnt);
 354
 355/* Supported Clock */
 356enum card_clock {CLK_20 = 1, CLK_30, CLK_40, CLK_50, CLK_60,
 357                 CLK_80, CLK_100, CLK_120, CLK_150, CLK_200};
 358
 359enum RTSX_STAT  {RTSX_STAT_INIT, RTSX_STAT_IDLE, RTSX_STAT_RUN, RTSX_STAT_SS,
 360                 RTSX_STAT_DELINK, RTSX_STAT_SUSPEND,
 361                 RTSX_STAT_ABORT, RTSX_STAT_DISCONNECT};
 362enum IC_VER     {IC_VER_AB, IC_VER_C = 2, IC_VER_D = 3};
 363
 364#define MAX_RESET_CNT           3
 365
 366/* For MS Card */
 367#define MAX_DEFECTIVE_BLOCK     10
 368
 369struct zone_entry {
 370        u16 *l2p_table;
 371        u16 *free_table;
 372        u16 defect_list[MAX_DEFECTIVE_BLOCK];  /* For MS card only */
 373        int set_index;
 374        int get_index;
 375        int unused_blk_cnt;
 376        int disable_count;
 377        /* To indicate whether the L2P table of this zone has been built. */
 378        int build_flag;
 379};
 380
 381#define TYPE_SD                 0x0000
 382#define TYPE_MMC                0x0001
 383
 384/* TYPE_SD */
 385#define SD_HS                   0x0100
 386#define SD_SDR50                0x0200
 387#define SD_DDR50                0x0400
 388#define SD_SDR104               0x0800
 389#define SD_HCXC                 0x1000
 390
 391/* TYPE_MMC */
 392#define MMC_26M                 0x0100
 393#define MMC_52M                 0x0200
 394#define MMC_4BIT                0x0400
 395#define MMC_8BIT                0x0800
 396#define MMC_SECTOR_MODE         0x1000
 397#define MMC_DDR52               0x2000
 398
 399/* SD card */
 400#define CHK_SD(sd_card)                 (((sd_card)->sd_type & 0xFF) == TYPE_SD)
 401#define CHK_SD_HS(sd_card)              (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_HS))
 402#define CHK_SD_SDR50(sd_card)           (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_SDR50))
 403#define CHK_SD_DDR50(sd_card)           (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_DDR50))
 404#define CHK_SD_SDR104(sd_card)          (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_SDR104))
 405#define CHK_SD_HCXC(sd_card)            (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_HCXC))
 406#define CHK_SD_HC(sd_card)              (CHK_SD_HCXC(sd_card) && ((sd_card)->capacity <= 0x4000000))
 407#define CHK_SD_XC(sd_card)              (CHK_SD_HCXC(sd_card) && ((sd_card)->capacity > 0x4000000))
 408#define CHK_SD30_SPEED(sd_card)         (CHK_SD_SDR50(sd_card) || CHK_SD_DDR50(sd_card) || CHK_SD_SDR104(sd_card))
 409
 410#define SET_SD(sd_card)                 ((sd_card)->sd_type = TYPE_SD)
 411#define SET_SD_HS(sd_card)              ((sd_card)->sd_type |= SD_HS)
 412#define SET_SD_SDR50(sd_card)           ((sd_card)->sd_type |= SD_SDR50)
 413#define SET_SD_DDR50(sd_card)           ((sd_card)->sd_type |= SD_DDR50)
 414#define SET_SD_SDR104(sd_card)          ((sd_card)->sd_type |= SD_SDR104)
 415#define SET_SD_HCXC(sd_card)            ((sd_card)->sd_type |= SD_HCXC)
 416
 417#define CLR_SD_HS(sd_card)              ((sd_card)->sd_type &= ~SD_HS)
 418#define CLR_SD_SDR50(sd_card)           ((sd_card)->sd_type &= ~SD_SDR50)
 419#define CLR_SD_DDR50(sd_card)           ((sd_card)->sd_type &= ~SD_DDR50)
 420#define CLR_SD_SDR104(sd_card)          ((sd_card)->sd_type &= ~SD_SDR104)
 421#define CLR_SD_HCXC(sd_card)            ((sd_card)->sd_type &= ~SD_HCXC)
 422
 423/* MMC card */
 424#define CHK_MMC(sd_card)                (((sd_card)->sd_type & 0xFF) == TYPE_MMC)
 425#define CHK_MMC_26M(sd_card)            (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_26M))
 426#define CHK_MMC_52M(sd_card)            (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_52M))
 427#define CHK_MMC_4BIT(sd_card)           (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_4BIT))
 428#define CHK_MMC_8BIT(sd_card)           (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_8BIT))
 429#define CHK_MMC_SECTOR_MODE(sd_card)    (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_SECTOR_MODE))
 430#define CHK_MMC_DDR52(sd_card)          (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_DDR52))
 431
 432#define SET_MMC(sd_card)                ((sd_card)->sd_type = TYPE_MMC)
 433#define SET_MMC_26M(sd_card)            ((sd_card)->sd_type |= MMC_26M)
 434#define SET_MMC_52M(sd_card)            ((sd_card)->sd_type |= MMC_52M)
 435#define SET_MMC_4BIT(sd_card)           ((sd_card)->sd_type |= MMC_4BIT)
 436#define SET_MMC_8BIT(sd_card)           ((sd_card)->sd_type |= MMC_8BIT)
 437#define SET_MMC_SECTOR_MODE(sd_card)    ((sd_card)->sd_type |= MMC_SECTOR_MODE)
 438#define SET_MMC_DDR52(sd_card)          ((sd_card)->sd_type |= MMC_DDR52)
 439
 440#define CLR_MMC_26M(sd_card)            ((sd_card)->sd_type &= ~MMC_26M)
 441#define CLR_MMC_52M(sd_card)            ((sd_card)->sd_type &= ~MMC_52M)
 442#define CLR_MMC_4BIT(sd_card)           ((sd_card)->sd_type &= ~MMC_4BIT)
 443#define CLR_MMC_8BIT(sd_card)           ((sd_card)->sd_type &= ~MMC_8BIT)
 444#define CLR_MMC_SECTOR_MODE(sd_card)    ((sd_card)->sd_type &= ~MMC_SECTOR_MODE)
 445#define CLR_MMC_DDR52(sd_card)          ((sd_card)->sd_type &= ~MMC_DDR52)
 446
 447#define CHK_MMC_HS(sd_card)             (CHK_MMC_52M(sd_card) && CHK_MMC_26M(sd_card))
 448#define CLR_MMC_HS(sd_card)                     \
 449do {                                            \
 450        CLR_MMC_DDR52(sd_card);                 \
 451        CLR_MMC_52M(sd_card);                   \
 452        CLR_MMC_26M(sd_card);                   \
 453} while (0)
 454
 455#define SD_SUPPORT_CLASS_TEN            0x01
 456#define SD_SUPPORT_1V8                  0x02
 457
 458#define SD_SET_CLASS_TEN(sd_card)       ((sd_card)->sd_setting |= SD_SUPPORT_CLASS_TEN)
 459#define SD_CHK_CLASS_TEN(sd_card)       ((sd_card)->sd_setting & SD_SUPPORT_CLASS_TEN)
 460#define SD_CLR_CLASS_TEN(sd_card)       ((sd_card)->sd_setting &= ~SD_SUPPORT_CLASS_TEN)
 461#define SD_SET_1V8(sd_card)             ((sd_card)->sd_setting |= SD_SUPPORT_1V8)
 462#define SD_CHK_1V8(sd_card)             ((sd_card)->sd_setting & SD_SUPPORT_1V8)
 463#define SD_CLR_1V8(sd_card)             ((sd_card)->sd_setting &= ~SD_SUPPORT_1V8)
 464
 465struct sd_info {
 466        u16 sd_type;
 467        u8 err_code;
 468        u8 sd_data_buf_ready;
 469        u32 sd_addr;
 470        u32 capacity;
 471
 472        u8 raw_csd[16];
 473        u8 raw_scr[8];
 474
 475        /* Sequential RW */
 476        int seq_mode;
 477        enum dma_data_direction pre_dir;
 478        u32 pre_sec_addr;
 479        u16 pre_sec_cnt;
 480
 481        int cleanup_counter;
 482
 483        int sd_clock;
 484
 485        int mmc_dont_switch_bus;
 486
 487#ifdef SUPPORT_CPRM
 488        int sd_pass_thru_en;
 489        int pre_cmd_err;
 490        u8 last_rsp_type;
 491        u8 rsp[17];
 492#endif
 493
 494        u8 func_group1_mask;
 495        u8 func_group2_mask;
 496        u8 func_group3_mask;
 497        u8 func_group4_mask;
 498
 499        u8 sd_switch_fail;
 500        u8 sd_read_phase;
 501
 502#ifdef SUPPORT_SD_LOCK
 503        u8 sd_lock_status;
 504        u8 sd_erase_status;
 505        u8 sd_lock_notify;
 506#endif
 507        int need_retune;
 508};
 509
 510struct xd_delay_write_tag {
 511        u32 old_phyblock;
 512        u32 new_phyblock;
 513        u32 logblock;
 514        u8 pageoff;
 515        u8 delay_write_flag;
 516};
 517
 518struct xd_info {
 519        u8 maker_code;
 520        u8 device_code;
 521        u8 block_shift;
 522        u8 page_off;
 523        u8 addr_cycle;
 524        u16 cis_block;
 525        u8 multi_flag;
 526        u8 err_code;
 527        u32 capacity;
 528
 529        struct zone_entry *zone;
 530        int zone_cnt;
 531
 532        struct xd_delay_write_tag delay_write;
 533        int cleanup_counter;
 534
 535        int xd_clock;
 536};
 537
 538#define MODE_512_SEQ            0x01
 539#define MODE_2K_SEQ             0x02
 540
 541#define TYPE_MS                 0x0000
 542#define TYPE_MSPRO              0x0001
 543
 544#define MS_4BIT                 0x0100
 545#define MS_8BIT                 0x0200
 546#define MS_HG                   0x0400
 547#define MS_XC                   0x0800
 548
 549#define HG8BIT                  (MS_HG | MS_8BIT)
 550
 551#define CHK_MSPRO(ms_card)      (((ms_card)->ms_type & 0xFF) == TYPE_MSPRO)
 552#define CHK_HG8BIT(ms_card)     (CHK_MSPRO(ms_card) && (((ms_card)->ms_type & HG8BIT) == HG8BIT))
 553#define CHK_MSXC(ms_card)       (CHK_MSPRO(ms_card) && ((ms_card)->ms_type & MS_XC))
 554#define CHK_MSHG(ms_card)       (CHK_MSPRO(ms_card) && ((ms_card)->ms_type & MS_HG))
 555
 556#define CHK_MS8BIT(ms_card)     (((ms_card)->ms_type & MS_8BIT))
 557#define CHK_MS4BIT(ms_card)     (((ms_card)->ms_type & MS_4BIT))
 558
 559struct ms_delay_write_tag {
 560        u16 old_phyblock;
 561        u16 new_phyblock;
 562        u16 logblock;
 563        u8 pageoff;
 564        u8 delay_write_flag;
 565};
 566
 567struct ms_info {
 568        u16 ms_type;
 569        u8 block_shift;
 570        u8 page_off;
 571        u16 total_block;
 572        u16 boot_block;
 573        u32 capacity;
 574
 575        u8 check_ms_flow;
 576        u8 switch_8bit_fail;
 577        u8 err_code;
 578
 579        struct zone_entry *segment;
 580        int segment_cnt;
 581
 582        int pro_under_formatting;
 583        int format_status;
 584        u16 progress;
 585        u8 raw_sys_info[96];
 586#ifdef SUPPORT_PCGL_1P18
 587        u8 raw_model_name[48];
 588#endif
 589
 590        u8 multi_flag;
 591
 592        /* Sequential RW */
 593        u8 seq_mode;
 594        enum dma_data_direction pre_dir;
 595        u32 pre_sec_addr;
 596        u16 pre_sec_cnt;
 597        u32 total_sec_cnt;
 598
 599        struct ms_delay_write_tag delay_write;
 600
 601        int cleanup_counter;
 602
 603        int ms_clock;
 604
 605#ifdef SUPPORT_MAGIC_GATE
 606        u8 magic_gate_id[16];
 607        u8 mg_entry_num;
 608        int mg_auth;    /* flag to indicate authentication process */
 609#endif
 610};
 611
 612struct spi_info {
 613        u8 use_clk;
 614        u8 write_en;
 615        u16 clk_div;
 616        u8 err_code;
 617
 618        int spi_clock;
 619};
 620
 621
 622#ifdef _MSG_TRACE
 623struct trace_msg_t {
 624        u16 line;
 625#define MSG_FUNC_LEN 64
 626        char func[MSG_FUNC_LEN];
 627#define MSG_FILE_LEN 32
 628        char file[MSG_FILE_LEN];
 629#define TIME_VAL_LEN 16
 630        u8 timeval_buf[TIME_VAL_LEN];
 631        u8 valid;
 632};
 633#endif
 634
 635/************/
 636/* LUN mode */
 637/************/
 638/* Single LUN, support xD/SD/MS */
 639#define DEFAULT_SINGLE          0
 640/* 2 LUN mode, support SD/MS */
 641#define SD_MS_2LUN              1
 642/* Single LUN, but only support SD/MS, for Barossa LQFP */
 643#define SD_MS_1LUN              2
 644
 645#define LAST_LUN_MODE           2
 646
 647/* Barossa package */
 648#define QFN             0
 649#define LQFP            1
 650
 651/******************/
 652/* sd_ctl bit map */
 653/******************/
 654/* SD push point control, bit 0, 1 */
 655#define SD_PUSH_POINT_CTL_MASK          0x03
 656#define SD_PUSH_POINT_DELAY             0x01
 657#define SD_PUSH_POINT_AUTO              0x02
 658/* SD sample point control, bit 2, 3 */
 659#define SD_SAMPLE_POINT_CTL_MASK        0x0C
 660#define SD_SAMPLE_POINT_DELAY           0x04
 661#define SD_SAMPLE_POINT_AUTO            0x08
 662/* SD DDR Tx phase set by user, bit 4 */
 663#define SD_DDR_TX_PHASE_SET_BY_USER     0x10
 664/* MMC DDR Tx phase set by user, bit 5 */
 665#define MMC_DDR_TX_PHASE_SET_BY_USER    0x20
 666/* Support MMC DDR mode, bit 6 */
 667#define SUPPORT_MMC_DDR_MODE            0x40
 668/* Reset MMC at first */
 669#define RESET_MMC_FIRST                 0x80
 670
 671#define SEQ_START_CRITERIA              0x20
 672
 673/* MS Power Class En */
 674#define POWER_CLASS_2_EN                0x02
 675#define POWER_CLASS_1_EN                0x01
 676
 677#define MAX_SHOW_CNT                    10
 678#define MAX_RESET_CNT                   3
 679
 680#define SDIO_EXIST                      0x01
 681#define SDIO_IGNORED                    0x02
 682
 683#define CHK_SDIO_EXIST(chip)            ((chip)->sdio_func_exist & SDIO_EXIST)
 684#define SET_SDIO_EXIST(chip)            ((chip)->sdio_func_exist |= SDIO_EXIST)
 685#define CLR_SDIO_EXIST(chip)            ((chip)->sdio_func_exist &= ~SDIO_EXIST)
 686
 687#define CHK_SDIO_IGNORED(chip)          ((chip)->sdio_func_exist & SDIO_IGNORED)
 688#define SET_SDIO_IGNORED(chip)          ((chip)->sdio_func_exist |= SDIO_IGNORED)
 689#define CLR_SDIO_IGNORED(chip)          ((chip)->sdio_func_exist &= ~SDIO_IGNORED)
 690
 691struct rtsx_chip {
 692        rtsx_dev_t      *rtsx;
 693
 694        u32             int_reg; /* Bus interrupt pending register */
 695        char            max_lun;
 696        void            *context;
 697
 698        void            *host_cmds_ptr; /* host commands buffer pointer */
 699        dma_addr_t      host_cmds_addr;
 700        int             ci;                     /* Command Index */
 701
 702        void            *host_sg_tbl_ptr;       /* SG descriptor table */
 703        dma_addr_t      host_sg_tbl_addr;
 704        int             sgi;                    /* SG entry index */
 705
 706        struct scsi_cmnd        *srb;                   /* current srb */
 707        struct sense_data_t     sense_buffer[MAX_ALLOWED_LUN_CNT];
 708
 709        int                     cur_clk;                /* current card clock */
 710
 711        /* Current accessed card */
 712        int                     cur_card;
 713
 714        unsigned long   need_release;           /* need release bit map */
 715        unsigned long   need_reset;             /* need reset
 716                                                 * bit map */
 717        /* Flag to indicate that this card is just resumed from SS state,
 718         * and need released before being resetted
 719         */
 720        unsigned long           need_reinit;
 721
 722        int                     rw_need_retry;
 723
 724#ifdef SUPPORT_OCP
 725        u32                     ocp_int;
 726        u8                      ocp_stat;
 727#endif
 728
 729        u8      card_exist;     /* card exist bit map (physical exist) */
 730        u8      card_ready;     /* card ready bit map (reset successfully) */
 731        u8      card_fail;      /* card reset fail bit map */
 732        u8      card_ejected;   /* card ejected bit map */
 733        u8      card_wp;        /* card write protected bit map */
 734
 735        u8      lun_mc;         /* flag to indicate whether to answer
 736                                 * MediaChange */
 737
 738#ifndef LED_AUTO_BLINK
 739        int                     led_toggle_counter;
 740#endif
 741
 742        int                     sd_reset_counter;
 743        int                     xd_reset_counter;
 744        int                     ms_reset_counter;
 745
 746        /* card bus width */
 747        u8                      card_bus_width[MAX_ALLOWED_LUN_CNT];
 748        /* card capacity */
 749        u32                     capacity[MAX_ALLOWED_LUN_CNT];
 750        /* read/write card function pointer */
 751        card_rw_func            rw_card[MAX_ALLOWED_LUN_CNT];
 752        /* read/write capacity, used for GPIO Toggle */
 753        u32                     rw_cap[MAX_ALLOWED_LUN_CNT];
 754        /* card to lun mapping table */
 755        u8                      card2lun[32];
 756        /* lun to card mapping table */
 757        u8                      lun2card[MAX_ALLOWED_LUN_CNT];
 758
 759        int                     rw_fail_cnt[MAX_ALLOWED_LUN_CNT];
 760
 761        int                     sd_show_cnt;
 762        int                     xd_show_cnt;
 763        int                     ms_show_cnt;
 764
 765        /* card information */
 766        struct sd_info          sd_card;
 767        struct xd_info          xd_card;
 768        struct ms_info          ms_card;
 769
 770        struct spi_info         spi;
 771
 772#ifdef _MSG_TRACE
 773        struct trace_msg_t      trace_msg[TRACE_ITEM_CNT];
 774        int                     msg_idx;
 775#endif
 776
 777        int                     auto_delink_cnt;
 778        int                     auto_delink_allowed;
 779
 780        int                     aspm_enabled;
 781
 782        int                     sdio_aspm;
 783        int                     sdio_idle;
 784        int                     sdio_counter;
 785        u8                      sdio_raw_data[12];
 786
 787        u8                      sd_io;
 788        u8                      sd_int;
 789
 790        u8                      rtsx_flag;
 791
 792        int                     ss_counter;
 793        int                     idle_counter;
 794        enum RTSX_STAT          rtsx_stat;
 795
 796        u16                     vendor_id;
 797        u16                     product_id;
 798        u8                      ic_version;
 799
 800        int                     driver_first_load;
 801
 802#ifdef HW_AUTO_SWITCH_SD_BUS
 803        int                     sdio_in_charge;
 804#endif
 805
 806        u8                      aspm_level[2];
 807
 808        int                     chip_insert_with_sdio;
 809
 810        /* Options */
 811
 812        int adma_mode;
 813
 814        int auto_delink_en;
 815        int ss_en;
 816        u8 lun_mode;
 817        u8 aspm_l0s_l1_en;
 818
 819        int power_down_in_ss;
 820
 821        int sdr104_en;
 822        int ddr50_en;
 823        int sdr50_en;
 824
 825        int baro_pkg;
 826
 827        int asic_code;
 828        int phy_debug_mode;
 829        int hw_bypass_sd;
 830        int sdio_func_exist;
 831        int aux_pwr_exist;
 832        u8 ms_power_class_en;
 833
 834        int mspro_formatter_enable;
 835
 836        int remote_wakeup_en;
 837
 838        int ignore_sd;
 839        int use_hw_setting;
 840
 841        int ss_idle_period;
 842
 843        int dynamic_aspm;
 844
 845        int fpga_sd_sdr104_clk;
 846        int fpga_sd_ddr50_clk;
 847        int fpga_sd_sdr50_clk;
 848        int fpga_sd_hs_clk;
 849        int fpga_mmc_52m_clk;
 850        int fpga_ms_hg_clk;
 851        int fpga_ms_4bit_clk;
 852        int fpga_ms_1bit_clk;
 853
 854        int asic_sd_sdr104_clk;
 855        int asic_sd_ddr50_clk;
 856        int asic_sd_sdr50_clk;
 857        int asic_sd_hs_clk;
 858        int asic_mmc_52m_clk;
 859        int asic_ms_hg_clk;
 860        int asic_ms_4bit_clk;
 861        int asic_ms_1bit_clk;
 862
 863        u8 ssc_depth_sd_sdr104;
 864        u8 ssc_depth_sd_ddr50;
 865        u8 ssc_depth_sd_sdr50;
 866        u8 ssc_depth_sd_hs;
 867        u8 ssc_depth_mmc_52m;
 868        u8 ssc_depth_ms_hg;
 869        u8 ssc_depth_ms_4bit;
 870        u8 ssc_depth_low_speed;
 871
 872        u8 card_drive_sel;
 873        u8 sd30_drive_sel_1v8;
 874        u8 sd30_drive_sel_3v3;
 875
 876        u8 sd_400mA_ocp_thd;
 877        u8 sd_800mA_ocp_thd;
 878        u8 ms_ocp_thd;
 879
 880        int ssc_en;
 881        int msi_en;
 882
 883        int xd_timeout;
 884        int sd_timeout;
 885        int ms_timeout;
 886        int mspro_timeout;
 887
 888        int auto_power_down;
 889
 890        int sd_ddr_tx_phase;
 891        int mmc_ddr_tx_phase;
 892        int sd_default_tx_phase;
 893        int sd_default_rx_phase;
 894
 895        int pmos_pwr_on_interval;
 896        int sd_voltage_switch_delay;
 897        int s3_pwr_off_delay;
 898
 899        int force_clkreq_0;
 900        int ft2_fast_mode;
 901
 902        int do_delink_before_power_down;
 903        int polling_config;
 904        int sdio_retry_cnt;
 905
 906        int delink_stage1_step;
 907        int delink_stage2_step;
 908        int delink_stage3_step;
 909
 910        int auto_delink_in_L1;
 911        int hp_watch_bios_hotplug;
 912        int support_ms_8bit;
 913
 914        u8 blink_led;
 915        u8 phy_voltage;
 916        u8 max_payload;
 917
 918        u32 sd_speed_prior;
 919        u32 sd_current_prior;
 920        u32 sd_ctl;
 921};
 922
 923static inline struct device *rtsx_dev(const struct rtsx_chip *chip)
 924{
 925        return &chip->rtsx->pci->dev;
 926}
 927
 928#define rtsx_set_stat(chip, stat)                               \
 929do {                                                            \
 930        if ((stat) != RTSX_STAT_IDLE) {                         \
 931                (chip)->idle_counter = 0;                       \
 932        }                                                       \
 933        (chip)->rtsx_stat = (enum RTSX_STAT)(stat);             \
 934} while (0)
 935#define rtsx_get_stat(chip)             ((chip)->rtsx_stat)
 936#define rtsx_chk_stat(chip, stat)       ((chip)->rtsx_stat == (stat))
 937
 938#define RTSX_SET_DELINK(chip)   ((chip)->rtsx_flag |= 0x01)
 939#define RTSX_CLR_DELINK(chip)   ((chip)->rtsx_flag &= 0xFE)
 940#define RTSX_TST_DELINK(chip)   ((chip)->rtsx_flag & 0x01)
 941
 942#define CHECK_PID(chip, pid)            ((chip)->product_id == (pid))
 943#define CHECK_BARO_PKG(chip, pkg)       ((chip)->baro_pkg == (pkg))
 944#define CHECK_LUN_MODE(chip, mode)      ((chip)->lun_mode == (mode))
 945
 946/* Power down control */
 947#define SSC_PDCTL               0x01
 948#define OC_PDCTL                0x02
 949
 950int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl);
 951int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl);
 952
 953void rtsx_disable_card_int(struct rtsx_chip *chip);
 954void rtsx_enable_card_int(struct rtsx_chip *chip);
 955void rtsx_enable_bus_int(struct rtsx_chip *chip);
 956void rtsx_disable_bus_int(struct rtsx_chip *chip);
 957int rtsx_reset_chip(struct rtsx_chip *chip);
 958int rtsx_init_chip(struct rtsx_chip *chip);
 959void rtsx_release_chip(struct rtsx_chip *chip);
 960void rtsx_polling_func(struct rtsx_chip *chip);
 961void rtsx_undo_delink(struct rtsx_chip *chip);
 962void rtsx_stop_cmd(struct rtsx_chip *chip, int card);
 963int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data);
 964int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data);
 965int rtsx_write_cfg_dw(struct rtsx_chip *chip,
 966                u8 func_no, u16 addr, u32 mask, u32 val);
 967int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val);
 968int rtsx_write_cfg_seq(struct rtsx_chip *chip,
 969                u8 func, u16 addr, u8 *buf, int len);
 970int rtsx_read_cfg_seq(struct rtsx_chip *chip,
 971                u8 func, u16 addr, u8 *buf, int len);
 972int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val);
 973int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val);
 974int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val);
 975int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val);
 976int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit);
 977int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit);
 978int rtsx_check_link_ready(struct rtsx_chip *chip);
 979void rtsx_enter_ss(struct rtsx_chip *chip);
 980void rtsx_exit_ss(struct rtsx_chip *chip);
 981int rtsx_pre_handle_interrupt(struct rtsx_chip *chip);
 982void rtsx_enter_L1(struct rtsx_chip *chip);
 983void rtsx_exit_L1(struct rtsx_chip *chip);
 984void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat);
 985void rtsx_enable_aspm(struct rtsx_chip *chip);
 986void rtsx_disable_aspm(struct rtsx_chip *chip);
 987int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len);
 988int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len);
 989int rtsx_check_chip_exist(struct rtsx_chip *chip);
 990
 991#endif  /* __REALTEK_RTSX_CHIP_H */
 992