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19#ifndef __DRIVERS_USB_DWC3_CORE_H
20#define __DRIVERS_USB_DWC3_CORE_H
21
22#include <linux/device.h>
23#include <linux/spinlock.h>
24#include <linux/ioport.h>
25#include <linux/list.h>
26#include <linux/dma-mapping.h>
27#include <linux/mm.h>
28#include <linux/debugfs.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32#include <linux/usb/otg.h>
33#include <linux/ulpi/interface.h>
34
35#include <linux/phy/phy.h>
36
37#define DWC3_MSG_MAX 500
38
39
40#define DWC3_ZLP_BUF_SIZE 1024
41#define DWC3_EP0_BOUNCE_SIZE 512
42#define DWC3_ENDPOINTS_NUM 32
43#define DWC3_XHCI_RESOURCES_NUM 2
44
45#define DWC3_SCRATCHBUF_SIZE 4096
46#define DWC3_EVENT_SIZE 4
47#define DWC3_EVENT_MAX_NUM 64
48#define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
49#define DWC3_EVENT_TYPE_MASK 0xfe
50
51#define DWC3_EVENT_TYPE_DEV 0
52#define DWC3_EVENT_TYPE_CARKIT 3
53#define DWC3_EVENT_TYPE_I2C 4
54
55#define DWC3_DEVICE_EVENT_DISCONNECT 0
56#define DWC3_DEVICE_EVENT_RESET 1
57#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
58#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
59#define DWC3_DEVICE_EVENT_WAKEUP 4
60#define DWC3_DEVICE_EVENT_HIBER_REQ 5
61#define DWC3_DEVICE_EVENT_EOPF 6
62#define DWC3_DEVICE_EVENT_SOF 7
63#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
64#define DWC3_DEVICE_EVENT_CMD_CMPL 10
65#define DWC3_DEVICE_EVENT_OVERFLOW 11
66
67#define DWC3_GEVNTCOUNT_MASK 0xfffc
68#define DWC3_GSNPSID_MASK 0xffff0000
69#define DWC3_GSNPSREV_MASK 0xffff
70
71
72#define DWC3_XHCI_REGS_START 0x0
73#define DWC3_XHCI_REGS_END 0x7fff
74#define DWC3_GLOBALS_REGS_START 0xc100
75#define DWC3_GLOBALS_REGS_END 0xc6ff
76#define DWC3_DEVICE_REGS_START 0xc700
77#define DWC3_DEVICE_REGS_END 0xcbff
78#define DWC3_OTG_REGS_START 0xcc00
79#define DWC3_OTG_REGS_END 0xccff
80
81
82#define DWC3_GSBUSCFG0 0xc100
83#define DWC3_GSBUSCFG1 0xc104
84#define DWC3_GTXTHRCFG 0xc108
85#define DWC3_GRXTHRCFG 0xc10c
86#define DWC3_GCTL 0xc110
87#define DWC3_GEVTEN 0xc114
88#define DWC3_GSTS 0xc118
89#define DWC3_GSNPSID 0xc120
90#define DWC3_GGPIO 0xc124
91#define DWC3_GUID 0xc128
92#define DWC3_GUCTL 0xc12c
93#define DWC3_GBUSERRADDR0 0xc130
94#define DWC3_GBUSERRADDR1 0xc134
95#define DWC3_GPRTBIMAP0 0xc138
96#define DWC3_GPRTBIMAP1 0xc13c
97#define DWC3_GHWPARAMS0 0xc140
98#define DWC3_GHWPARAMS1 0xc144
99#define DWC3_GHWPARAMS2 0xc148
100#define DWC3_GHWPARAMS3 0xc14c
101#define DWC3_GHWPARAMS4 0xc150
102#define DWC3_GHWPARAMS5 0xc154
103#define DWC3_GHWPARAMS6 0xc158
104#define DWC3_GHWPARAMS7 0xc15c
105#define DWC3_GDBGFIFOSPACE 0xc160
106#define DWC3_GDBGLTSSM 0xc164
107#define DWC3_GPRTBIMAP_HS0 0xc180
108#define DWC3_GPRTBIMAP_HS1 0xc184
109#define DWC3_GPRTBIMAP_FS0 0xc188
110#define DWC3_GPRTBIMAP_FS1 0xc18c
111
112#define DWC3_VER_NUMBER 0xc1a0
113#define DWC3_VER_TYPE 0xc1a4
114
115#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
116#define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
117
118#define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
119
120#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
121
122#define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
123#define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
124
125#define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
126#define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
127#define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
128#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
129
130#define DWC3_GHWPARAMS8 0xc600
131#define DWC3_GFLADJ 0xc630
132
133
134#define DWC3_DCFG 0xc700
135#define DWC3_DCTL 0xc704
136#define DWC3_DEVTEN 0xc708
137#define DWC3_DSTS 0xc70c
138#define DWC3_DGCMDPAR 0xc710
139#define DWC3_DGCMD 0xc714
140#define DWC3_DALEPENA 0xc720
141#define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
142#define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
143#define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
144#define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
145
146
147#define DWC3_OCFG 0xcc00
148#define DWC3_OCTL 0xcc04
149#define DWC3_OEVT 0xcc08
150#define DWC3_OEVTEN 0xcc0C
151#define DWC3_OSTS 0xcc10
152
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154
155
156#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
157#define DWC3_GCTL_U2RSTECN (1 << 16)
158#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
159#define DWC3_GCTL_CLK_BUS (0)
160#define DWC3_GCTL_CLK_PIPE (1)
161#define DWC3_GCTL_CLK_PIPEHALF (2)
162#define DWC3_GCTL_CLK_MASK (3)
163
164#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
165#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
166#define DWC3_GCTL_PRTCAP_HOST 1
167#define DWC3_GCTL_PRTCAP_DEVICE 2
168#define DWC3_GCTL_PRTCAP_OTG 3
169
170#define DWC3_GCTL_CORESOFTRESET (1 << 11)
171#define DWC3_GCTL_SOFITPSYNC (1 << 10)
172#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
173#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
174#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
175#define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
176#define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
177#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
178
179
180#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
181#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
182#define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4)
183#define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8)
184
185
186#define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25)
187#define DWC3_GUSB2PHYACC_BUSY (1 << 23)
188#define DWC3_GUSB2PHYACC_WRITE (1 << 22)
189#define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
190#define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
191#define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
192
193
194#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
195#define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
196#define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24)
197#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
198#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
199#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
200#define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18)
201#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
202#define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
203#define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8)
204#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
205#define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
206
207
208#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
209#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
210
211
212#define DWC3_GEVNTSIZ_INTMASK (1 << 31)
213#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
214
215
216#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
217#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
218#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
219#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
220#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
221#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
222
223
224#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
225#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
226#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1
227#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2
228#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
229#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
230#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
231#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
232#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
233#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
234#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
235#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
236
237
238#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
239#define DWC3_MAX_HIBER_SCRATCHBUFS 15
240
241
242#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
243
244
245#define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7)
246#define DWC3_GFLADJ_30MHZ_MASK 0x3f
247#define DWC3_GFLADJ_REFCLK_FLADJ (0x3fff << 8)
248
249
250#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
251#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
252
253#define DWC3_DCFG_SPEED_MASK (7 << 0)
254#define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0)
255#define DWC3_DCFG_SUPERSPEED (4 << 0)
256#define DWC3_DCFG_HIGHSPEED (0 << 0)
257#define DWC3_DCFG_FULLSPEED2 (1 << 0)
258#define DWC3_DCFG_LOWSPEED (2 << 0)
259#define DWC3_DCFG_FULLSPEED1 (3 << 0)
260
261#define DWC3_DCFG_LPM_CAP (1 << 22)
262
263
264#define DWC3_DCTL_RUN_STOP (1 << 31)
265#define DWC3_DCTL_CSFTRST (1 << 30)
266#define DWC3_DCTL_LSFTRST (1 << 29)
267
268#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
269#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
270
271#define DWC3_DCTL_APPL1RES (1 << 23)
272
273
274#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
275#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
276#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
277#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
278#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
279#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
280#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
281
282
283#define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
284#define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
285
286#define DWC3_DCTL_KEEP_CONNECT (1 << 19)
287#define DWC3_DCTL_L1_HIBER_EN (1 << 18)
288#define DWC3_DCTL_CRS (1 << 17)
289#define DWC3_DCTL_CSS (1 << 16)
290
291#define DWC3_DCTL_INITU2ENA (1 << 12)
292#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
293#define DWC3_DCTL_INITU1ENA (1 << 10)
294#define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
295#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
296
297#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
298#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
299
300#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
301#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
302#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
303#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
304#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
305#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
306#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
307
308
309#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
310#define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
311#define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
312#define DWC3_DEVTEN_ERRTICERREN (1 << 9)
313#define DWC3_DEVTEN_SOFEN (1 << 7)
314#define DWC3_DEVTEN_EOPFEN (1 << 6)
315#define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
316#define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
317#define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
318#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
319#define DWC3_DEVTEN_USBRSTEN (1 << 1)
320#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
321
322
323#define DWC3_DSTS_DCNRD (1 << 29)
324
325
326#define DWC3_DSTS_PWRUPREQ (1 << 24)
327
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329#define DWC3_DSTS_RSS (1 << 25)
330#define DWC3_DSTS_SSS (1 << 24)
331
332#define DWC3_DSTS_COREIDLE (1 << 23)
333#define DWC3_DSTS_DEVCTRLHLT (1 << 22)
334
335#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
336#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
337
338#define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
339
340#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
341#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
342
343#define DWC3_DSTS_CONNECTSPD (7 << 0)
344
345#define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0)
346#define DWC3_DSTS_SUPERSPEED (4 << 0)
347#define DWC3_DSTS_HIGHSPEED (0 << 0)
348#define DWC3_DSTS_FULLSPEED2 (1 << 0)
349#define DWC3_DSTS_LOWSPEED (2 << 0)
350#define DWC3_DSTS_FULLSPEED1 (3 << 0)
351
352
353#define DWC3_DGCMD_SET_LMP 0x01
354#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
355#define DWC3_DGCMD_XMIT_FUNCTION 0x03
356
357
358#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
359#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
360
361#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
362#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
363#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
364#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
365
366#define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
367#define DWC3_DGCMD_CMDACT (1 << 10)
368#define DWC3_DGCMD_CMDIOC (1 << 8)
369
370
371#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
372#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
373#define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
374#define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
375#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
376#define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
377
378
379#define DWC3_DEPCMD_PARAM_SHIFT 16
380#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
381#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
382#define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
383#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
384#define DWC3_DEPCMD_CMDACT (1 << 10)
385#define DWC3_DEPCMD_CMDIOC (1 << 8)
386
387#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
388#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
389#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
390#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
391#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
392#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
393
394#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
395
396#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
397#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
398#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
399
400
401#define DWC3_DALEPENA_EP(n) (1 << n)
402
403#define DWC3_DEPCMD_TYPE_CONTROL 0
404#define DWC3_DEPCMD_TYPE_ISOC 1
405#define DWC3_DEPCMD_TYPE_BULK 2
406#define DWC3_DEPCMD_TYPE_INTR 3
407
408
409
410struct dwc3_trb;
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421
422struct dwc3_event_buffer {
423 void *buf;
424 unsigned length;
425 unsigned int lpos;
426 unsigned int count;
427 unsigned int flags;
428
429#define DWC3_EVENT_PENDING BIT(0)
430
431 dma_addr_t dma;
432
433 struct dwc3 *dwc;
434};
435
436#define DWC3_EP_FLAG_STALLED (1 << 0)
437#define DWC3_EP_FLAG_WEDGED (1 << 1)
438
439#define DWC3_EP_DIRECTION_TX true
440#define DWC3_EP_DIRECTION_RX false
441
442#define DWC3_TRB_NUM 32
443#define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
444
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466struct dwc3_ep {
467 struct usb_ep endpoint;
468 struct list_head request_list;
469 struct list_head req_queued;
470
471 struct dwc3_trb *trb_pool;
472 dma_addr_t trb_pool_dma;
473 u32 free_slot;
474 u32 busy_slot;
475 const struct usb_ss_ep_comp_descriptor *comp_desc;
476 struct dwc3 *dwc;
477
478 u32 saved_state;
479 unsigned flags;
480#define DWC3_EP_ENABLED (1 << 0)
481#define DWC3_EP_STALL (1 << 1)
482#define DWC3_EP_WEDGE (1 << 2)
483#define DWC3_EP_BUSY (1 << 4)
484#define DWC3_EP_PENDING_REQUEST (1 << 5)
485#define DWC3_EP_MISSED_ISOC (1 << 6)
486
487
488#define DWC3_EP0_DIR_IN (1 << 31)
489
490 u8 number;
491 u8 type;
492 u8 resource_index;
493 u32 interval;
494
495 char name[20];
496
497 unsigned direction:1;
498 unsigned stream_capable:1;
499};
500
501enum dwc3_phy {
502 DWC3_PHY_UNKNOWN = 0,
503 DWC3_PHY_USB3,
504 DWC3_PHY_USB2,
505};
506
507enum dwc3_ep0_next {
508 DWC3_EP0_UNKNOWN = 0,
509 DWC3_EP0_COMPLETE,
510 DWC3_EP0_NRDY_DATA,
511 DWC3_EP0_NRDY_STATUS,
512};
513
514enum dwc3_ep0_state {
515 EP0_UNCONNECTED = 0,
516 EP0_SETUP_PHASE,
517 EP0_DATA_PHASE,
518 EP0_STATUS_PHASE,
519};
520
521enum dwc3_link_state {
522
523 DWC3_LINK_STATE_U0 = 0x00,
524 DWC3_LINK_STATE_U1 = 0x01,
525 DWC3_LINK_STATE_U2 = 0x02,
526 DWC3_LINK_STATE_U3 = 0x03,
527 DWC3_LINK_STATE_SS_DIS = 0x04,
528 DWC3_LINK_STATE_RX_DET = 0x05,
529 DWC3_LINK_STATE_SS_INACT = 0x06,
530 DWC3_LINK_STATE_POLL = 0x07,
531 DWC3_LINK_STATE_RECOV = 0x08,
532 DWC3_LINK_STATE_HRESET = 0x09,
533 DWC3_LINK_STATE_CMPLY = 0x0a,
534 DWC3_LINK_STATE_LPBK = 0x0b,
535 DWC3_LINK_STATE_RESET = 0x0e,
536 DWC3_LINK_STATE_RESUME = 0x0f,
537 DWC3_LINK_STATE_MASK = 0x0f,
538};
539
540
541#define DWC3_TRB_SIZE_MASK (0x00ffffff)
542#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
543#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
544#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
545
546#define DWC3_TRBSTS_OK 0
547#define DWC3_TRBSTS_MISSED_ISOC 1
548#define DWC3_TRBSTS_SETUP_PENDING 2
549#define DWC3_TRB_STS_XFER_IN_PROG 4
550
551
552#define DWC3_TRB_CTRL_HWO (1 << 0)
553#define DWC3_TRB_CTRL_LST (1 << 1)
554#define DWC3_TRB_CTRL_CHN (1 << 2)
555#define DWC3_TRB_CTRL_CSP (1 << 3)
556#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
557#define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
558#define DWC3_TRB_CTRL_IOC (1 << 11)
559#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
560
561#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
562#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
563#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
564#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
565#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
566#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
567#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
568#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
569
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575
576
577struct dwc3_trb {
578 u32 bpl;
579 u32 bph;
580 u32 size;
581 u32 ctrl;
582} __packed;
583
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595
596struct dwc3_hwparams {
597 u32 hwparams0;
598 u32 hwparams1;
599 u32 hwparams2;
600 u32 hwparams3;
601 u32 hwparams4;
602 u32 hwparams5;
603 u32 hwparams6;
604 u32 hwparams7;
605 u32 hwparams8;
606};
607
608
609#define DWC3_MODE(n) ((n) & 0x7)
610
611#define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
612
613
614#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
615
616
617#define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
618#define DWC3_NUM_EPS_MASK (0x3f << 12)
619#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
620 (DWC3_NUM_EPS_MASK)) >> 12)
621#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
622 (DWC3_NUM_IN_EPS_MASK)) >> 18)
623
624
625#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
626
627struct dwc3_request {
628 struct usb_request request;
629 struct list_head list;
630 struct dwc3_ep *dep;
631 u32 start_slot;
632
633 u8 epnum;
634 struct dwc3_trb *trb;
635 dma_addr_t trb_dma;
636
637 unsigned direction:1;
638 unsigned mapped:1;
639 unsigned queued:1;
640};
641
642
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644
645
646struct dwc3_scratchpad_array {
647 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
648};
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738
739struct dwc3 {
740 struct usb_ctrlrequest *ctrl_req;
741 struct dwc3_trb *ep0_trb;
742 void *ep0_bounce;
743 void *zlp_buf;
744 void *scratchbuf;
745 u8 *setup_buf;
746 dma_addr_t ctrl_req_addr;
747 dma_addr_t ep0_trb_addr;
748 dma_addr_t ep0_bounce_addr;
749 dma_addr_t scratch_addr;
750 struct dwc3_request ep0_usb_req;
751
752
753 spinlock_t lock;
754
755 struct device *dev;
756
757 struct platform_device *xhci;
758 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
759
760 struct dwc3_event_buffer **ev_buffs;
761 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
762
763 struct usb_gadget gadget;
764 struct usb_gadget_driver *gadget_driver;
765
766 struct usb_phy *usb2_phy;
767 struct usb_phy *usb3_phy;
768
769 struct phy *usb2_generic_phy;
770 struct phy *usb3_generic_phy;
771
772 struct ulpi *ulpi;
773
774 void __iomem *regs;
775 size_t regs_size;
776
777 enum usb_dr_mode dr_mode;
778
779
780 u32 dcfg;
781 u32 gctl;
782
783 u32 nr_scratch;
784 u32 num_event_buffers;
785 u32 u1u2;
786 u32 maximum_speed;
787
788
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794
795 u32 revision;
796
797#define DWC3_REVISION_173A 0x5533173a
798#define DWC3_REVISION_175A 0x5533175a
799#define DWC3_REVISION_180A 0x5533180a
800#define DWC3_REVISION_183A 0x5533183a
801#define DWC3_REVISION_185A 0x5533185a
802#define DWC3_REVISION_187A 0x5533187a
803#define DWC3_REVISION_188A 0x5533188a
804#define DWC3_REVISION_190A 0x5533190a
805#define DWC3_REVISION_194A 0x5533194a
806#define DWC3_REVISION_200A 0x5533200a
807#define DWC3_REVISION_202A 0x5533202a
808#define DWC3_REVISION_210A 0x5533210a
809#define DWC3_REVISION_220A 0x5533220a
810#define DWC3_REVISION_230A 0x5533230a
811#define DWC3_REVISION_240A 0x5533240a
812#define DWC3_REVISION_250A 0x5533250a
813#define DWC3_REVISION_260A 0x5533260a
814#define DWC3_REVISION_270A 0x5533270a
815#define DWC3_REVISION_280A 0x5533280a
816
817
818
819
820
821#define DWC3_REVISION_IS_DWC31 0x80000000
822#define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_USB31)
823
824 enum dwc3_ep0_next ep0_next_event;
825 enum dwc3_ep0_state ep0state;
826 enum dwc3_link_state link_state;
827
828 u16 isoch_delay;
829 u16 u2sel;
830 u16 u2pel;
831 u8 u1sel;
832 u8 u1pel;
833
834 u8 speed;
835
836 u8 num_out_eps;
837 u8 num_in_eps;
838
839 void *mem;
840
841 struct dwc3_hwparams hwparams;
842 struct dentry *root;
843 struct debugfs_regset32 *regset;
844
845 u8 test_mode;
846 u8 test_mode_nr;
847 u8 lpm_nyet_threshold;
848 u8 hird_threshold;
849
850 const char *hsphy_interface;
851
852 unsigned delayed_status:1;
853 unsigned ep0_bounced:1;
854 unsigned ep0_expect_in:1;
855 unsigned has_hibernation:1;
856 unsigned has_lpm_erratum:1;
857 unsigned is_utmi_l1_suspend:1;
858 unsigned is_fpga:1;
859 unsigned needs_fifo_resize:1;
860 unsigned pullups_connected:1;
861 unsigned resize_fifos:1;
862 unsigned setup_packet_pending:1;
863 unsigned three_stage_setup:1;
864 unsigned usb3_lpm_capable:1;
865
866 unsigned disable_scramble_quirk:1;
867 unsigned u2exit_lfps_quirk:1;
868 unsigned u2ss_inp3_quirk:1;
869 unsigned req_p1p2p3_quirk:1;
870 unsigned del_p1p2p3_quirk:1;
871 unsigned del_phy_power_chg_quirk:1;
872 unsigned lfps_filter_quirk:1;
873 unsigned rx_detect_poll_quirk:1;
874 unsigned dis_u3_susphy_quirk:1;
875 unsigned dis_u2_susphy_quirk:1;
876 unsigned dis_enblslpm_quirk:1;
877
878 unsigned tx_de_emphasis_quirk:1;
879 unsigned tx_de_emphasis:2;
880};
881
882
883
884
885
886struct dwc3_event_type {
887 u32 is_devspec:1;
888 u32 type:7;
889 u32 reserved8_31:24;
890} __packed;
891
892#define DWC3_DEPEVT_XFERCOMPLETE 0x01
893#define DWC3_DEPEVT_XFERINPROGRESS 0x02
894#define DWC3_DEPEVT_XFERNOTREADY 0x03
895#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
896#define DWC3_DEPEVT_STREAMEVT 0x06
897#define DWC3_DEPEVT_EPCMDCMPLT 0x07
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918struct dwc3_event_depevt {
919 u32 one_bit:1;
920 u32 endpoint_number:5;
921 u32 endpoint_event:4;
922 u32 reserved11_10:2;
923 u32 status:4;
924
925
926#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
927
928
929#define DEPEVT_STATUS_BUSERR (1 << 0)
930#define DEPEVT_STATUS_SHORT (1 << 1)
931#define DEPEVT_STATUS_IOC (1 << 2)
932#define DEPEVT_STATUS_LST (1 << 3)
933
934
935#define DEPEVT_STREAMEVT_FOUND 1
936#define DEPEVT_STREAMEVT_NOTFOUND 2
937
938
939#define DEPEVT_STATUS_CONTROL_DATA 1
940#define DEPEVT_STATUS_CONTROL_STATUS 2
941
942 u32 parameters:16;
943} __packed;
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967struct dwc3_event_devt {
968 u32 one_bit:1;
969 u32 device_event:7;
970 u32 type:4;
971 u32 reserved15_12:4;
972 u32 event_info:9;
973 u32 reserved31_25:7;
974} __packed;
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981
982
983struct dwc3_event_gevt {
984 u32 one_bit:1;
985 u32 device_event:7;
986 u32 phy_port_number:4;
987 u32 reserved31_12:20;
988} __packed;
989
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997
998union dwc3_event {
999 u32 raw;
1000 struct dwc3_event_type type;
1001 struct dwc3_event_depevt depevt;
1002 struct dwc3_event_devt devt;
1003 struct dwc3_event_gevt gevt;
1004};
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1011
1012
1013struct dwc3_gadget_ep_cmd_params {
1014 u32 param2;
1015 u32 param1;
1016 u32 param0;
1017};
1018
1019
1020
1021
1022
1023#define DWC3_HAS_PERIPHERAL BIT(0)
1024#define DWC3_HAS_XHCI BIT(1)
1025#define DWC3_HAS_OTG BIT(3)
1026
1027
1028void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1029int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
1030
1031
1032static inline bool dwc3_is_usb31(struct dwc3 *dwc)
1033{
1034 return !!(dwc->revision & DWC3_REVISION_IS_DWC31);
1035}
1036
1037#if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1038int dwc3_host_init(struct dwc3 *dwc);
1039void dwc3_host_exit(struct dwc3 *dwc);
1040#else
1041static inline int dwc3_host_init(struct dwc3 *dwc)
1042{ return 0; }
1043static inline void dwc3_host_exit(struct dwc3 *dwc)
1044{ }
1045#endif
1046
1047#if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1048int dwc3_gadget_init(struct dwc3 *dwc);
1049void dwc3_gadget_exit(struct dwc3 *dwc);
1050int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1051int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1052int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1053int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1054 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params);
1055int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1056#else
1057static inline int dwc3_gadget_init(struct dwc3 *dwc)
1058{ return 0; }
1059static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1060{ }
1061static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1062{ return 0; }
1063static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1064{ return 0; }
1065static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1066 enum dwc3_link_state state)
1067{ return 0; }
1068
1069static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1070 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
1071{ return 0; }
1072static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1073 int cmd, u32 param)
1074{ return 0; }
1075#endif
1076
1077
1078#if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1079int dwc3_gadget_suspend(struct dwc3 *dwc);
1080int dwc3_gadget_resume(struct dwc3 *dwc);
1081#else
1082static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1083{
1084 return 0;
1085}
1086
1087static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1088{
1089 return 0;
1090}
1091#endif
1092
1093#if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1094int dwc3_ulpi_init(struct dwc3 *dwc);
1095void dwc3_ulpi_exit(struct dwc3 *dwc);
1096#else
1097static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1098{ return 0; }
1099static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1100{ }
1101#endif
1102
1103#endif
1104