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19#ifndef __LINUX_EHCI_HCD_H
20#define __LINUX_EHCI_HCD_H
21
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30
31
32#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
33typedef __u32 __bitwise __hc32;
34typedef __u16 __bitwise __hc16;
35#else
36#define __hc32 __le32
37#define __hc16 __le16
38#endif
39
40
41#ifdef CONFIG_DYNAMIC_DEBUG
42#define EHCI_STATS
43#endif
44
45struct ehci_stats {
46
47 unsigned long normal;
48 unsigned long error;
49 unsigned long iaa;
50 unsigned long lost_iaa;
51
52
53 unsigned long complete;
54 unsigned long unlink;
55};
56
57
58
59
60
61struct ehci_per_sched {
62 struct usb_device *udev;
63 struct usb_host_endpoint *ep;
64 struct list_head ps_list;
65 u16 tt_usecs;
66 u16 cs_mask;
67 u16 period;
68 u16 phase;
69 u8 bw_phase;
70
71 u8 phase_uf;
72 u8 usecs, c_usecs;
73 u8 bw_uperiod;
74
75 u8 bw_period;
76};
77#define NO_FRAME 29999
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86
87
88
89#define EHCI_MAX_ROOT_PORTS 15
90
91
92
93
94
95enum ehci_rh_state {
96 EHCI_RH_HALTED,
97 EHCI_RH_SUSPENDED,
98 EHCI_RH_RUNNING,
99 EHCI_RH_STOPPING
100};
101
102
103
104
105
106
107enum ehci_hrtimer_event {
108 EHCI_HRTIMER_POLL_ASS,
109 EHCI_HRTIMER_POLL_PSS,
110 EHCI_HRTIMER_POLL_DEAD,
111 EHCI_HRTIMER_UNLINK_INTR,
112 EHCI_HRTIMER_FREE_ITDS,
113 EHCI_HRTIMER_ACTIVE_UNLINK,
114 EHCI_HRTIMER_START_UNLINK_INTR,
115 EHCI_HRTIMER_ASYNC_UNLINKS,
116 EHCI_HRTIMER_IAA_WATCHDOG,
117 EHCI_HRTIMER_DISABLE_PERIODIC,
118 EHCI_HRTIMER_DISABLE_ASYNC,
119 EHCI_HRTIMER_IO_WATCHDOG,
120 EHCI_HRTIMER_NUM_EVENTS
121};
122#define EHCI_HRTIMER_NO_EVENT 99
123
124struct ehci_hcd {
125
126 enum ehci_hrtimer_event next_hrtimer_event;
127 unsigned enabled_hrtimer_events;
128 ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
129 struct hrtimer hrtimer;
130
131 int PSS_poll_count;
132 int ASS_poll_count;
133 int died_poll_count;
134
135
136 struct ehci_caps __iomem *caps;
137 struct ehci_regs __iomem *regs;
138 struct ehci_dbg_port __iomem *debug;
139
140 __u32 hcs_params;
141 spinlock_t lock;
142 enum ehci_rh_state rh_state;
143
144
145 bool scanning:1;
146 bool need_rescan:1;
147 bool intr_unlinking:1;
148 bool iaa_in_progress:1;
149 bool async_unlinking:1;
150 bool shutdown:1;
151 struct ehci_qh *qh_scan_next;
152
153
154 struct ehci_qh *async;
155 struct ehci_qh *dummy;
156 struct list_head async_unlink;
157 struct list_head async_idle;
158 unsigned async_unlink_cycle;
159 unsigned async_count;
160 __hc32 old_current;
161 __hc32 old_token;
162
163
164#define DEFAULT_I_TDPS 1024
165 unsigned periodic_size;
166 __hc32 *periodic;
167 dma_addr_t periodic_dma;
168 struct list_head intr_qh_list;
169 unsigned i_thresh;
170
171 union ehci_shadow *pshadow;
172 struct list_head intr_unlink_wait;
173 struct list_head intr_unlink;
174 unsigned intr_unlink_wait_cycle;
175 unsigned intr_unlink_cycle;
176 unsigned now_frame;
177 unsigned last_iso_frame;
178 unsigned intr_count;
179 unsigned isoc_count;
180 unsigned periodic_count;
181 unsigned uframe_periodic_max;
182
183
184
185 struct list_head cached_itd_list;
186 struct ehci_itd *last_itd_to_free;
187 struct list_head cached_sitd_list;
188 struct ehci_sitd *last_sitd_to_free;
189
190
191 unsigned long reset_done[EHCI_MAX_ROOT_PORTS];
192
193
194 unsigned long bus_suspended;
195
196 unsigned long companion_ports;
197
198 unsigned long owned_ports;
199
200 unsigned long port_c_suspend;
201
202 unsigned long suspended_ports;
203
204 unsigned long resuming_ports;
205
206
207
208 struct dma_pool *qh_pool;
209 struct dma_pool *qtd_pool;
210 struct dma_pool *itd_pool;
211 struct dma_pool *sitd_pool;
212
213 unsigned random_frame;
214 unsigned long next_statechange;
215 ktime_t last_periodic_enable;
216 u32 command;
217
218
219 unsigned no_selective_suspend:1;
220 unsigned has_fsl_port_bug:1;
221 unsigned has_fsl_hs_errata:1;
222 unsigned big_endian_mmio:1;
223 unsigned big_endian_desc:1;
224 unsigned big_endian_capbase:1;
225 unsigned has_amcc_usb23:1;
226 unsigned need_io_watchdog:1;
227 unsigned amd_pll_fix:1;
228 unsigned use_dummy_qh:1;
229 unsigned has_synopsys_hc_bug:1;
230 unsigned frame_index_bug:1;
231 unsigned need_oc_pp_cycle:1;
232 unsigned imx28_write_fix:1;
233
234
235 #define OHCI_CTRL_HCFS (3 << 6)
236 #define OHCI_USB_OPER (2 << 6)
237 #define OHCI_USB_SUSPEND (3 << 6)
238
239 #define OHCI_HCCTRL_OFFSET 0x4
240 #define OHCI_HCCTRL_LEN 0x4
241 __hc32 *ohci_hcctrl_reg;
242 unsigned has_hostpc:1;
243 unsigned has_tdi_phy_lpm:1;
244 unsigned has_ppcd:1;
245 u8 sbrn;
246
247
248#ifdef EHCI_STATS
249 struct ehci_stats stats;
250# define COUNT(x) ((x)++)
251#else
252# define COUNT(x)
253#endif
254
255
256#ifdef CONFIG_DYNAMIC_DEBUG
257 struct dentry *debug_dir;
258#endif
259
260
261#define EHCI_BANDWIDTH_SIZE 64
262#define EHCI_BANDWIDTH_FRAMES (EHCI_BANDWIDTH_SIZE >> 3)
263 u8 bandwidth[EHCI_BANDWIDTH_SIZE];
264
265 u8 tt_budget[EHCI_BANDWIDTH_SIZE];
266
267 struct list_head tt_list;
268
269
270 unsigned long priv[0] __aligned(sizeof(s64));
271};
272
273
274static inline struct ehci_hcd *hcd_to_ehci(struct usb_hcd *hcd)
275{
276 return (struct ehci_hcd *) (hcd->hcd_priv);
277}
278static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci)
279{
280 return container_of((void *) ehci, struct usb_hcd, hcd_priv);
281}
282
283
284
285#include <linux/usb/ehci_def.h>
286
287
288
289#define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
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298
299struct ehci_qtd {
300
301 __hc32 hw_next;
302 __hc32 hw_alt_next;
303 __hc32 hw_token;
304#define QTD_TOGGLE (1 << 31)
305#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
306#define QTD_IOC (1 << 15)
307#define QTD_CERR(tok) (((tok)>>10) & 0x3)
308#define QTD_PID(tok) (((tok)>>8) & 0x3)
309#define QTD_STS_ACTIVE (1 << 7)
310#define QTD_STS_HALT (1 << 6)
311#define QTD_STS_DBE (1 << 5)
312#define QTD_STS_BABBLE (1 << 4)
313#define QTD_STS_XACT (1 << 3)
314#define QTD_STS_MMF (1 << 2)
315#define QTD_STS_STS (1 << 1)
316#define QTD_STS_PING (1 << 0)
317
318#define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
319#define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
320#define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
321
322 __hc32 hw_buf[5];
323 __hc32 hw_buf_hi[5];
324
325
326 dma_addr_t qtd_dma;
327 struct list_head qtd_list;
328 struct urb *urb;
329 size_t length;
330} __aligned(32);
331
332
333#define QTD_MASK(ehci) cpu_to_hc32(ehci, ~0x1f)
334
335#define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
336
337
338
339
340#define Q_NEXT_TYPE(ehci, dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
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349
350#define Q_TYPE_ITD (0 << 1)
351#define Q_TYPE_QH (1 << 1)
352#define Q_TYPE_SITD (2 << 1)
353#define Q_TYPE_FSTN (3 << 1)
354
355
356#define QH_NEXT(ehci, dma) \
357 (cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH))
358
359
360#define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1)
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369
370union ehci_shadow {
371 struct ehci_qh *qh;
372 struct ehci_itd *itd;
373 struct ehci_sitd *sitd;
374 struct ehci_fstn *fstn;
375 __hc32 *hw_next;
376 void *ptr;
377};
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389
390struct ehci_qh_hw {
391 __hc32 hw_next;
392 __hc32 hw_info1;
393#define QH_CONTROL_EP (1 << 27)
394#define QH_HEAD (1 << 15)
395#define QH_TOGGLE_CTL (1 << 14)
396#define QH_HIGH_SPEED (2 << 12)
397#define QH_LOW_SPEED (1 << 12)
398#define QH_FULL_SPEED (0 << 12)
399#define QH_INACTIVATE (1 << 7)
400 __hc32 hw_info2;
401#define QH_SMASK 0x000000ff
402#define QH_CMASK 0x0000ff00
403#define QH_HUBADDR 0x007f0000
404#define QH_HUBPORT 0x3f800000
405#define QH_MULT 0xc0000000
406 __hc32 hw_current;
407
408
409 __hc32 hw_qtd_next;
410 __hc32 hw_alt_next;
411 __hc32 hw_token;
412 __hc32 hw_buf[5];
413 __hc32 hw_buf_hi[5];
414} __aligned(32);
415
416struct ehci_qh {
417 struct ehci_qh_hw *hw;
418
419 dma_addr_t qh_dma;
420 union ehci_shadow qh_next;
421 struct list_head qtd_list;
422 struct list_head intr_node;
423 struct ehci_qtd *dummy;
424 struct list_head unlink_node;
425 struct ehci_per_sched ps;
426
427 unsigned unlink_cycle;
428
429 u8 qh_state;
430#define QH_STATE_LINKED 1
431#define QH_STATE_UNLINK 2
432#define QH_STATE_IDLE 3
433#define QH_STATE_UNLINK_WAIT 4
434#define QH_STATE_COMPLETING 5
435
436 u8 xacterrs;
437#define QH_XACTERR_MAX 32
438
439 u8 unlink_reason;
440#define QH_UNLINK_HALTED 0x01
441#define QH_UNLINK_SHORT_READ 0x02
442#define QH_UNLINK_DUMMY_OVERLAY 0x04
443#define QH_UNLINK_SHUTDOWN 0x08
444#define QH_UNLINK_QUEUE_EMPTY 0x10
445#define QH_UNLINK_REQUESTED 0x20
446
447 u8 gap_uf;
448
449 unsigned is_out:1;
450 unsigned clearing_tt:1;
451 unsigned dequeue_during_giveback:1;
452 unsigned should_be_inactive:1;
453};
454
455
456
457
458struct ehci_iso_packet {
459
460 u64 bufp;
461 __hc32 transaction;
462 u8 cross;
463
464 u32 buf1;
465};
466
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468
469
470
471struct ehci_iso_sched {
472 struct list_head td_list;
473 unsigned span;
474 unsigned first_packet;
475 struct ehci_iso_packet packet[0];
476};
477
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479
480
481
482struct ehci_iso_stream {
483
484 struct ehci_qh_hw *hw;
485
486 u8 bEndpointAddress;
487 u8 highspeed;
488 struct list_head td_list;
489 struct list_head free_list;
490
491
492 struct ehci_per_sched ps;
493 unsigned next_uframe;
494 __hc32 splits;
495
496
497
498
499 u16 uperiod;
500 u16 maxp;
501 unsigned bandwidth;
502
503
504 __hc32 buf0;
505 __hc32 buf1;
506 __hc32 buf2;
507
508
509 __hc32 address;
510};
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519
520struct ehci_itd {
521
522 __hc32 hw_next;
523 __hc32 hw_transaction[8];
524#define EHCI_ISOC_ACTIVE (1<<31)
525#define EHCI_ISOC_BUF_ERR (1<<30)
526#define EHCI_ISOC_BABBLE (1<<29)
527#define EHCI_ISOC_XACTERR (1<<28)
528#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
529#define EHCI_ITD_IOC (1 << 15)
530
531#define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
532
533 __hc32 hw_bufp[7];
534 __hc32 hw_bufp_hi[7];
535
536
537 dma_addr_t itd_dma;
538 union ehci_shadow itd_next;
539
540 struct urb *urb;
541 struct ehci_iso_stream *stream;
542 struct list_head itd_list;
543
544
545 unsigned frame;
546 unsigned pg;
547 unsigned index[8];
548} __aligned(32);
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557
558struct ehci_sitd {
559
560 __hc32 hw_next;
561
562 __hc32 hw_fullspeed_ep;
563 __hc32 hw_uframe;
564 __hc32 hw_results;
565#define SITD_IOC (1 << 31)
566#define SITD_PAGE (1 << 30)
567#define SITD_LENGTH(x) (((x) >> 16) & 0x3ff)
568#define SITD_STS_ACTIVE (1 << 7)
569#define SITD_STS_ERR (1 << 6)
570#define SITD_STS_DBE (1 << 5)
571#define SITD_STS_BABBLE (1 << 4)
572#define SITD_STS_XACT (1 << 3)
573#define SITD_STS_MMF (1 << 2)
574#define SITD_STS_STS (1 << 1)
575
576#define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
577
578 __hc32 hw_buf[2];
579 __hc32 hw_backpointer;
580 __hc32 hw_buf_hi[2];
581
582
583 dma_addr_t sitd_dma;
584 union ehci_shadow sitd_next;
585
586 struct urb *urb;
587 struct ehci_iso_stream *stream;
588 struct list_head sitd_list;
589 unsigned frame;
590 unsigned index;
591} __aligned(32);
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603
604struct ehci_fstn {
605 __hc32 hw_next;
606 __hc32 hw_prev;
607
608
609 dma_addr_t fstn_dma;
610 union ehci_shadow fstn_next;
611} __aligned(32);
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632
633struct ehci_tt {
634 u16 bandwidth[EHCI_BANDWIDTH_FRAMES];
635
636 struct list_head tt_list;
637 struct list_head ps_list;
638 struct usb_tt *usb_tt;
639 int tt_port;
640};
641
642
643
644
645
646#define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
647 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup)
648
649#define ehci_prepare_ports_for_controller_resume(ehci) \
650 ehci_adjust_port_wakeup_flags(ehci, false, false)
651
652
653
654#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
655
656
657
658
659
660
661
662
663#define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
664
665
666static inline unsigned int
667ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
668{
669 if (ehci_is_TDI(ehci)) {
670 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
671 case 0:
672 return 0;
673 case 1:
674 return USB_PORT_STAT_LOW_SPEED;
675 case 2:
676 default:
677 return USB_PORT_STAT_HIGH_SPEED;
678 }
679 }
680 return USB_PORT_STAT_HIGH_SPEED;
681}
682
683#else
684
685#define ehci_is_TDI(e) (0)
686
687#define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
688#endif
689
690
691
692#ifdef CONFIG_PPC_83xx
693
694
695
696#define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
697#else
698#define ehci_has_fsl_portno_bug(e) (0)
699#endif
700
701#define PORTSC_FSL_PFSC 24
702
703#if defined(CONFIG_PPC_85xx)
704
705
706
707#define ehci_has_fsl_hs_errata(e) ((e)->has_fsl_hs_errata)
708#else
709#define ehci_has_fsl_hs_errata(e) (0)
710#endif
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724
725
726#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
727#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
728#define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
729#else
730#define ehci_big_endian_mmio(e) 0
731#define ehci_big_endian_capbase(e) 0
732#endif
733
734
735
736
737
738#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
739#define readl_be(addr) __raw_readl((__force unsigned *)addr)
740#define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
741#endif
742
743static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
744 __u32 __iomem *regs)
745{
746#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
747 return ehci_big_endian_mmio(ehci) ?
748 readl_be(regs) :
749 readl(regs);
750#else
751 return readl(regs);
752#endif
753}
754
755#ifdef CONFIG_SOC_IMX28
756static inline void imx28_ehci_writel(const unsigned int val,
757 volatile __u32 __iomem *addr)
758{
759 __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
760}
761#else
762static inline void imx28_ehci_writel(const unsigned int val,
763 volatile __u32 __iomem *addr)
764{
765}
766#endif
767static inline void ehci_writel(const struct ehci_hcd *ehci,
768 const unsigned int val, __u32 __iomem *regs)
769{
770#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
771 ehci_big_endian_mmio(ehci) ?
772 writel_be(val, regs) :
773 writel(val, regs);
774#else
775 if (ehci->imx28_write_fix)
776 imx28_ehci_writel(val, regs);
777 else
778 writel(val, regs);
779#endif
780}
781
782
783
784
785
786
787#ifdef CONFIG_44x
788static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
789{
790 u32 hc_control;
791
792 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
793 if (operational)
794 hc_control |= OHCI_USB_OPER;
795 else
796 hc_control |= OHCI_USB_SUSPEND;
797
798 writel_be(hc_control, ehci->ohci_hcctrl_reg);
799 (void) readl_be(ehci->ohci_hcctrl_reg);
800}
801#else
802static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
803{ }
804#endif
805
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813
814
815#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
816#define ehci_big_endian_desc(e) ((e)->big_endian_desc)
817
818
819static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
820{
821 return ehci_big_endian_desc(ehci)
822 ? (__force __hc32)cpu_to_be32(x)
823 : (__force __hc32)cpu_to_le32(x);
824}
825
826
827static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
828{
829 return ehci_big_endian_desc(ehci)
830 ? be32_to_cpu((__force __be32)x)
831 : le32_to_cpu((__force __le32)x);
832}
833
834static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
835{
836 return ehci_big_endian_desc(ehci)
837 ? be32_to_cpup((__force __be32 *)x)
838 : le32_to_cpup((__force __le32 *)x);
839}
840
841#else
842
843
844static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
845{
846 return cpu_to_le32(x);
847}
848
849
850static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
851{
852 return le32_to_cpu(x);
853}
854
855static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
856{
857 return le32_to_cpup(x);
858}
859
860#endif
861
862
863
864#define ehci_dbg(ehci, fmt, args...) \
865 dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
866#define ehci_err(ehci, fmt, args...) \
867 dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
868#define ehci_info(ehci, fmt, args...) \
869 dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
870#define ehci_warn(ehci, fmt, args...) \
871 dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
872
873
874
875
876
877struct ehci_driver_overrides {
878 size_t extra_priv_size;
879 int (*reset)(struct usb_hcd *hcd);
880 int (*port_power)(struct usb_hcd *hcd,
881 int portnum, bool enable);
882};
883
884extern void ehci_init_driver(struct hc_driver *drv,
885 const struct ehci_driver_overrides *over);
886extern int ehci_setup(struct usb_hcd *hcd);
887extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
888 u32 mask, u32 done, int usec);
889extern int ehci_reset(struct ehci_hcd *ehci);
890
891extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup);
892extern int ehci_resume(struct usb_hcd *hcd, bool force_reset);
893extern void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
894 bool suspending, bool do_wakeup);
895
896extern int ehci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
897 u16 wIndex, char *buf, u16 wLength);
898
899#endif
900