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8
9
10#include <linux/irq.h>
11#include <linux/slab.h>
12
13static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
14{
15 int last = urb_priv->length - 1;
16
17 if (last >= 0) {
18 int i;
19 struct td *td;
20
21 for (i = 0; i <= last; i++) {
22 td = urb_priv->td [i];
23 if (td)
24 td_free (hc, td);
25 }
26 }
27
28 list_del (&urb_priv->pending);
29 kfree (urb_priv);
30}
31
32
33
34
35
36
37
38
39static void
40finish_urb(struct ohci_hcd *ohci, struct urb *urb, int status)
41__releases(ohci->lock)
42__acquires(ohci->lock)
43{
44 struct device *dev = ohci_to_hcd(ohci)->self.controller;
45 struct usb_host_endpoint *ep = urb->ep;
46 struct urb_priv *urb_priv;
47
48
49
50 restart:
51 urb_free_priv (ohci, urb->hcpriv);
52 urb->hcpriv = NULL;
53 if (likely(status == -EINPROGRESS))
54 status = 0;
55
56 switch (usb_pipetype (urb->pipe)) {
57 case PIPE_ISOCHRONOUS:
58 ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
59 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
60 if (quirk_amdiso(ohci))
61 usb_amd_quirk_pll_enable();
62 if (quirk_amdprefetch(ohci))
63 sb800_prefetch(dev, 0);
64 }
65 break;
66 case PIPE_INTERRUPT:
67 ohci_to_hcd(ohci)->self.bandwidth_int_reqs--;
68 break;
69 }
70
71
72 usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci), urb);
73 spin_unlock (&ohci->lock);
74 usb_hcd_giveback_urb(ohci_to_hcd(ohci), urb, status);
75 spin_lock (&ohci->lock);
76
77
78 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
79 && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) {
80 ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE);
81 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
82 }
83
84
85
86
87
88
89
90 if (!list_empty(&ep->urb_list)) {
91 urb = list_first_entry(&ep->urb_list, struct urb, urb_list);
92 urb_priv = urb->hcpriv;
93 if (urb_priv->td_cnt > urb_priv->length) {
94 status = 0;
95 goto restart;
96 }
97 }
98}
99
100
101
102
103
104
105
106
107
108static int balance (struct ohci_hcd *ohci, int interval, int load)
109{
110 int i, branch = -ENOSPC;
111
112
113 if (interval > NUM_INTS)
114 interval = NUM_INTS;
115
116
117
118
119 for (i = 0; i < interval ; i++) {
120 if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
121 int j;
122
123
124 for (j = i; j < NUM_INTS; j += interval) {
125 if ((ohci->load [j] + load) > 900)
126 break;
127 }
128 if (j < NUM_INTS)
129 continue;
130 branch = i;
131 }
132 }
133 return branch;
134}
135
136
137
138
139
140
141
142static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
143{
144 unsigned i;
145
146 ohci_dbg(ohci, "link %sed %p branch %d [%dus.], interval %d\n",
147 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
148 ed, ed->branch, ed->load, ed->interval);
149
150 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
151 struct ed **prev = &ohci->periodic [i];
152 __hc32 *prev_p = &ohci->hcca->int_table [i];
153 struct ed *here = *prev;
154
155
156
157
158
159 while (here && ed != here) {
160 if (ed->interval > here->interval)
161 break;
162 prev = &here->ed_next;
163 prev_p = &here->hwNextED;
164 here = *prev;
165 }
166 if (ed != here) {
167 ed->ed_next = here;
168 if (here)
169 ed->hwNextED = *prev_p;
170 wmb ();
171 *prev = ed;
172 *prev_p = cpu_to_hc32(ohci, ed->dma);
173 wmb();
174 }
175 ohci->load [i] += ed->load;
176 }
177 ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval;
178}
179
180
181
182static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
183{
184 int branch;
185
186 ed->state = ED_OPER;
187 ed->ed_prev = NULL;
188 ed->ed_next = NULL;
189 ed->hwNextED = 0;
190 wmb ();
191
192
193
194
195
196
197
198
199
200
201
202 switch (ed->type) {
203 case PIPE_CONTROL:
204 if (ohci->ed_controltail == NULL) {
205 WARN_ON (ohci->hc_control & OHCI_CTRL_CLE);
206 ohci_writel (ohci, ed->dma,
207 &ohci->regs->ed_controlhead);
208 } else {
209 ohci->ed_controltail->ed_next = ed;
210 ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci,
211 ed->dma);
212 }
213 ed->ed_prev = ohci->ed_controltail;
214 if (!ohci->ed_controltail && !ohci->ed_rm_list) {
215 wmb();
216 ohci->hc_control |= OHCI_CTRL_CLE;
217 ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent);
218 ohci_writel (ohci, ohci->hc_control,
219 &ohci->regs->control);
220 }
221 ohci->ed_controltail = ed;
222 break;
223
224 case PIPE_BULK:
225 if (ohci->ed_bulktail == NULL) {
226 WARN_ON (ohci->hc_control & OHCI_CTRL_BLE);
227 ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead);
228 } else {
229 ohci->ed_bulktail->ed_next = ed;
230 ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci,
231 ed->dma);
232 }
233 ed->ed_prev = ohci->ed_bulktail;
234 if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
235 wmb();
236 ohci->hc_control |= OHCI_CTRL_BLE;
237 ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent);
238 ohci_writel (ohci, ohci->hc_control,
239 &ohci->regs->control);
240 }
241 ohci->ed_bulktail = ed;
242 break;
243
244
245
246 default:
247 branch = balance (ohci, ed->interval, ed->load);
248 if (branch < 0) {
249 ohci_dbg (ohci,
250 "ERR %d, interval %d msecs, load %d\n",
251 branch, ed->interval, ed->load);
252
253 return branch;
254 }
255 ed->branch = branch;
256 periodic_link (ohci, ed);
257 }
258
259
260
261
262 return 0;
263}
264
265
266
267
268static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
269{
270 int i;
271
272 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
273 struct ed *temp;
274 struct ed **prev = &ohci->periodic [i];
275 __hc32 *prev_p = &ohci->hcca->int_table [i];
276
277 while (*prev && (temp = *prev) != ed) {
278 prev_p = &temp->hwNextED;
279 prev = &temp->ed_next;
280 }
281 if (*prev) {
282 *prev_p = ed->hwNextED;
283 *prev = ed->ed_next;
284 }
285 ohci->load [i] -= ed->load;
286 }
287 ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval;
288
289 ohci_dbg(ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
290 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
291 ed, ed->branch, ed->load, ed->interval);
292}
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
316{
317 ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
318 wmb ();
319 ed->state = ED_UNLINK;
320
321
322
323
324
325
326
327
328
329
330
331 switch (ed->type) {
332 case PIPE_CONTROL:
333
334 if (ed->ed_prev == NULL) {
335 if (!ed->hwNextED) {
336 ohci->hc_control &= ~OHCI_CTRL_CLE;
337 ohci_writel (ohci, ohci->hc_control,
338 &ohci->regs->control);
339
340 } else
341 ohci_writel (ohci,
342 hc32_to_cpup (ohci, &ed->hwNextED),
343 &ohci->regs->ed_controlhead);
344 } else {
345 ed->ed_prev->ed_next = ed->ed_next;
346 ed->ed_prev->hwNextED = ed->hwNextED;
347 }
348
349 if (ohci->ed_controltail == ed) {
350 ohci->ed_controltail = ed->ed_prev;
351 if (ohci->ed_controltail)
352 ohci->ed_controltail->ed_next = NULL;
353 } else if (ed->ed_next) {
354 ed->ed_next->ed_prev = ed->ed_prev;
355 }
356 break;
357
358 case PIPE_BULK:
359
360 if (ed->ed_prev == NULL) {
361 if (!ed->hwNextED) {
362 ohci->hc_control &= ~OHCI_CTRL_BLE;
363 ohci_writel (ohci, ohci->hc_control,
364 &ohci->regs->control);
365
366 } else
367 ohci_writel (ohci,
368 hc32_to_cpup (ohci, &ed->hwNextED),
369 &ohci->regs->ed_bulkhead);
370 } else {
371 ed->ed_prev->ed_next = ed->ed_next;
372 ed->ed_prev->hwNextED = ed->hwNextED;
373 }
374
375 if (ohci->ed_bulktail == ed) {
376 ohci->ed_bulktail = ed->ed_prev;
377 if (ohci->ed_bulktail)
378 ohci->ed_bulktail->ed_next = NULL;
379 } else if (ed->ed_next) {
380 ed->ed_next->ed_prev = ed->ed_prev;
381 }
382 break;
383
384
385
386 default:
387 periodic_unlink (ohci, ed);
388 break;
389 }
390}
391
392
393
394
395
396
397
398static struct ed *ed_get (
399 struct ohci_hcd *ohci,
400 struct usb_host_endpoint *ep,
401 struct usb_device *udev,
402 unsigned int pipe,
403 int interval
404) {
405 struct ed *ed;
406 unsigned long flags;
407
408 spin_lock_irqsave (&ohci->lock, flags);
409
410 ed = ep->hcpriv;
411 if (!ed) {
412 struct td *td;
413 int is_out;
414 u32 info;
415
416 ed = ed_alloc (ohci, GFP_ATOMIC);
417 if (!ed) {
418
419 goto done;
420 }
421
422
423 td = td_alloc (ohci, GFP_ATOMIC);
424 if (!td) {
425
426 ed_free (ohci, ed);
427 ed = NULL;
428 goto done;
429 }
430 ed->dummy = td;
431 ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma);
432 ed->hwHeadP = ed->hwTailP;
433 ed->state = ED_IDLE;
434
435 is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN);
436
437
438
439
440 info = usb_pipedevice (pipe);
441 ed->type = usb_pipetype(pipe);
442
443 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7;
444 info |= usb_endpoint_maxp(&ep->desc) << 16;
445 if (udev->speed == USB_SPEED_LOW)
446 info |= ED_LOWSPEED;
447
448 if (ed->type != PIPE_CONTROL) {
449 info |= is_out ? ED_OUT : ED_IN;
450 if (ed->type != PIPE_BULK) {
451
452 if (ed->type == PIPE_ISOCHRONOUS)
453 info |= ED_ISO;
454 else if (interval > 32)
455 interval = 32;
456 ed->interval = interval;
457 ed->load = usb_calc_bus_time (
458 udev->speed, !is_out,
459 ed->type == PIPE_ISOCHRONOUS,
460 usb_endpoint_maxp(&ep->desc))
461 / 1000;
462 }
463 }
464 ed->hwINFO = cpu_to_hc32(ohci, info);
465
466 ep->hcpriv = ed;
467 }
468
469done:
470 spin_unlock_irqrestore (&ohci->lock, flags);
471 return ed;
472}
473
474
475
476
477
478
479
480
481
482static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed)
483{
484 ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE);
485 ed_deschedule (ohci, ed);
486
487
488 ed->ed_next = ohci->ed_rm_list;
489 ed->ed_prev = NULL;
490 ohci->ed_rm_list = ed;
491
492
493 ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus);
494 ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable);
495
496 (void) ohci_readl (ohci, &ohci->regs->control);
497
498
499
500
501
502
503 ed->tick = ohci_frame_no(ohci) + 1;
504
505}
506
507
508
509
510
511
512
513static void
514td_fill (struct ohci_hcd *ohci, u32 info,
515 dma_addr_t data, int len,
516 struct urb *urb, int index)
517{
518 struct td *td, *td_pt;
519 struct urb_priv *urb_priv = urb->hcpriv;
520 int is_iso = info & TD_ISO;
521 int hash;
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536 if (index != (urb_priv->length - 1)
537 || (urb->transfer_flags & URB_NO_INTERRUPT))
538 info |= TD_DI_SET (6);
539
540
541 td_pt = urb_priv->td [index];
542
543
544 td = urb_priv->td [index] = urb_priv->ed->dummy;
545 urb_priv->ed->dummy = td_pt;
546
547 td->ed = urb_priv->ed;
548 td->next_dl_td = NULL;
549 td->index = index;
550 td->urb = urb;
551 td->data_dma = data;
552 if (!len)
553 data = 0;
554
555 td->hwINFO = cpu_to_hc32 (ohci, info);
556 if (is_iso) {
557 td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000);
558 *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci,
559 (data & 0x0FFF) | 0xE000);
560 } else {
561 td->hwCBP = cpu_to_hc32 (ohci, data);
562 }
563 if (data)
564 td->hwBE = cpu_to_hc32 (ohci, data + len - 1);
565 else
566 td->hwBE = 0;
567 td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma);
568
569
570 list_add_tail (&td->td_list, &td->ed->td_list);
571
572
573 hash = TD_HASH_FUNC (td->td_dma);
574 td->td_hash = ohci->td_hash [hash];
575 ohci->td_hash [hash] = td;
576
577
578 wmb ();
579 td->ed->hwTailP = td->hwNextTD;
580}
581
582
583
584
585
586
587
588
589static void td_submit_urb (
590 struct ohci_hcd *ohci,
591 struct urb *urb
592) {
593 struct urb_priv *urb_priv = urb->hcpriv;
594 struct device *dev = ohci_to_hcd(ohci)->self.controller;
595 dma_addr_t data;
596 int data_len = urb->transfer_buffer_length;
597 int cnt = 0;
598 u32 info = 0;
599 int is_out = usb_pipeout (urb->pipe);
600 int periodic = 0;
601 int i, this_sg_len, n;
602 struct scatterlist *sg;
603
604
605
606
607
608 if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
609 usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
610 is_out, 1);
611 urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C);
612 }
613
614 list_add (&urb_priv->pending, &ohci->pending);
615
616 i = urb->num_mapped_sgs;
617 if (data_len > 0 && i > 0) {
618 sg = urb->sg;
619 data = sg_dma_address(sg);
620
621
622
623
624
625 this_sg_len = min_t(int, sg_dma_len(sg), data_len);
626 } else {
627 sg = NULL;
628 if (data_len)
629 data = urb->transfer_dma;
630 else
631 data = 0;
632 this_sg_len = data_len;
633 }
634
635
636
637
638
639 switch (urb_priv->ed->type) {
640
641
642
643
644 case PIPE_INTERRUPT:
645
646 periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0
647 && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0;
648
649 case PIPE_BULK:
650 info = is_out
651 ? TD_T_TOGGLE | TD_CC | TD_DP_OUT
652 : TD_T_TOGGLE | TD_CC | TD_DP_IN;
653
654 for (;;) {
655 n = min(this_sg_len, 4096);
656
657
658 if (n >= data_len || (i == 1 && n >= this_sg_len)) {
659 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
660 info |= TD_R;
661 }
662 td_fill(ohci, info, data, n, urb, cnt);
663 this_sg_len -= n;
664 data_len -= n;
665 data += n;
666 cnt++;
667
668 if (this_sg_len <= 0) {
669 if (--i <= 0 || data_len <= 0)
670 break;
671 sg = sg_next(sg);
672 data = sg_dma_address(sg);
673 this_sg_len = min_t(int, sg_dma_len(sg),
674 data_len);
675 }
676 }
677 if ((urb->transfer_flags & URB_ZERO_PACKET)
678 && cnt < urb_priv->length) {
679 td_fill (ohci, info, 0, 0, urb, cnt);
680 cnt++;
681 }
682
683 if (urb_priv->ed->type == PIPE_BULK) {
684 wmb ();
685 ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus);
686 }
687 break;
688
689
690
691
692 case PIPE_CONTROL:
693 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
694 td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
695 if (data_len > 0) {
696 info = TD_CC | TD_R | TD_T_DATA1;
697 info |= is_out ? TD_DP_OUT : TD_DP_IN;
698
699 td_fill (ohci, info, data, data_len, urb, cnt++);
700 }
701 info = (is_out || data_len == 0)
702 ? TD_CC | TD_DP_IN | TD_T_DATA1
703 : TD_CC | TD_DP_OUT | TD_T_DATA1;
704 td_fill (ohci, info, data, 0, urb, cnt++);
705
706 wmb ();
707 ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus);
708 break;
709
710
711
712
713
714 case PIPE_ISOCHRONOUS:
715 for (cnt = urb_priv->td_cnt; cnt < urb->number_of_packets;
716 cnt++) {
717 int frame = urb->start_frame;
718
719
720
721
722 frame += cnt * urb->interval;
723 frame &= 0xffff;
724 td_fill (ohci, TD_CC | TD_ISO | frame,
725 data + urb->iso_frame_desc [cnt].offset,
726 urb->iso_frame_desc [cnt].length, urb, cnt);
727 }
728 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
729 if (quirk_amdiso(ohci))
730 usb_amd_quirk_pll_disable();
731 if (quirk_amdprefetch(ohci))
732 sb800_prefetch(dev, 1);
733 }
734 periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
735 && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
736 break;
737 }
738
739
740 if (periodic) {
741 wmb ();
742 ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
743 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
744 }
745
746
747}
748
749
750
751
752
753
754static int td_done(struct ohci_hcd *ohci, struct urb *urb, struct td *td)
755{
756 u32 tdINFO = hc32_to_cpup (ohci, &td->hwINFO);
757 int cc = 0;
758 int status = -EINPROGRESS;
759
760 list_del (&td->td_list);
761
762
763 if (tdINFO & TD_ISO) {
764 u16 tdPSW = ohci_hwPSW(ohci, td, 0);
765 int dlen = 0;
766
767
768
769
770
771 cc = (tdPSW >> 12) & 0xF;
772 if (tdINFO & TD_CC)
773 return status;
774
775 if (usb_pipeout (urb->pipe))
776 dlen = urb->iso_frame_desc [td->index].length;
777 else {
778
779 if (cc == TD_DATAUNDERRUN)
780 cc = TD_CC_NOERROR;
781 dlen = tdPSW & 0x3ff;
782 }
783 urb->actual_length += dlen;
784 urb->iso_frame_desc [td->index].actual_length = dlen;
785 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
786
787 if (cc != TD_CC_NOERROR)
788 ohci_dbg(ohci,
789 "urb %p iso td %p (%d) len %d cc %d\n",
790 urb, td, 1 + td->index, dlen, cc);
791
792
793
794
795
796 } else {
797 int type = usb_pipetype (urb->pipe);
798 u32 tdBE = hc32_to_cpup (ohci, &td->hwBE);
799
800 cc = TD_CC_GET (tdINFO);
801
802
803 if (cc == TD_DATAUNDERRUN
804 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
805 cc = TD_CC_NOERROR;
806 if (cc != TD_CC_NOERROR && cc < 0x0E)
807 status = cc_to_error[cc];
808
809
810 if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
811 if (td->hwCBP == 0)
812 urb->actual_length += tdBE - td->data_dma + 1;
813 else
814 urb->actual_length +=
815 hc32_to_cpup (ohci, &td->hwCBP)
816 - td->data_dma;
817 }
818
819 if (cc != TD_CC_NOERROR && cc < 0x0E)
820 ohci_dbg(ohci,
821 "urb %p td %p (%d) cc %d, len=%d/%d\n",
822 urb, td, 1 + td->index, cc,
823 urb->actual_length,
824 urb->transfer_buffer_length);
825 }
826 return status;
827}
828
829
830
831static void ed_halted(struct ohci_hcd *ohci, struct td *td, int cc)
832{
833 struct urb *urb = td->urb;
834 urb_priv_t *urb_priv = urb->hcpriv;
835 struct ed *ed = td->ed;
836 struct list_head *tmp = td->td_list.next;
837 __hc32 toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C);
838
839
840
841
842 ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
843 wmb ();
844 ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H);
845
846
847
848
849
850 while (tmp != &ed->td_list) {
851 struct td *next;
852
853 next = list_entry (tmp, struct td, td_list);
854 tmp = next->td_list.next;
855
856 if (next->urb != urb)
857 break;
858
859
860
861
862
863
864
865
866
867 list_del(&next->td_list);
868 urb_priv->td_cnt++;
869 ed->hwHeadP = next->hwNextTD | toggle;
870 }
871
872
873
874
875
876 switch (cc) {
877 case TD_DATAUNDERRUN:
878 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
879 break;
880
881 case TD_CC_STALL:
882 if (usb_pipecontrol (urb->pipe))
883 break;
884
885 default:
886 ohci_dbg (ohci,
887 "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
888 urb, urb->dev->devpath,
889 usb_pipeendpoint (urb->pipe),
890 usb_pipein (urb->pipe) ? "in" : "out",
891 hc32_to_cpu (ohci, td->hwINFO),
892 cc, cc_to_error [cc]);
893 }
894}
895
896
897static void add_to_done_list(struct ohci_hcd *ohci, struct td *td)
898{
899 struct td *td2, *td_prev;
900 struct ed *ed;
901
902 if (td->next_dl_td)
903 return;
904
905
906 ed = td->ed;
907 td2 = td_prev = td;
908 list_for_each_entry_continue_reverse(td2, &ed->td_list, td_list) {
909 if (td2->next_dl_td)
910 break;
911 td2->next_dl_td = td_prev;
912 td_prev = td2;
913 }
914
915 if (ohci->dl_end)
916 ohci->dl_end->next_dl_td = td_prev;
917 else
918 ohci->dl_start = td_prev;
919
920
921
922
923
924 ohci->dl_end = td->next_dl_td = td;
925
926
927 td2 = ed->pending_td;
928 if (td2 && td2->next_dl_td)
929 ed->pending_td = NULL;
930}
931
932
933static void update_done_list(struct ohci_hcd *ohci)
934{
935 u32 td_dma;
936 struct td *td = NULL;
937
938 td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head);
939 ohci->hcca->done_head = 0;
940 wmb();
941
942
943
944
945 while (td_dma) {
946 int cc;
947
948 td = dma_to_td (ohci, td_dma);
949 if (!td) {
950 ohci_err (ohci, "bad entry %8x\n", td_dma);
951 break;
952 }
953
954 td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE);
955 cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO));
956
957
958
959
960
961 if (cc != TD_CC_NOERROR
962 && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H)))
963 ed_halted(ohci, td, cc);
964
965 td_dma = hc32_to_cpup (ohci, &td->hwNextTD);
966 add_to_done_list(ohci, td);
967 }
968}
969
970
971
972
973static void finish_unlinks(struct ohci_hcd *ohci)
974{
975 unsigned tick = ohci_frame_no(ohci);
976 struct ed *ed, **last;
977
978rescan_all:
979 for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
980 struct list_head *entry, *tmp;
981 int completed, modified;
982 __hc32 *prev;
983
984
985
986
987 if (likely(ohci->rh_state == OHCI_RH_RUNNING) &&
988 tick_before(tick, ed->tick)) {
989skip_ed:
990 last = &ed->ed_next;
991 continue;
992 }
993 if (!list_empty(&ed->td_list)) {
994 struct td *td;
995 u32 head;
996
997 td = list_first_entry(&ed->td_list, struct td, td_list);
998
999
1000 head = hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK;
1001 if (td->td_dma != head &&
1002 ohci->rh_state == OHCI_RH_RUNNING)
1003 goto skip_ed;
1004
1005
1006 if (td->next_dl_td)
1007 goto skip_ed;
1008 }
1009
1010
1011 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H);
1012 ed->hwNextED = 0;
1013 wmb();
1014 ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE);
1015
1016
1017
1018
1019
1020 modified = 0;
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030rescan_this:
1031 completed = 0;
1032 prev = &ed->hwHeadP;
1033 list_for_each_safe (entry, tmp, &ed->td_list) {
1034 struct td *td;
1035 struct urb *urb;
1036 urb_priv_t *urb_priv;
1037 __hc32 savebits;
1038 u32 tdINFO;
1039
1040 td = list_entry (entry, struct td, td_list);
1041 urb = td->urb;
1042 urb_priv = td->urb->hcpriv;
1043
1044 if (!urb->unlinked) {
1045 prev = &td->hwNextTD;
1046 continue;
1047 }
1048
1049
1050 savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK);
1051 *prev = td->hwNextTD | savebits;
1052
1053
1054
1055
1056
1057
1058 tdINFO = hc32_to_cpup(ohci, &td->hwINFO);
1059 if ((tdINFO & TD_T) == TD_T_DATA0)
1060 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_C);
1061 else if ((tdINFO & TD_T) == TD_T_DATA1)
1062 ed->hwHeadP |= cpu_to_hc32(ohci, ED_C);
1063
1064
1065 td_done (ohci, urb, td);
1066 urb_priv->td_cnt++;
1067
1068
1069 if (urb_priv->td_cnt >= urb_priv->length) {
1070 modified = completed = 1;
1071 finish_urb(ohci, urb, 0);
1072 }
1073 }
1074 if (completed && !list_empty (&ed->td_list))
1075 goto rescan_this;
1076
1077
1078
1079
1080
1081
1082 if (list_empty(&ed->td_list)) {
1083 *last = ed->ed_next;
1084 ed->ed_next = NULL;
1085 ed->state = ED_IDLE;
1086 list_del(&ed->in_use_list);
1087 } else if (ohci->rh_state == OHCI_RH_RUNNING) {
1088 *last = ed->ed_next;
1089 ed->ed_next = NULL;
1090 ed_schedule(ohci, ed);
1091 } else {
1092 last = &ed->ed_next;
1093 }
1094
1095 if (modified)
1096 goto rescan_all;
1097 }
1098
1099
1100 if (ohci->rh_state == OHCI_RH_RUNNING && !ohci->ed_rm_list) {
1101 u32 command = 0, control = 0;
1102
1103 if (ohci->ed_controltail) {
1104 command |= OHCI_CLF;
1105 if (quirk_zfmicro(ohci))
1106 mdelay(1);
1107 if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
1108 control |= OHCI_CTRL_CLE;
1109 ohci_writel (ohci, 0,
1110 &ohci->regs->ed_controlcurrent);
1111 }
1112 }
1113 if (ohci->ed_bulktail) {
1114 command |= OHCI_BLF;
1115 if (quirk_zfmicro(ohci))
1116 mdelay(1);
1117 if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
1118 control |= OHCI_CTRL_BLE;
1119 ohci_writel (ohci, 0,
1120 &ohci->regs->ed_bulkcurrent);
1121 }
1122 }
1123
1124
1125 if (control) {
1126 ohci->hc_control |= control;
1127 if (quirk_zfmicro(ohci))
1128 mdelay(1);
1129 ohci_writel (ohci, ohci->hc_control,
1130 &ohci->regs->control);
1131 }
1132 if (command) {
1133 if (quirk_zfmicro(ohci))
1134 mdelay(1);
1135 ohci_writel (ohci, command, &ohci->regs->cmdstatus);
1136 }
1137 }
1138}
1139
1140
1141
1142
1143
1144
1145static void takeback_td(struct ohci_hcd *ohci, struct td *td)
1146{
1147 struct urb *urb = td->urb;
1148 urb_priv_t *urb_priv = urb->hcpriv;
1149 struct ed *ed = td->ed;
1150 int status;
1151
1152
1153 status = td_done(ohci, urb, td);
1154 urb_priv->td_cnt++;
1155
1156
1157 if (urb_priv->td_cnt >= urb_priv->length)
1158 finish_urb(ohci, urb, status);
1159
1160
1161 if (list_empty(&ed->td_list)) {
1162 if (ed->state == ED_OPER)
1163 start_ed_unlink(ohci, ed);
1164
1165
1166 } else if ((ed->hwINFO & cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE))
1167 == cpu_to_hc32(ohci, ED_SKIP)) {
1168 td = list_entry(ed->td_list.next, struct td, td_list);
1169 if (!(td->hwINFO & cpu_to_hc32(ohci, TD_DONE))) {
1170 ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP);
1171
1172 switch (ed->type) {
1173 case PIPE_CONTROL:
1174 ohci_writel(ohci, OHCI_CLF,
1175 &ohci->regs->cmdstatus);
1176 break;
1177 case PIPE_BULK:
1178 ohci_writel(ohci, OHCI_BLF,
1179 &ohci->regs->cmdstatus);
1180 break;
1181 }
1182 }
1183 }
1184}
1185
1186
1187
1188
1189
1190
1191
1192
1193static void process_done_list(struct ohci_hcd *ohci)
1194{
1195 struct td *td;
1196
1197 while (ohci->dl_start) {
1198 td = ohci->dl_start;
1199 if (td == ohci->dl_end)
1200 ohci->dl_start = ohci->dl_end = NULL;
1201 else
1202 ohci->dl_start = td->next_dl_td;
1203
1204 takeback_td(ohci, td);
1205 }
1206}
1207
1208
1209
1210
1211
1212static void ohci_work(struct ohci_hcd *ohci)
1213{
1214 if (ohci->working) {
1215 ohci->restart_work = 1;
1216 return;
1217 }
1218 ohci->working = 1;
1219
1220 restart:
1221 process_done_list(ohci);
1222 if (ohci->ed_rm_list)
1223 finish_unlinks(ohci);
1224
1225 if (ohci->restart_work) {
1226 ohci->restart_work = 0;
1227 goto restart;
1228 }
1229 ohci->working = 0;
1230}
1231