1#ifndef __LINUX_OMAP_DMA_H
2#define __LINUX_OMAP_DMA_H
3#include <linux/omap-dmaengine.h>
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17
18#include <linux/platform_device.h>
19
20#define INT_DMA_LCD (NR_IRQS_LEGACY + 25)
21
22#define OMAP1_DMA_TOUT_IRQ (1 << 0)
23#define OMAP_DMA_DROP_IRQ (1 << 1)
24#define OMAP_DMA_HALF_IRQ (1 << 2)
25#define OMAP_DMA_FRAME_IRQ (1 << 3)
26#define OMAP_DMA_LAST_IRQ (1 << 4)
27#define OMAP_DMA_BLOCK_IRQ (1 << 5)
28#define OMAP1_DMA_SYNC_IRQ (1 << 6)
29#define OMAP2_DMA_PKT_IRQ (1 << 7)
30#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
31#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
32#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
33#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
34
35#define OMAP_DMA_CCR_EN (1 << 7)
36#define OMAP_DMA_CCR_RD_ACTIVE (1 << 9)
37#define OMAP_DMA_CCR_WR_ACTIVE (1 << 10)
38#define OMAP_DMA_CCR_SEL_SRC_DST_SYNC (1 << 24)
39#define OMAP_DMA_CCR_BUFFERING_DISABLE (1 << 25)
40
41#define OMAP_DMA_DATA_TYPE_S8 0x00
42#define OMAP_DMA_DATA_TYPE_S16 0x01
43#define OMAP_DMA_DATA_TYPE_S32 0x02
44
45#define OMAP_DMA_SYNC_ELEMENT 0x00
46#define OMAP_DMA_SYNC_FRAME 0x01
47#define OMAP_DMA_SYNC_BLOCK 0x02
48#define OMAP_DMA_SYNC_PACKET 0x03
49
50#define OMAP_DMA_DST_SYNC_PREFETCH 0x02
51#define OMAP_DMA_SRC_SYNC 0x01
52#define OMAP_DMA_DST_SYNC 0x00
53
54#define OMAP_DMA_PORT_EMIFF 0x00
55#define OMAP_DMA_PORT_EMIFS 0x01
56#define OMAP_DMA_PORT_OCP_T1 0x02
57#define OMAP_DMA_PORT_TIPB 0x03
58#define OMAP_DMA_PORT_OCP_T2 0x04
59#define OMAP_DMA_PORT_MPUI 0x05
60
61#define OMAP_DMA_AMODE_CONSTANT 0x00
62#define OMAP_DMA_AMODE_POST_INC 0x01
63#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
64#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
65
66#define DMA_DEFAULT_FIFO_DEPTH 0x10
67#define DMA_DEFAULT_ARB_RATE 0x01
68
69#define DMA_THREAD_RESERVE_NORM (0x00 << 12)
70#define DMA_THREAD_RESERVE_ONET (0x01 << 12)
71#define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
72#define DMA_THREAD_RESERVE_THREET (0x03 << 12)
73#define DMA_THREAD_FIFO_NONE (0x00 << 14)
74#define DMA_THREAD_FIFO_75 (0x01 << 14)
75#define DMA_THREAD_FIFO_25 (0x02 << 14)
76#define DMA_THREAD_FIFO_50 (0x03 << 14)
77
78
79#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12)
80#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
81#define DMA_SYSCONFIG_EMUFREE (1 << 5)
82#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3)
83#define DMA_SYSCONFIG_SOFTRESET (1 << 2)
84#define DMA_SYSCONFIG_AUTOIDLE (1 << 0)
85
86#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12)
87#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3)
88
89#define DMA_IDLEMODE_SMARTIDLE 0x2
90#define DMA_IDLEMODE_NO_IDLE 0x1
91#define DMA_IDLEMODE_FORCE_IDLE 0x0
92
93
94#ifndef CONFIG_ARCH_OMAP1
95#define OMAP_DMA_STATIC_CHAIN 0x1
96#define OMAP_DMA_DYNAMIC_CHAIN 0x2
97#define OMAP_DMA_CHAIN_ACTIVE 0x1
98#define OMAP_DMA_CHAIN_INACTIVE 0x0
99#endif
100
101#define DMA_CH_PRIO_HIGH 0x1
102#define DMA_CH_PRIO_LOW 0x0
103
104
105#define IS_DMA_ERRATA(id) (errata & (id))
106#define SET_DMA_ERRATA(id) (errata |= (id))
107
108#define DMA_ERRATA_IFRAME_BUFFERING BIT(0x0)
109#define DMA_ERRATA_PARALLEL_CHANNELS BIT(0x1)
110#define DMA_ERRATA_i378 BIT(0x2)
111#define DMA_ERRATA_i541 BIT(0x3)
112#define DMA_ERRATA_i88 BIT(0x4)
113#define DMA_ERRATA_3_3 BIT(0x5)
114#define DMA_ROMCODE_BUG BIT(0x6)
115
116
117#define DMA_LINKED_LCH BIT(0x0)
118#define GLOBAL_PRIORITY BIT(0x1)
119#define RESERVE_CHANNEL BIT(0x2)
120#define IS_CSSA_32 BIT(0x3)
121#define IS_CDSA_32 BIT(0x4)
122#define IS_RW_PRIORITY BIT(0x5)
123#define ENABLE_1510_MODE BIT(0x6)
124#define SRC_PORT BIT(0x7)
125#define DST_PORT BIT(0x8)
126#define SRC_INDEX BIT(0x9)
127#define DST_INDEX BIT(0xa)
128#define IS_BURST_ONLY4 BIT(0xb)
129#define CLEAR_CSR_ON_READ BIT(0xc)
130#define IS_WORD_16 BIT(0xd)
131#define ENABLE_16XX_MODE BIT(0xe)
132#define HS_CHANNELS_RESERVED BIT(0xf)
133#define DMA_ENGINE_HANDLE_IRQ BIT(0x10)
134
135
136#define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18)
137#define DMA_HAS_CONSTANT_FILL_CAPS (0x1 << 19)
138#define DMA_HAS_DESCRIPTOR_CAPS (0x3 << 20)
139
140enum omap_reg_offsets {
141
142GCR, GSCR, GRST1, HW_ID,
143PCH2_ID, PCH0_ID, PCH1_ID, PCHG_ID,
144PCHD_ID, CAPS_0, CAPS_1, CAPS_2,
145CAPS_3, CAPS_4, PCH2_SR, PCH0_SR,
146PCH1_SR, PCHD_SR, REVISION, IRQSTATUS_L0,
147IRQSTATUS_L1, IRQSTATUS_L2, IRQSTATUS_L3, IRQENABLE_L0,
148IRQENABLE_L1, IRQENABLE_L2, IRQENABLE_L3, SYSSTATUS,
149OCP_SYSCONFIG,
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151
152CPC, CCR2, LCH_CTRL,
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154
155CSDP, CCR, CICR, CSR,
156CEN, CFN, CSFI, CSEI,
157CSAC, CDAC, CDEI,
158CDFI, CLNK_CTRL,
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160
161CSSA, CDSA, COLOR,
162CCEN, CCFN,
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164
165CDP, CNDP, CCDN,
166
167};
168
169enum omap_dma_burst_mode {
170 OMAP_DMA_DATA_BURST_DIS = 0,
171 OMAP_DMA_DATA_BURST_4,
172 OMAP_DMA_DATA_BURST_8,
173 OMAP_DMA_DATA_BURST_16,
174};
175
176enum end_type {
177 OMAP_DMA_LITTLE_ENDIAN = 0,
178 OMAP_DMA_BIG_ENDIAN
179};
180
181enum omap_dma_color_mode {
182 OMAP_DMA_COLOR_DIS = 0,
183 OMAP_DMA_CONSTANT_FILL,
184 OMAP_DMA_TRANSPARENT_COPY
185};
186
187enum omap_dma_write_mode {
188 OMAP_DMA_WRITE_NON_POSTED = 0,
189 OMAP_DMA_WRITE_POSTED,
190 OMAP_DMA_WRITE_LAST_NON_POSTED
191};
192
193enum omap_dma_channel_mode {
194 OMAP_DMA_LCH_2D = 0,
195 OMAP_DMA_LCH_G,
196 OMAP_DMA_LCH_P,
197 OMAP_DMA_LCH_PD
198};
199
200struct omap_dma_channel_params {
201 int data_type;
202 int elem_count;
203 int frame_count;
204
205 int src_port;
206 int src_amode;
207
208 unsigned long src_start;
209 int src_ei;
210 int src_fi;
211
212 int dst_port;
213 int dst_amode;
214
215 unsigned long dst_start;
216 int dst_ei;
217 int dst_fi;
218
219 int trigger;
220
221 int sync_mode;
222 int src_or_dst_synch;
223
224 int ie;
225
226 unsigned char read_prio;
227 unsigned char write_prio;
228
229#ifndef CONFIG_ARCH_OMAP1
230 enum omap_dma_burst_mode burst_mode;
231#endif
232};
233
234struct omap_dma_lch {
235 int next_lch;
236 int dev_id;
237 u16 saved_csr;
238 u16 enabled_irqs;
239 const char *dev_name;
240 void (*callback)(int lch, u16 ch_status, void *data);
241 void *data;
242 long flags;
243
244 int prev_linked_ch;
245 int next_linked_ch;
246 int state;
247 int chain_id;
248 int status;
249};
250
251struct omap_dma_dev_attr {
252 u32 dev_caps;
253 u16 lch_count;
254 u16 chan_count;
255};
256
257enum {
258 OMAP_DMA_REG_NONE,
259 OMAP_DMA_REG_16BIT,
260 OMAP_DMA_REG_2X16BIT,
261 OMAP_DMA_REG_32BIT,
262};
263
264struct omap_dma_reg {
265 u16 offset;
266 u8 stride;
267 u8 type;
268};
269
270#define SDMA_FILTER_PARAM(hw_req) ((int[]) { (hw_req) })
271struct dma_slave_map;
272
273
274struct omap_system_dma_plat_info {
275 const struct omap_dma_reg *reg_map;
276 unsigned channel_stride;
277 struct omap_dma_dev_attr *dma_attr;
278 u32 errata;
279 void (*show_dma_caps)(void);
280 void (*clear_lch_regs)(int lch);
281 void (*clear_dma)(int lch);
282 void (*dma_write)(u32 val, int reg, int lch);
283 u32 (*dma_read)(int reg, int lch);
284
285 const struct dma_slave_map *slave_map;
286 int slavecnt;
287};
288
289#ifdef CONFIG_ARCH_OMAP2PLUS
290#define dma_omap2plus() 1
291#else
292#define dma_omap2plus() 0
293#endif
294#define dma_omap1() (!dma_omap2plus())
295#define __dma_omap15xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_1510_MODE)
296#define __dma_omap16xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_16XX_MODE)
297#define dma_omap15xx() __dma_omap15xx(d)
298#define dma_omap16xx() __dma_omap16xx(d)
299
300extern struct omap_system_dma_plat_info *omap_get_plat_info(void);
301
302extern void omap_set_dma_priority(int lch, int dst_port, int priority);
303extern int omap_request_dma(int dev_id, const char *dev_name,
304 void (*callback)(int lch, u16 ch_status, void *data),
305 void *data, int *dma_ch);
306extern void omap_enable_dma_irq(int ch, u16 irq_bits);
307extern void omap_disable_dma_irq(int ch, u16 irq_bits);
308extern void omap_free_dma(int ch);
309extern void omap_start_dma(int lch);
310extern void omap_stop_dma(int lch);
311extern void omap_set_dma_transfer_params(int lch, int data_type,
312 int elem_count, int frame_count,
313 int sync_mode,
314 int dma_trigger, int src_or_dst_synch);
315extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
316extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
317
318extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
319 unsigned long src_start,
320 int src_ei, int src_fi);
321extern void omap_set_dma_src_data_pack(int lch, int enable);
322extern void omap_set_dma_src_burst_mode(int lch,
323 enum omap_dma_burst_mode burst_mode);
324
325extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
326 unsigned long dest_start,
327 int dst_ei, int dst_fi);
328extern void omap_set_dma_dest_data_pack(int lch, int enable);
329extern void omap_set_dma_dest_burst_mode(int lch,
330 enum omap_dma_burst_mode burst_mode);
331
332extern void omap_set_dma_params(int lch,
333 struct omap_dma_channel_params *params);
334
335extern void omap_dma_link_lch(int lch_head, int lch_queue);
336
337extern int omap_set_dma_callback(int lch,
338 void (*callback)(int lch, u16 ch_status, void *data),
339 void *data);
340extern dma_addr_t omap_get_dma_src_pos(int lch);
341extern dma_addr_t omap_get_dma_dst_pos(int lch);
342extern int omap_get_dma_active_status(int lch);
343extern int omap_dma_running(void);
344extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
345 int tparams);
346void omap_dma_global_context_save(void);
347void omap_dma_global_context_restore(void);
348
349#if defined(CONFIG_ARCH_OMAP1) && IS_ENABLED(CONFIG_FB_OMAP)
350#include <mach/lcd_dma.h>
351#else
352static inline int omap_lcd_dma_running(void)
353{
354 return 0;
355}
356#endif
357
358#endif
359
