1#ifndef __SH_CLOCK_H
2#define __SH_CLOCK_H
3
4#include <linux/list.h>
5#include <linux/seq_file.h>
6#include <linux/cpufreq.h>
7#include <linux/types.h>
8#include <linux/kref.h>
9#include <linux/clk.h>
10#include <linux/err.h>
11
12struct clk;
13
14struct clk_mapping {
15 phys_addr_t phys;
16 void __iomem *base;
17 unsigned long len;
18 struct kref ref;
19};
20
21struct sh_clk_ops {
22#ifdef CONFIG_SH_CLK_CPG_LEGACY
23 void (*init)(struct clk *clk);
24#endif
25 int (*enable)(struct clk *clk);
26 void (*disable)(struct clk *clk);
27 unsigned long (*recalc)(struct clk *clk);
28 int (*set_rate)(struct clk *clk, unsigned long rate);
29 int (*set_parent)(struct clk *clk, struct clk *parent);
30 long (*round_rate)(struct clk *clk, unsigned long rate);
31};
32
33#define SH_CLK_DIV_MSK(div) ((1 << (div)) - 1)
34#define SH_CLK_DIV4_MSK SH_CLK_DIV_MSK(4)
35#define SH_CLK_DIV6_MSK SH_CLK_DIV_MSK(6)
36
37struct clk {
38 struct list_head node;
39 struct clk *parent;
40 struct clk **parent_table;
41 unsigned short parent_num;
42 unsigned char src_shift;
43 unsigned char src_width;
44 struct sh_clk_ops *ops;
45
46 struct list_head children;
47 struct list_head sibling;
48
49 int usecount;
50
51 unsigned long rate;
52 unsigned long flags;
53
54 void __iomem *enable_reg;
55 void __iomem *status_reg;
56 unsigned int enable_bit;
57 void __iomem *mapped_reg;
58
59 unsigned int div_mask;
60 unsigned long arch_flags;
61 void *priv;
62 struct clk_mapping *mapping;
63 struct cpufreq_frequency_table *freq_table;
64 unsigned int nr_freqs;
65};
66
67#define CLK_ENABLE_ON_INIT BIT(0)
68
69#define CLK_ENABLE_REG_32BIT BIT(1)
70#define CLK_ENABLE_REG_16BIT BIT(2)
71#define CLK_ENABLE_REG_8BIT BIT(3)
72
73#define CLK_MASK_DIV_ON_DISABLE BIT(4)
74
75#define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT | \
76 CLK_ENABLE_REG_16BIT | \
77 CLK_ENABLE_REG_8BIT)
78
79
80unsigned long followparent_recalc(struct clk *);
81void recalculate_root_clocks(void);
82void propagate_rate(struct clk *);
83int clk_reparent(struct clk *child, struct clk *parent);
84int clk_register(struct clk *);
85void clk_unregister(struct clk *);
86void clk_enable_init_clocks(void);
87
88struct clk_div_mult_table {
89 unsigned int *divisors;
90 unsigned int nr_divisors;
91 unsigned int *multipliers;
92 unsigned int nr_multipliers;
93};
94
95struct cpufreq_frequency_table;
96void clk_rate_table_build(struct clk *clk,
97 struct cpufreq_frequency_table *freq_table,
98 int nr_freqs,
99 struct clk_div_mult_table *src_table,
100 unsigned long *bitmap);
101
102long clk_rate_table_round(struct clk *clk,
103 struct cpufreq_frequency_table *freq_table,
104 unsigned long rate);
105
106int clk_rate_table_find(struct clk *clk,
107 struct cpufreq_frequency_table *freq_table,
108 unsigned long rate);
109
110long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
111 unsigned int div_max, unsigned long rate);
112
113long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min,
114 unsigned int mult_max, unsigned long rate);
115
116#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \
117{ \
118 .parent = _parent, \
119 .enable_reg = (void __iomem *)_enable_reg, \
120 .enable_bit = _enable_bit, \
121 .status_reg = _status_reg, \
122 .flags = _flags, \
123}
124
125#define SH_CLK_MSTP32(_p, _r, _b, _f) \
126 SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_32BIT)
127
128#define SH_CLK_MSTP32_STS(_p, _r, _b, _s, _f) \
129 SH_CLK_MSTP(_p, _r, _b, _s, _f | CLK_ENABLE_REG_32BIT)
130
131#define SH_CLK_MSTP16(_p, _r, _b, _f) \
132 SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_16BIT)
133
134#define SH_CLK_MSTP8(_p, _r, _b, _f) \
135 SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_8BIT)
136
137int sh_clk_mstp_register(struct clk *clks, int nr);
138
139
140
141
142
143
144
145static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr)
146{
147 return sh_clk_mstp_register(clks, nr);
148}
149
150#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
151{ \
152 .parent = _parent, \
153 .enable_reg = (void __iomem *)_reg, \
154 .enable_bit = _shift, \
155 .arch_flags = _div_bitmap, \
156 .div_mask = SH_CLK_DIV4_MSK, \
157 .flags = _flags, \
158}
159
160struct clk_div_table {
161 struct clk_div_mult_table *div_mult_table;
162 void (*kick)(struct clk *clk);
163};
164
165#define clk_div4_table clk_div_table
166
167int sh_clk_div4_register(struct clk *clks, int nr,
168 struct clk_div4_table *table);
169int sh_clk_div4_enable_register(struct clk *clks, int nr,
170 struct clk_div4_table *table);
171int sh_clk_div4_reparent_register(struct clk *clks, int nr,
172 struct clk_div4_table *table);
173
174#define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \
175 _num_parents, _src_shift, _src_width) \
176{ \
177 .enable_reg = (void __iomem *)_reg, \
178 .enable_bit = 0, \
179 .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
180 .div_mask = SH_CLK_DIV6_MSK, \
181 .parent_table = _parents, \
182 .parent_num = _num_parents, \
183 .src_shift = _src_shift, \
184 .src_width = _src_width, \
185}
186
187#define SH_CLK_DIV6(_parent, _reg, _flags) \
188{ \
189 .parent = _parent, \
190 .enable_reg = (void __iomem *)_reg, \
191 .enable_bit = 0, \
192 .div_mask = SH_CLK_DIV6_MSK, \
193 .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
194}
195
196int sh_clk_div6_register(struct clk *clks, int nr);
197int sh_clk_div6_reparent_register(struct clk *clks, int nr);
198
199#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
200#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
201#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
202
203
204#define SH_CLK_FSIDIV(_reg, _parent) \
205{ \
206 .enable_reg = (void __iomem *)_reg, \
207 .parent = _parent, \
208}
209
210int sh_clk_fsidiv_register(struct clk *clks, int nr);
211
212#endif
213
