LXR linux/include/linux/via-core.h

   1/*
   2 * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
   3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4 * Copyright 2009-2010 Jonathan Corbet <corbet@lwn.net>
   5 * Copyright 2010 Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public
   9 * License as published by the Free Software Foundation;
  10 * either version 2, or (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  14 * the implied warranty of MERCHANTABILITY or FITNESS FOR
  15 * A PARTICULAR PURPOSE.See the GNU General Public License
  16 * for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc.,
  21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22 */
  23
  24#ifndef __VIA_CORE_H__
  25#define __VIA_CORE_H__
  26#include <linux/types.h>
  27#include <linux/io.h>
  28#include <linux/spinlock.h>
  29#include <linux/pci.h>
  30
  31/*
  32 * A description of each known serial I2C/GPIO port.
  33 */
  34enum via_port_type {
  35        VIA_PORT_NONE = 0,
  36        VIA_PORT_I2C,
  37        VIA_PORT_GPIO,
  38};
  39
  40enum via_port_mode {
  41        VIA_MODE_OFF = 0,
  42        VIA_MODE_I2C,           /* Used as I2C port */
  43        VIA_MODE_GPIO,  /* Two GPIO ports */
  44};
  45
  46enum viafb_i2c_adap {
  47        VIA_PORT_26 = 0,
  48        VIA_PORT_31,
  49        VIA_PORT_25,
  50        VIA_PORT_2C,
  51        VIA_PORT_3D,
  52};
  53#define VIAFB_NUM_PORTS 5
  54
  55struct via_port_cfg {
  56        enum via_port_type      type;
  57        enum via_port_mode      mode;
  58        u16                     io_port;
  59        u8                      ioport_index;
  60};
  61
  62/*
  63 * Allow subdevs to register suspend/resume hooks.
  64 */
  65#ifdef CONFIG_PM
  66struct viafb_pm_hooks {
  67        struct list_head list;
  68        int (*suspend)(void *private);
  69        int (*resume)(void *private);
  70        void *private;
  71};
  72
  73void viafb_pm_register(struct viafb_pm_hooks *hooks);
  74void viafb_pm_unregister(struct viafb_pm_hooks *hooks);
  75#endif /* CONFIG_PM */
  76
  77/*
  78 * This is the global viafb "device" containing stuff needed by
  79 * all subdevs.
  80 */
  81struct viafb_dev {
  82        struct pci_dev *pdev;
  83        int chip_type;
  84        struct via_port_cfg *port_cfg;
  85        /*
  86         * Spinlock for access to device registers.  Not yet
  87         * globally used.
  88         */
  89        spinlock_t reg_lock;
  90        /*
  91         * The framebuffer MMIO region.  Little, if anything, touches
  92         * this memory directly, and certainly nothing outside of the
  93         * framebuffer device itself.  We *do* have to be able to allocate
  94         * chunks of this memory for other devices, though.
  95         */
  96        unsigned long fbmem_start;
  97        long fbmem_len;
  98        void __iomem *fbmem;
  99#if defined(CONFIG_VIDEO_VIA_CAMERA) || defined(CONFIG_VIDEO_VIA_CAMERA_MODULE)
 100        long camera_fbmem_offset;
 101        long camera_fbmem_size;
 102#endif
 103        /*
 104         * The MMIO region for device registers.
 105         */
 106        unsigned long engine_start;
 107        unsigned long engine_len;
 108        void __iomem *engine_mmio;
 109
 110};
 111
 112/*
 113 * Interrupt management.
 114 */
 115
 116void viafb_irq_enable(u32 mask);
 117void viafb_irq_disable(u32 mask);
 118
 119/*
 120 * The global interrupt control register and its bits.
 121 */
 122#define VDE_INTERRUPT   0x200   /* Video interrupt flags/masks */
 123#define   VDE_I_DVISENSE  0x00000001  /* DVI sense int status */
 124#define   VDE_I_VBLANK    0x00000002  /* Vertical blank status */
 125#define   VDE_I_MCCFI     0x00000004  /* MCE compl. frame int status */
 126#define   VDE_I_VSYNC     0x00000008  /* VGA VSYNC int status */
 127#define   VDE_I_DMA0DDONE 0x00000010  /* DMA 0 descr done */
 128#define   VDE_I_DMA0TDONE 0x00000020  /* DMA 0 transfer done */
 129#define   VDE_I_DMA1DDONE 0x00000040  /* DMA 1 descr done */
 130#define   VDE_I_DMA1TDONE 0x00000080  /* DMA 1 transfer done */
 131#define   VDE_I_C1AV      0x00000100  /* Cap Eng 1 act vid end */
 132#define   VDE_I_HQV0      0x00000200  /* First HQV engine */
 133#define   VDE_I_HQV1      0x00000400  /* Second HQV engine */
 134#define   VDE_I_HQV1EN    0x00000800  /* Second HQV engine enable */
 135#define   VDE_I_C0AV      0x00001000  /* Cap Eng 0 act vid end */
 136#define   VDE_I_C0VBI     0x00002000  /* Cap Eng 0 VBI end */
 137#define   VDE_I_C1VBI     0x00004000  /* Cap Eng 1 VBI end */
 138#define   VDE_I_VSYNC2    0x00008000  /* Sec. Disp. VSYNC */
 139#define   VDE_I_DVISNSEN  0x00010000  /* DVI sense enable */
 140#define   VDE_I_VSYNC2EN  0x00020000  /* Sec Disp VSYNC enable */
 141#define   VDE_I_MCCFIEN   0x00040000  /* MC comp frame int mask enable */
 142#define   VDE_I_VSYNCEN   0x00080000  /* VSYNC enable */
 143#define   VDE_I_DMA0DDEN  0x00100000  /* DMA 0 descr done enable */
 144#define   VDE_I_DMA0TDEN  0x00200000  /* DMA 0 trans done enable */
 145#define   VDE_I_DMA1DDEN  0x00400000  /* DMA 1 descr done enable */
 146#define   VDE_I_DMA1TDEN  0x00800000  /* DMA 1 trans done enable */
 147#define   VDE_I_C1AVEN    0x01000000  /* cap 1 act vid end enable */
 148#define   VDE_I_HQV0EN    0x02000000  /* First hqv engine enable */
 149#define   VDE_I_C1VBIEN   0x04000000  /* Cap 1 VBI end enable */
 150#define   VDE_I_LVDSSI    0x08000000  /* LVDS sense interrupt */
 151#define   VDE_I_C0AVEN    0x10000000  /* Cap 0 act vid end enable */
 152#define   VDE_I_C0VBIEN   0x20000000  /* Cap 0 VBI end enable */
 153#define   VDE_I_LVDSSIEN  0x40000000  /* LVDS Sense enable */
 154#define   VDE_I_ENABLE    0x80000000  /* Global interrupt enable */
 155
 156#if defined(CONFIG_VIDEO_VIA_CAMERA) || defined(CONFIG_VIDEO_VIA_CAMERA_MODULE)
 157/*
 158 * DMA management.
 159 */
 160int viafb_request_dma(void);
 161void viafb_release_dma(void);
 162/* void viafb_dma_copy_out(unsigned int offset, dma_addr_t paddr, int len); */
 163int viafb_dma_copy_out_sg(unsigned int offset, struct scatterlist *sg, int nsg);
 164
 165/*
 166 * DMA Controller registers.
 167 */
 168#define VDMA_MR0        0xe00           /* Mod reg 0 */
 169#define   VDMA_MR_CHAIN   0x01          /* Chaining mode */
 170#define   VDMA_MR_TDIE    0x02          /* Transfer done int enable */
 171#define VDMA_CSR0       0xe04           /* Control/status */
 172#define   VDMA_C_ENABLE   0x01            /* DMA Enable */
 173#define   VDMA_C_START    0x02            /* Start a transfer */
 174#define   VDMA_C_ABORT    0x04            /* Abort a transfer */
 175#define   VDMA_C_DONE     0x08            /* Transfer is done */
 176#define VDMA_MARL0      0xe20           /* Mem addr low */
 177#define VDMA_MARH0      0xe24           /* Mem addr high */
 178#define VDMA_DAR0       0xe28           /* Device address */
 179#define VDMA_DQWCR0     0xe2c           /* Count (16-byte) */
 180#define VDMA_TMR0       0xe30           /* Tile mode reg */
 181#define VDMA_DPRL0      0xe34           /* Not sure */
 182#define   VDMA_DPR_IN     0x08          /* Inbound transfer to FB */
 183#define VDMA_DPRH0      0xe38
 184#define VDMA_PMR0       (0xe00 + 0x134) /* Pitch mode */
 185
 186/*
 187 * Useful stuff that probably belongs somewhere global.
 188 */
 189#define VGA_WIDTH       640
 190#define VGA_HEIGHT      480
 191#endif /* CONFIG_VIDEO_VIA_CAMERA */
 192
 193/*
 194 * Indexed port operations.  Note that these are all multi-op
 195 * functions; every invocation will be racy if you're not holding
 196 * reg_lock.
 197 */
 198
 199#define VIAStatus   0x3DA  /* Non-indexed port */
 200#define VIACR       0x3D4
 201#define VIASR       0x3C4
 202#define VIAGR       0x3CE
 203#define VIAAR       0x3C0
 204
 205static inline u8 via_read_reg(u16 port, u8 index)
 206{
 207        outb(index, port);
 208        return inb(port + 1);
 209}
 210
 211static inline void via_write_reg(u16 port, u8 index, u8 data)
 212{
 213        outb(index, port);
 214        outb(data, port + 1);
 215}
 216
 217static inline void via_write_reg_mask(u16 port, u8 index, u8 data, u8 mask)
 218{
 219        u8 old;
 220
 221        outb(index, port);
 222        old = inb(port + 1);
 223        outb((data & mask) | (old & ~mask), port + 1);
 224}
 225
 226#define VIA_MISC_REG_READ       0x03CC
 227#define VIA_MISC_REG_WRITE      0x03C2
 228
 229static inline void via_write_misc_reg_mask(u8 data, u8 mask)
 230{
 231        u8 old = inb(VIA_MISC_REG_READ);
 232        outb((data & mask) | (old & ~mask), VIA_MISC_REG_WRITE);
 233}
 234
 235
 236#endif /* __VIA_CORE_H__ */
 237