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15#ifndef _UAPI_EXYNOS_DRM_H_
16#define _UAPI_EXYNOS_DRM_H_
17
18#include "drm.h"
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29struct drm_exynos_gem_create {
30 __u64 size;
31 __u32 flags;
32 __u32 handle;
33};
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42struct drm_exynos_gem_map {
43 __u32 handle;
44 __u32 reserved;
45 __u64 offset;
46};
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57struct drm_exynos_gem_info {
58 __u32 handle;
59 __u32 flags;
60 __u64 size;
61};
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71struct drm_exynos_vidi_connection {
72 __u32 connection;
73 __u32 extensions;
74 __u64 edid;
75};
76
77
78enum e_drm_exynos_gem_mem_type {
79
80 EXYNOS_BO_CONTIG = 0 << 0,
81
82 EXYNOS_BO_NONCONTIG = 1 << 0,
83
84 EXYNOS_BO_NONCACHABLE = 0 << 1,
85
86 EXYNOS_BO_CACHABLE = 1 << 1,
87
88 EXYNOS_BO_WC = 1 << 2,
89 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
90 EXYNOS_BO_WC
91};
92
93struct drm_exynos_g2d_get_ver {
94 __u32 major;
95 __u32 minor;
96};
97
98struct drm_exynos_g2d_cmd {
99 __u32 offset;
100 __u32 data;
101};
102
103enum drm_exynos_g2d_buf_type {
104 G2D_BUF_USERPTR = 1 << 31,
105};
106
107enum drm_exynos_g2d_event_type {
108 G2D_EVENT_NOT,
109 G2D_EVENT_NONSTOP,
110 G2D_EVENT_STOP,
111};
112
113struct drm_exynos_g2d_userptr {
114 unsigned long userptr;
115 unsigned long size;
116};
117
118struct drm_exynos_g2d_set_cmdlist {
119 __u64 cmd;
120 __u64 cmd_buf;
121 __u32 cmd_nr;
122 __u32 cmd_buf_nr;
123
124
125 __u64 event_type;
126 __u64 user_data;
127};
128
129struct drm_exynos_g2d_exec {
130 __u64 async;
131};
132
133enum drm_exynos_ops_id {
134 EXYNOS_DRM_OPS_SRC,
135 EXYNOS_DRM_OPS_DST,
136 EXYNOS_DRM_OPS_MAX,
137};
138
139struct drm_exynos_sz {
140 __u32 hsize;
141 __u32 vsize;
142};
143
144struct drm_exynos_pos {
145 __u32 x;
146 __u32 y;
147 __u32 w;
148 __u32 h;
149};
150
151enum drm_exynos_flip {
152 EXYNOS_DRM_FLIP_NONE = (0 << 0),
153 EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
154 EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
155 EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL |
156 EXYNOS_DRM_FLIP_HORIZONTAL,
157};
158
159enum drm_exynos_degree {
160 EXYNOS_DRM_DEGREE_0,
161 EXYNOS_DRM_DEGREE_90,
162 EXYNOS_DRM_DEGREE_180,
163 EXYNOS_DRM_DEGREE_270,
164};
165
166enum drm_exynos_planer {
167 EXYNOS_DRM_PLANAR_Y,
168 EXYNOS_DRM_PLANAR_CB,
169 EXYNOS_DRM_PLANAR_CR,
170 EXYNOS_DRM_PLANAR_MAX,
171};
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192struct drm_exynos_ipp_prop_list {
193 __u32 version;
194 __u32 ipp_id;
195 __u32 count;
196 __u32 writeback;
197 __u32 flip;
198 __u32 degree;
199 __u32 csc;
200 __u32 crop;
201 __u32 scale;
202 __u32 refresh_min;
203 __u32 refresh_max;
204 __u32 reserved;
205 struct drm_exynos_sz crop_min;
206 struct drm_exynos_sz crop_max;
207 struct drm_exynos_sz scale_min;
208 struct drm_exynos_sz scale_max;
209};
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221struct drm_exynos_ipp_config {
222 __u32 ops_id;
223 __u32 flip;
224 __u32 degree;
225 __u32 fmt;
226 struct drm_exynos_sz sz;
227 struct drm_exynos_pos pos;
228};
229
230enum drm_exynos_ipp_cmd {
231 IPP_CMD_NONE,
232 IPP_CMD_M2M,
233 IPP_CMD_WB,
234 IPP_CMD_OUTPUT,
235 IPP_CMD_MAX,
236};
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247struct drm_exynos_ipp_property {
248 struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
249 __u32 cmd;
250 __u32 ipp_id;
251 __u32 prop_id;
252 __u32 refresh_rate;
253};
254
255enum drm_exynos_ipp_buf_type {
256 IPP_BUF_ENQUEUE,
257 IPP_BUF_DEQUEUE,
258};
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270struct drm_exynos_ipp_queue_buf {
271 __u32 ops_id;
272 __u32 buf_type;
273 __u32 prop_id;
274 __u32 buf_id;
275 __u32 handle[EXYNOS_DRM_PLANAR_MAX];
276 __u32 reserved;
277 __u64 user_data;
278};
279
280enum drm_exynos_ipp_ctrl {
281 IPP_CTRL_PLAY,
282 IPP_CTRL_STOP,
283 IPP_CTRL_PAUSE,
284 IPP_CTRL_RESUME,
285 IPP_CTRL_MAX,
286};
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294struct drm_exynos_ipp_cmd_ctrl {
295 __u32 prop_id;
296 __u32 ctrl;
297};
298
299#define DRM_EXYNOS_GEM_CREATE 0x00
300#define DRM_EXYNOS_GEM_MAP 0x01
301
302#define DRM_EXYNOS_GEM_GET 0x04
303#define DRM_EXYNOS_VIDI_CONNECTION 0x07
304
305
306#define DRM_EXYNOS_G2D_GET_VER 0x20
307#define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
308#define DRM_EXYNOS_G2D_EXEC 0x22
309
310
311#define DRM_EXYNOS_IPP_GET_PROPERTY 0x30
312#define DRM_EXYNOS_IPP_SET_PROPERTY 0x31
313#define DRM_EXYNOS_IPP_QUEUE_BUF 0x32
314#define DRM_EXYNOS_IPP_CMD_CTRL 0x33
315
316#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
317 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
318#define DRM_IOCTL_EXYNOS_GEM_MAP DRM_IOWR(DRM_COMMAND_BASE + \
319 DRM_EXYNOS_GEM_MAP, struct drm_exynos_gem_map)
320#define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \
321 DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
322
323#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \
324 DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
325
326#define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \
327 DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
328#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \
329 DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
330#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
331 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
332
333#define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
334 DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
335#define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
336 DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
337#define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \
338 DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
339#define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \
340 DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)
341
342
343#define DRM_EXYNOS_G2D_EVENT 0x80000000
344#define DRM_EXYNOS_IPP_EVENT 0x80000001
345
346struct drm_exynos_g2d_event {
347 struct drm_event base;
348 __u64 user_data;
349 __u32 tv_sec;
350 __u32 tv_usec;
351 __u32 cmdlist_no;
352 __u32 reserved;
353};
354
355struct drm_exynos_ipp_event {
356 struct drm_event base;
357 __u64 user_data;
358 __u32 tv_sec;
359 __u32 tv_usec;
360 __u32 prop_id;
361 __u32 reserved;
362 __u32 buf_id[EXYNOS_DRM_OPS_MAX];
363};
364
365#endif
366