1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#ifndef _I2O_DEV_H
21#define _I2O_DEV_H
22
23
24#define MAX_I2O_CONTROLLERS 32
25
26#include <linux/ioctl.h>
27#include <linux/types.h>
28
29
30
31
32#define I2O_MAGIC_NUMBER 'i'
33#define I2OGETIOPS _IOR(I2O_MAGIC_NUMBER,0,__u8[MAX_I2O_CONTROLLERS])
34#define I2OHRTGET _IOWR(I2O_MAGIC_NUMBER,1,struct i2o_cmd_hrtlct)
35#define I2OLCTGET _IOWR(I2O_MAGIC_NUMBER,2,struct i2o_cmd_hrtlct)
36#define I2OPARMSET _IOWR(I2O_MAGIC_NUMBER,3,struct i2o_cmd_psetget)
37#define I2OPARMGET _IOWR(I2O_MAGIC_NUMBER,4,struct i2o_cmd_psetget)
38#define I2OSWDL _IOWR(I2O_MAGIC_NUMBER,5,struct i2o_sw_xfer)
39#define I2OSWUL _IOWR(I2O_MAGIC_NUMBER,6,struct i2o_sw_xfer)
40#define I2OSWDEL _IOWR(I2O_MAGIC_NUMBER,7,struct i2o_sw_xfer)
41#define I2OVALIDATE _IOR(I2O_MAGIC_NUMBER,8,__u32)
42#define I2OHTML _IOWR(I2O_MAGIC_NUMBER,9,struct i2o_html)
43#define I2OEVTREG _IOW(I2O_MAGIC_NUMBER,10,struct i2o_evt_id)
44#define I2OEVTGET _IOR(I2O_MAGIC_NUMBER,11,struct i2o_evt_info)
45#define I2OPASSTHRU _IOR(I2O_MAGIC_NUMBER,12,struct i2o_cmd_passthru)
46#define I2OPASSTHRU32 _IOR(I2O_MAGIC_NUMBER,12,struct i2o_cmd_passthru32)
47
48struct i2o_cmd_passthru32 {
49 unsigned int iop;
50 __u32 msg;
51};
52
53struct i2o_cmd_passthru {
54 unsigned int iop;
55 void __user *msg;
56};
57
58struct i2o_cmd_hrtlct {
59 unsigned int iop;
60 void __user *resbuf;
61 unsigned int __user *reslen;
62};
63
64struct i2o_cmd_psetget {
65 unsigned int iop;
66 unsigned int tid;
67 void __user *opbuf;
68 unsigned int oplen;
69 void __user *resbuf;
70 unsigned int __user *reslen;
71};
72
73struct i2o_sw_xfer {
74 unsigned int iop;
75 unsigned char flags;
76 unsigned char sw_type;
77 unsigned int sw_id;
78 void __user *buf;
79 unsigned int __user *swlen;
80 unsigned int __user *maxfrag;
81 unsigned int __user *curfrag;
82};
83
84struct i2o_html {
85 unsigned int iop;
86 unsigned int tid;
87 unsigned int page;
88 void __user *resbuf;
89 unsigned int __user *reslen;
90 void __user *qbuf;
91 unsigned int qlen;
92};
93
94#define I2O_EVT_Q_LEN 32
95
96struct i2o_evt_id {
97 unsigned int iop;
98 unsigned int tid;
99 unsigned int evt_mask;
100};
101
102
103#define I2O_EVT_DATA_SIZE 88
104
105struct i2o_evt_info {
106 struct i2o_evt_id id;
107 unsigned char evt_data[I2O_EVT_DATA_SIZE];
108 unsigned int data_size;
109};
110
111struct i2o_evt_get {
112 struct i2o_evt_info info;
113 int pending;
114 int lost;
115};
116
117typedef struct i2o_sg_io_hdr {
118 unsigned int flags;
119} i2o_sg_io_hdr_t;
120
121
122
123
124#define I2O_BUS_LOCAL 0
125#define I2O_BUS_ISA 1
126#define I2O_BUS_EISA 2
127
128#define I2O_BUS_PCI 4
129#define I2O_BUS_PCMCIA 5
130#define I2O_BUS_NUBUS 6
131#define I2O_BUS_CARDBUS 7
132#define I2O_BUS_UNKNOWN 0x80
133
134typedef struct _i2o_pci_bus {
135 __u8 PciFunctionNumber;
136 __u8 PciDeviceNumber;
137 __u8 PciBusNumber;
138 __u8 reserved;
139 __u16 PciVendorID;
140 __u16 PciDeviceID;
141} i2o_pci_bus;
142
143typedef struct _i2o_local_bus {
144 __u16 LbBaseIOPort;
145 __u16 reserved;
146 __u32 LbBaseMemoryAddress;
147} i2o_local_bus;
148
149typedef struct _i2o_isa_bus {
150 __u16 IsaBaseIOPort;
151 __u8 CSN;
152 __u8 reserved;
153 __u32 IsaBaseMemoryAddress;
154} i2o_isa_bus;
155
156typedef struct _i2o_eisa_bus_info {
157 __u16 EisaBaseIOPort;
158 __u8 reserved;
159 __u8 EisaSlotNumber;
160 __u32 EisaBaseMemoryAddress;
161} i2o_eisa_bus;
162
163typedef struct _i2o_mca_bus {
164 __u16 McaBaseIOPort;
165 __u8 reserved;
166 __u8 McaSlotNumber;
167 __u32 McaBaseMemoryAddress;
168} i2o_mca_bus;
169
170typedef struct _i2o_other_bus {
171 __u16 BaseIOPort;
172 __u16 reserved;
173 __u32 BaseMemoryAddress;
174} i2o_other_bus;
175
176typedef struct _i2o_hrt_entry {
177 __u32 adapter_id;
178 __u32 parent_tid:12;
179 __u32 state:4;
180 __u32 bus_num:8;
181 __u32 bus_type:8;
182 union {
183 i2o_pci_bus pci_bus;
184 i2o_local_bus local_bus;
185 i2o_isa_bus isa_bus;
186 i2o_eisa_bus eisa_bus;
187 i2o_mca_bus mca_bus;
188 i2o_other_bus other_bus;
189 } bus;
190} i2o_hrt_entry;
191
192typedef struct _i2o_hrt {
193 __u16 num_entries;
194 __u8 entry_len;
195 __u8 hrt_version;
196 __u32 change_ind;
197 i2o_hrt_entry hrt_entry[1];
198} i2o_hrt;
199
200typedef struct _i2o_lct_entry {
201 __u32 entry_size:16;
202 __u32 tid:12;
203 __u32 reserved:4;
204 __u32 change_ind;
205 __u32 device_flags;
206 __u32 class_id:12;
207 __u32 version:4;
208 __u32 vendor_id:16;
209 __u32 sub_class;
210 __u32 user_tid:12;
211 __u32 parent_tid:12;
212 __u32 bios_info:8;
213 __u8 identity_tag[8];
214 __u32 event_capabilities;
215} i2o_lct_entry;
216
217typedef struct _i2o_lct {
218 __u32 table_size:16;
219 __u32 boot_tid:12;
220 __u32 lct_ver:4;
221 __u32 iop_flags;
222 __u32 change_ind;
223 i2o_lct_entry lct_entry[1];
224} i2o_lct;
225
226typedef struct _i2o_status_block {
227 __u16 org_id;
228 __u16 reserved;
229 __u16 iop_id:12;
230 __u16 reserved1:4;
231 __u16 host_unit_id;
232 __u16 segment_number:12;
233 __u16 i2o_version:4;
234 __u8 iop_state;
235 __u8 msg_type;
236 __u16 inbound_frame_size;
237 __u8 init_code;
238 __u8 reserved2;
239 __u32 max_inbound_frames;
240 __u32 cur_inbound_frames;
241 __u32 max_outbound_frames;
242 char product_id[24];
243 __u32 expected_lct_size;
244 __u32 iop_capabilities;
245 __u32 desired_mem_size;
246 __u32 current_mem_size;
247 __u32 current_mem_base;
248 __u32 desired_io_size;
249 __u32 current_io_size;
250 __u32 current_io_base;
251 __u32 reserved3:24;
252 __u32 cmd_status:8;
253} i2o_status_block;
254
255
256#define I2O_EVT_IND_STATE_CHANGE 0x80000000
257#define I2O_EVT_IND_GENERAL_WARNING 0x40000000
258#define I2O_EVT_IND_CONFIGURATION_FLAG 0x20000000
259#define I2O_EVT_IND_LOCK_RELEASE 0x10000000
260#define I2O_EVT_IND_CAPABILITY_CHANGE 0x08000000
261#define I2O_EVT_IND_DEVICE_RESET 0x04000000
262#define I2O_EVT_IND_EVT_MASK_MODIFIED 0x02000000
263#define I2O_EVT_IND_FIELD_MODIFIED 0x01000000
264#define I2O_EVT_IND_VENDOR_EVT 0x00800000
265#define I2O_EVT_IND_DEVICE_STATE 0x00400000
266
267
268#define I2O_EVT_IND_EXEC_RESOURCE_LIMITS 0x00000001
269#define I2O_EVT_IND_EXEC_CONNECTION_FAIL 0x00000002
270#define I2O_EVT_IND_EXEC_ADAPTER_FAULT 0x00000004
271#define I2O_EVT_IND_EXEC_POWER_FAIL 0x00000008
272#define I2O_EVT_IND_EXEC_RESET_PENDING 0x00000010
273#define I2O_EVT_IND_EXEC_RESET_IMMINENT 0x00000020
274#define I2O_EVT_IND_EXEC_HW_FAIL 0x00000040
275#define I2O_EVT_IND_EXEC_XCT_CHANGE 0x00000080
276#define I2O_EVT_IND_EXEC_NEW_LCT_ENTRY 0x00000100
277#define I2O_EVT_IND_EXEC_MODIFIED_LCT 0x00000200
278#define I2O_EVT_IND_EXEC_DDM_AVAILABILITY 0x00000400
279
280
281#define I2O_EVT_IND_BSA_VOLUME_LOAD 0x00000001
282#define I2O_EVT_IND_BSA_VOLUME_UNLOAD 0x00000002
283#define I2O_EVT_IND_BSA_VOLUME_UNLOAD_REQ 0x00000004
284#define I2O_EVT_IND_BSA_CAPACITY_CHANGE 0x00000008
285#define I2O_EVT_IND_BSA_SCSI_SMART 0x00000010
286
287
288#define I2O_EVT_STATE_CHANGE_NORMAL 0x00
289#define I2O_EVT_STATE_CHANGE_SUSPENDED 0x01
290#define I2O_EVT_STATE_CHANGE_RESTART 0x02
291#define I2O_EVT_STATE_CHANGE_NA_RECOVER 0x03
292#define I2O_EVT_STATE_CHANGE_NA_NO_RECOVER 0x04
293#define I2O_EVT_STATE_CHANGE_QUIESCE_REQUEST 0x05
294#define I2O_EVT_STATE_CHANGE_FAILED 0x10
295#define I2O_EVT_STATE_CHANGE_FAULTED 0x11
296
297#define I2O_EVT_GEN_WARNING_NORMAL 0x00
298#define I2O_EVT_GEN_WARNING_ERROR_THRESHOLD 0x01
299#define I2O_EVT_GEN_WARNING_MEDIA_FAULT 0x02
300
301#define I2O_EVT_CAPABILITY_OTHER 0x01
302#define I2O_EVT_CAPABILITY_CHANGED 0x02
303
304#define I2O_EVT_SENSOR_STATE_CHANGED 0x01
305
306
307
308
309
310
311
312
313#define I2O_CLASS_VERSION_10 0x00
314#define I2O_CLASS_VERSION_11 0x01
315
316
317
318
319
320#define I2O_CLASS_EXECUTIVE 0x000
321#define I2O_CLASS_DDM 0x001
322#define I2O_CLASS_RANDOM_BLOCK_STORAGE 0x010
323#define I2O_CLASS_SEQUENTIAL_STORAGE 0x011
324#define I2O_CLASS_LAN 0x020
325#define I2O_CLASS_WAN 0x030
326#define I2O_CLASS_FIBRE_CHANNEL_PORT 0x040
327#define I2O_CLASS_FIBRE_CHANNEL_PERIPHERAL 0x041
328#define I2O_CLASS_SCSI_PERIPHERAL 0x051
329#define I2O_CLASS_ATE_PORT 0x060
330#define I2O_CLASS_ATE_PERIPHERAL 0x061
331#define I2O_CLASS_FLOPPY_CONTROLLER 0x070
332#define I2O_CLASS_FLOPPY_DEVICE 0x071
333#define I2O_CLASS_BUS_ADAPTER 0x080
334#define I2O_CLASS_PEER_TRANSPORT_AGENT 0x090
335#define I2O_CLASS_PEER_TRANSPORT 0x091
336#define I2O_CLASS_END 0xfff
337
338
339
340
341
342#define I2O_CLASS_MATCH_ANYCLASS 0xffffffff
343
344
345
346
347
348#define I2O_SUBCLASS_i960 0x001
349#define I2O_SUBCLASS_HDM 0x020
350#define I2O_SUBCLASS_ISM 0x021
351
352
353
354#define I2O_PARAMS_FIELD_GET 0x0001
355#define I2O_PARAMS_LIST_GET 0x0002
356#define I2O_PARAMS_MORE_GET 0x0003
357#define I2O_PARAMS_SIZE_GET 0x0004
358#define I2O_PARAMS_TABLE_GET 0x0005
359#define I2O_PARAMS_FIELD_SET 0x0006
360#define I2O_PARAMS_LIST_SET 0x0007
361#define I2O_PARAMS_ROW_ADD 0x0008
362#define I2O_PARAMS_ROW_DELETE 0x0009
363#define I2O_PARAMS_TABLE_CLEAR 0x000A
364
365
366
367
368
369
370#define I2O_SNFORMAT_UNKNOWN 0
371#define I2O_SNFORMAT_BINARY 1
372#define I2O_SNFORMAT_ASCII 2
373#define I2O_SNFORMAT_UNICODE 3
374#define I2O_SNFORMAT_LAN48_MAC 4
375#define I2O_SNFORMAT_WAN 5
376
377
378
379
380
381#define I2O_SNFORMAT_LAN64_MAC 6
382#define I2O_SNFORMAT_DDM 7
383#define I2O_SNFORMAT_IEEE_REG64 8
384#define I2O_SNFORMAT_IEEE_REG128 9
385#define I2O_SNFORMAT_UNKNOWN2 0xff
386
387
388
389
390
391#define ADAPTER_STATE_INITIALIZING 0x01
392#define ADAPTER_STATE_RESET 0x02
393#define ADAPTER_STATE_HOLD 0x04
394#define ADAPTER_STATE_READY 0x05
395#define ADAPTER_STATE_OPERATIONAL 0x08
396#define ADAPTER_STATE_FAILED 0x10
397#define ADAPTER_STATE_FAULTED 0x11
398
399
400
401
402#define I2O_SOFTWARE_MODULE_IRTOS 0x11
403#define I2O_SOFTWARE_MODULE_IOP_PRIVATE 0x22
404#define I2O_SOFTWARE_MODULE_IOP_CONFIG 0x23
405
406
407
408
409#define I2O_VENDOR_DPT 0x001b
410
411
412
413
414#define I2O_DPT_SG_FLAG_INTERPRET 0x00010000
415#define I2O_DPT_SG_FLAG_PHYSICAL 0x00020000
416
417#define I2O_DPT_FLASH_FRAG_SIZE 0x10000
418#define I2O_DPT_FLASH_READ 0x0101
419#define I2O_DPT_FLASH_WRITE 0x0102
420
421#endif
422
