1/* 2 * pci_regs.h 3 * 4 * PCI standard defines 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 * 16 * For HyperTransport information, please consult the following manuals 17 * from http://www.hypertransport.org 18 * 19 * The HyperTransport I/O Link Specification 20 */ 21 22#ifndef LINUX_PCI_REGS_H 23#define LINUX_PCI_REGS_H 24 25/* 26 * Under PCI, each device has 256 bytes of configuration address space, 27 * of which the first 64 bytes are standardized as follows: 28 */ 29#define PCI_STD_HEADER_SIZEOF 64 30#define PCI_VENDOR_ID 0x00 /* 16 bits */ 31#define PCI_DEVICE_ID 0x02 /* 16 bits */ 32#define PCI_COMMAND 0x04 /* 16 bits */ 33#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 34#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 35#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 36#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 37#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 38#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 39#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 40#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 41#define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 42#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 43#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ 44 45#define PCI_STATUS 0x06 /* 16 bits */ 46#define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */ 47#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 48#define PCI_STATUS_66MHZ 0x20 /* Support 66 MHz PCI 2.1 bus */ 49#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 50#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 51#define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 52#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 53#define PCI_STATUS_DEVSEL_FAST 0x000 54#define PCI_STATUS_DEVSEL_MEDIUM 0x200 55#define PCI_STATUS_DEVSEL_SLOW 0x400 56#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 57#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 58#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 59#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 60#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 61 62#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */ 63#define PCI_REVISION_ID 0x08 /* Revision ID */ 64#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 65#define PCI_CLASS_DEVICE 0x0a /* Device class */ 66 67#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ 68#define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 69#define PCI_HEADER_TYPE 0x0e /* 8 bits */ 70#define PCI_HEADER_TYPE_NORMAL 0 71#define PCI_HEADER_TYPE_BRIDGE 1 72#define PCI_HEADER_TYPE_CARDBUS 2 73 74#define PCI_BIST 0x0f /* 8 bits */ 75#define PCI_BIST_CODE_MASK 0x0f /* Return result */ 76#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ 77#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ 78 79/* 80 * Base addresses specify locations in memory or I/O space. 81 * Decoded size can be determined by writing a value of 82 * 0xffffffff to the register, and reading it back. Only 83 * 1 bits are decoded. 84 */ 85#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 86#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ 87#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ 88#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 89#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 90#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 91#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ 92#define PCI_BASE_ADDRESS_SPACE_IO 0x01 93#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 94#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 95#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 96#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 97#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 98#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 99#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) 100#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) 101/* bit 1 is reserved if address_space = 1 */ 102 103/* Header type 0 (normal devices) */ 104#define PCI_CARDBUS_CIS 0x28 105#define PCI_SUBSYSTEM_VENDOR_ID 0x2c 106#define PCI_SUBSYSTEM_ID 0x2e 107#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 108#define PCI_ROM_ADDRESS_ENABLE 0x01 109#define PCI_ROM_ADDRESS_MASK (~0x7ffUL) 110 111#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ 112 113/* 0x35-0x3b are reserved */ 114#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 115#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 116#define PCI_MIN_GNT 0x3e /* 8 bits */ 117#define PCI_MAX_LAT 0x3f /* 8 bits */ 118 119/* Header type 1 (PCI-to-PCI bridges) */ 120#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 121#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 122#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 123#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 124#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 125#define PCI_IO_LIMIT 0x1d 126#define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */ 127#define PCI_IO_RANGE_TYPE_16 0x00 128#define PCI_IO_RANGE_TYPE_32 0x01 129#define PCI_IO_RANGE_MASK (~0x0fUL) /* Standard 4K I/O windows */ 130#define PCI_IO_1K_RANGE_MASK (~0x03UL) /* Intel 1K I/O windows */ 131#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 132#define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 133#define PCI_MEMORY_LIMIT 0x22 134#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 135#define PCI_MEMORY_RANGE_MASK (~0x0fUL) 136#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 137#define PCI_PREF_MEMORY_LIMIT 0x26 138#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 139#define PCI_PREF_RANGE_TYPE_32 0x00 140#define PCI_PREF_RANGE_TYPE_64 0x01 141#define PCI_PREF_RANGE_MASK (~0x0fUL) 142#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 143#define PCI_PREF_LIMIT_UPPER32 0x2c 144#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 145#define PCI_IO_LIMIT_UPPER16 0x32 146/* 0x34 same as for htype 0 */ 147/* 0x35-0x3b is reserved */ 148#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 149/* 0x3c-0x3d are same as for htype 0 */ 150#define PCI_BRIDGE_CONTROL 0x3e 151#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 152#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 153#define PCI_BRIDGE_CTL_ISA 0x04 /* Enable ISA mode */ 154#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 155#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 156#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 157#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 158 159/* Header type 2 (CardBus bridges) */ 160#define PCI_CB_CAPABILITY_LIST 0x14 161/* 0x15 reserved */ 162#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ 163#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ 164#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ 165#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ 166#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ 167#define PCI_CB_MEMORY_BASE_0 0x1c 168#define PCI_CB_MEMORY_LIMIT_0 0x20 169#define PCI_CB_MEMORY_BASE_1 0x24 170#define PCI_CB_MEMORY_LIMIT_1 0x28 171#define PCI_CB_IO_BASE_0 0x2c 172#define PCI_CB_IO_BASE_0_HI 0x2e 173#define PCI_CB_IO_LIMIT_0 0x30 174#define PCI_CB_IO_LIMIT_0_HI 0x32 175#define PCI_CB_IO_BASE_1 0x34 176#define PCI_CB_IO_BASE_1_HI 0x36 177#define PCI_CB_IO_LIMIT_1 0x38 178#define PCI_CB_IO_LIMIT_1_HI 0x3a 179#define PCI_CB_IO_RANGE_MASK (~0x03UL) 180/* 0x3c-0x3d are same as for htype 0 */ 181#define PCI_CB_BRIDGE_CONTROL 0x3e 182#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ 183#define PCI_CB_BRIDGE_CTL_SERR 0x02 184#define PCI_CB_BRIDGE_CTL_ISA 0x04 185#define PCI_CB_BRIDGE_CTL_VGA 0x08 186#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 187#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ 188#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ 189#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ 190#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 191#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 192#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 193#define PCI_CB_SUBSYSTEM_ID 0x42 194#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ 195/* 0x48-0x7f reserved */ 196 197/* Capability lists */ 198 199#define PCI_CAP_LIST_ID 0 /* Capability ID */ 200#define PCI_CAP_ID_PM 0x01 /* Power Management */ 201#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 202#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 203#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 204#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 205#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 206#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ 207#define PCI_CAP_ID_HT 0x08 /* HyperTransport */ 208#define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */ 209#define PCI_CAP_ID_DBG 0x0A /* Debug port */ 210#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ 211#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ 212#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ 213#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ 214#define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */ 215#define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 216#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ 217#define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */ 218#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */ 219#define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */ 220#define PCI_CAP_ID_MAX PCI_CAP_ID_EA 221#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 222#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 223#define PCI_CAP_SIZEOF 4 224 225/* Power Management Registers */ 226 227#define PCI_PM_PMC 2 /* PM Capabilities Register */ 228#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 229#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 230#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ 231#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ 232#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxiliary power support mask */ 233#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 234#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 235#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ 236#define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */ 237#define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */ 238#define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */ 239#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */ 240#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */ 241#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */ 242#define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */ 243#define PCI_PM_CTRL 4 /* PM control and status register */ 244#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 245#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */ 246#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 247#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 248#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 249#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 250#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ 251#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ 252#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ 253#define PCI_PM_DATA_REGISTER 7 /* (??) */ 254#define PCI_PM_SIZEOF 8 255 256/* AGP registers */ 257 258#define PCI_AGP_VERSION 2 /* BCD version number */ 259#define PCI_AGP_RFU 3 /* Rest of capability flags */ 260#define PCI_AGP_STATUS 4 /* Status register */ 261#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ 262#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ 263#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ 264#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ 265#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ 266#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ 267#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ 268#define PCI_AGP_COMMAND 8 /* Control register */ 269#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 270#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 271#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 272#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 273#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 274#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 275#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ 276#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ 277#define PCI_AGP_SIZEOF 12 278 279/* Vital Product Data */ 280 281#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */ 282#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */ 283#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */ 284#define PCI_VPD_DATA 4 /* 32-bits of data returned here */ 285#define PCI_CAP_VPD_SIZEOF 8 286 287/* Slot Identification */ 288 289#define PCI_SID_ESR 2 /* Expansion Slot Register */ 290#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ 291#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 292#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 293 294/* Message Signalled Interrupts registers */ 295 296#define PCI_MSI_FLAGS 2 /* Message Control */ 297#define PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */ 298#define PCI_MSI_FLAGS_QMASK 0x000e /* Maximum queue size available */ 299#define PCI_MSI_FLAGS_QSIZE 0x0070 /* Message queue size configured */ 300#define PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */ 301#define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */ 302#define PCI_MSI_RFU 3 /* Rest of capability flags */ 303#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ 304#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 305#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ 306#define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */ 307#define PCI_MSI_PENDING_32 16 /* Pending intrs for 32-bit devices */ 308#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 309#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */ 310#define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */ 311 312/* MSI-X registers */ 313#define PCI_MSIX_FLAGS 2 /* Message Control */ 314#define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */ 315#define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */ 316#define PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */ 317#define PCI_MSIX_TABLE 4 /* Table offset */ 318#define PCI_MSIX_TABLE_BIR 0x00000007 /* BAR index */ 319#define PCI_MSIX_TABLE_OFFSET 0xfffffff8 /* Offset into specified BAR */ 320#define PCI_MSIX_PBA 8 /* Pending Bit Array offset */ 321#define PCI_MSIX_PBA_BIR 0x00000007 /* BAR index */ 322#define PCI_MSIX_PBA_OFFSET 0xfffffff8 /* Offset into specified BAR */ 323#define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR /* deprecated */ 324#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */ 325 326/* MSI-X Table entry format */ 327#define PCI_MSIX_ENTRY_SIZE 16 328#define PCI_MSIX_ENTRY_LOWER_ADDR 0 329#define PCI_MSIX_ENTRY_UPPER_ADDR 4 330#define PCI_MSIX_ENTRY_DATA 8 331#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 332#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1 333 334/* CompactPCI Hotswap Register */ 335 336#define PCI_CHSWP_CSR 2 /* Control and Status Register */ 337#define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */ 338#define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */ 339#define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */ 340#define PCI_CHSWP_LOO 0x08 /* LED On / Off */ 341#define PCI_CHSWP_PI 0x30 /* Programming Interface */ 342#define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */ 343#define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */ 344 345/* PCI Advanced Feature registers */ 346 347#define PCI_AF_LENGTH 2 348#define PCI_AF_CAP 3 349#define PCI_AF_CAP_TP 0x01 350#define PCI_AF_CAP_FLR 0x02 351#define PCI_AF_CTRL 4 352#define PCI_AF_CTRL_FLR 0x01 353#define PCI_AF_STATUS 5 354#define PCI_AF_STATUS_TP 0x01 355#define PCI_CAP_AF_SIZEOF 6 /* size of AF registers */ 356 357/* PCI Enhanced Allocation registers */ 358 359#define PCI_EA_NUM_ENT 2 /* Number of Capability Entries */ 360#define PCI_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */ 361#define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */ 362#define PCI_EA_FIRST_ENT_BRIDGE 8 /* First EA Entry for Bridges */ 363#define PCI_EA_ES 0x00000007 /* Entry Size */ 364#define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */ 365/* 0-5 map to BARs 0-5 respectively */ 366#define PCI_EA_BEI_BAR0 0 367#define PCI_EA_BEI_BAR5 5 368#define PCI_EA_BEI_BRIDGE 6 /* Resource behind bridge */ 369#define PCI_EA_BEI_ENI 7 /* Equivalent Not Indicated */ 370#define PCI_EA_BEI_ROM 8 /* Expansion ROM */ 371/* 9-14 map to VF BARs 0-5 respectively */ 372#define PCI_EA_BEI_VF_BAR0 9 373#define PCI_EA_BEI_VF_BAR5 14 374#define PCI_EA_BEI_RESERVED 15 /* Reserved - Treat like ENI */ 375#define PCI_EA_PP 0x0000ff00 /* Primary Properties */ 376#define PCI_EA_SP 0x00ff0000 /* Secondary Properties */ 377#define PCI_EA_P_MEM 0x00 /* Non-Prefetch Memory */ 378#define PCI_EA_P_MEM_PREFETCH 0x01 /* Prefetchable Memory */ 379#define PCI_EA_P_IO 0x02 /* I/O Space */ 380#define PCI_EA_P_VF_MEM_PREFETCH 0x03 /* VF Prefetchable Memory */ 381#define PCI_EA_P_VF_MEM 0x04 /* VF Non-Prefetch Memory */ 382#define PCI_EA_P_BRIDGE_MEM 0x05 /* Bridge Non-Prefetch Memory */ 383#define PCI_EA_P_BRIDGE_MEM_PREFETCH 0x06 /* Bridge Prefetchable Memory */ 384#define PCI_EA_P_BRIDGE_IO 0x07 /* Bridge I/O Space */ 385/* 0x08-0xfc reserved */ 386#define PCI_EA_P_MEM_RESERVED 0xfd /* Reserved Memory */ 387#define PCI_EA_P_IO_RESERVED 0xfe /* Reserved I/O Space */ 388#define PCI_EA_P_UNAVAILABLE 0xff /* Entry Unavailable */ 389#define PCI_EA_WRITABLE 0x40000000 /* Writable: 1 = RW, 0 = HwInit */ 390#define PCI_EA_ENABLE 0x80000000 /* Enable for this entry */ 391#define PCI_EA_BASE 4 /* Base Address Offset */ 392#define PCI_EA_MAX_OFFSET 8 /* MaxOffset (resource length) */ 393/* bit 0 is reserved */ 394#define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */ 395#define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ 396 397/* PCI-X registers (Type 0 (non-bridge) devices) */ 398 399#define PCI_X_CMD 2 /* Modes & Features */ 400#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ 401#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ 402#define PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */ 403#define PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */ 404#define PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */ 405#define PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */ 406#define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */ 407 /* Max # of outstanding split transactions */ 408#define PCI_X_CMD_SPLIT_1 0x0000 /* Max 1 */ 409#define PCI_X_CMD_SPLIT_2 0x0010 /* Max 2 */ 410#define PCI_X_CMD_SPLIT_3 0x0020 /* Max 3 */ 411#define PCI_X_CMD_SPLIT_4 0x0030 /* Max 4 */ 412#define PCI_X_CMD_SPLIT_8 0x0040 /* Max 8 */ 413#define PCI_X_CMD_SPLIT_12 0x0050 /* Max 12 */ 414#define PCI_X_CMD_SPLIT_16 0x0060 /* Max 16 */ 415#define PCI_X_CMD_SPLIT_32 0x0070 /* Max 32 */ 416#define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ 417#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ 418#define PCI_X_STATUS 4 /* PCI-X capabilities */ 419#define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */ 420#define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */ 421#define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */ 422#define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */ 423#define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */ 424#define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */ 425#define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */ 426#define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */ 427#define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */ 428#define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */ 429#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */ 430#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ 431#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ 432#define PCI_X_ECC_CSR 8 /* ECC control and status */ 433#define PCI_CAP_PCIX_SIZEOF_V0 8 /* size of registers for Version 0 */ 434#define PCI_CAP_PCIX_SIZEOF_V1 24 /* size for Version 1 */ 435#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */ 436 437/* PCI-X registers (Type 1 (bridge) devices) */ 438 439#define PCI_X_BRIDGE_SSTATUS 2 /* Secondary Status */ 440#define PCI_X_SSTATUS_64BIT 0x0001 /* Secondary AD interface is 64 bits */ 441#define PCI_X_SSTATUS_133MHZ 0x0002 /* 133 MHz capable */ 442#define PCI_X_SSTATUS_FREQ 0x03c0 /* Secondary Bus Mode and Frequency */ 443#define PCI_X_SSTATUS_VERS 0x3000 /* PCI-X Capability Version */ 444#define PCI_X_SSTATUS_V1 0x1000 /* Mode 2, not Mode 1 */ 445#define PCI_X_SSTATUS_V2 0x2000 /* Mode 1 or Modes 1 and 2 */ 446#define PCI_X_SSTATUS_266MHZ 0x4000 /* 266 MHz capable */ 447#define PCI_X_SSTATUS_533MHZ 0x8000 /* 533 MHz capable */ 448#define PCI_X_BRIDGE_STATUS 4 /* Bridge Status */ 449 450/* PCI Bridge Subsystem ID registers */ 451 452#define PCI_SSVID_VENDOR_ID 4 /* PCI Bridge subsystem vendor ID */ 453#define PCI_SSVID_DEVICE_ID 6 /* PCI Bridge subsystem device ID */ 454 455/* PCI Express capability registers */ 456 457#define PCI_EXP_FLAGS 2 /* Capabilities register */ 458#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ 459#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ 460#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ 461#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ 462#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ 463#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ 464#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ 465#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */ 466#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */ 467#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */ 468#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */ 469#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ 470#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ 471#define PCI_EXP_DEVCAP 4 /* Device capabilities */ 472#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */ 473#define PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */ 474#define PCI_EXP_DEVCAP_EXT_TAG 0x00000020 /* Extended tags */ 475#define PCI_EXP_DEVCAP_L0S 0x000001c0 /* L0s Acceptable Latency */ 476#define PCI_EXP_DEVCAP_L1 0x00000e00 /* L1 Acceptable Latency */ 477#define PCI_EXP_DEVCAP_ATN_BUT 0x00001000 /* Attention Button Present */ 478#define PCI_EXP_DEVCAP_ATN_IND 0x00002000 /* Attention Indicator Present */ 479#define PCI_EXP_DEVCAP_PWR_IND 0x00004000 /* Power Indicator Present */ 480#define PCI_EXP_DEVCAP_RBER 0x00008000 /* Role-Based Error Reporting */ 481#define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 /* Slot Power Limit Value */ 482#define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 /* Slot Power Limit Scale */ 483#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ 484#define PCI_EXP_DEVCTL 8 /* Device Control */ 485#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ 486#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ 487#define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */ 488#define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */ 489#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ 490#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ 491#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ 492#define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */ 493#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ 494#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ 495#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ 496#define PCI_EXP_DEVCTL_READRQ_128B 0x0000 /* 128 Bytes */ 497#define PCI_EXP_DEVCTL_READRQ_256B 0x1000 /* 256 Bytes */ 498#define PCI_EXP_DEVCTL_READRQ_512B 0x2000 /* 512 Bytes */ 499#define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */ 500#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ 501#define PCI_EXP_DEVSTA 10 /* Device Status */ 502#define PCI_EXP_DEVSTA_CED 0x0001 /* Correctable Error Detected */ 503#define PCI_EXP_DEVSTA_NFED 0x0002 /* Non-Fatal Error Detected */ 504#define PCI_EXP_DEVSTA_FED 0x0004 /* Fatal Error Detected */ 505#define PCI_EXP_DEVSTA_URD 0x0008 /* Unsupported Request Detected */ 506#define PCI_EXP_DEVSTA_AUXPD 0x0010 /* AUX Power Detected */ 507#define PCI_EXP_DEVSTA_TRPND 0x0020 /* Transactions Pending */ 508#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ 509#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ 510#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */ 511#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */ 512#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ 513#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ 514#define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ 515#define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */ 516#define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* Clock Power Management */ 517#define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Surprise Down Error Reporting Capable */ 518#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ 519#define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */ 520#define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ 521#define PCI_EXP_LNKCTL 16 /* Link Control */ 522#define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */ 523#define PCI_EXP_LNKCTL_ASPM_L0S 0x0001 /* L0s Enable */ 524#define PCI_EXP_LNKCTL_ASPM_L1 0x0002 /* L1 Enable */ 525#define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ 526#define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */ 527#define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */ 528#define PCI_EXP_LNKCTL_CCC 0x0040 /* Common Clock Configuration */ 529#define PCI_EXP_LNKCTL_ES 0x0080 /* Extended Synch */ 530#define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */ 531#define PCI_EXP_LNKCTL_HAWD 0x0200 /* Hardware Autonomous Width Disable */ 532#define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */ 533#define PCI_EXP_LNKCTL_LABIE 0x0800 /* Link Autonomous Bandwidth Interrupt Enable */ 534#define PCI_EXP_LNKSTA 18 /* Link Status */ 535#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ 536#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ 537#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ 538#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 539#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ 540#define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */ 541#define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */ 542#define PCI_EXP_LNKSTA_NLW_X4 0x0040 /* Current Link Width x4 */ 543#define PCI_EXP_LNKSTA_NLW_X8 0x0080 /* Current Link Width x8 */ 544#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ 545#define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ 546#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ 547#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ 548#define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */ 549#define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */ 550#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 /* v1 endpoints end here */ 551#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ 552#define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */ 553#define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */ 554#define PCI_EXP_SLTCAP_MRLSP 0x00000004 /* MRL Sensor Present */ 555#define PCI_EXP_SLTCAP_AIP 0x00000008 /* Attention Indicator Present */ 556#define PCI_EXP_SLTCAP_PIP 0x00000010 /* Power Indicator Present */ 557#define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */ 558#define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */ 559#define PCI_EXP_SLTCAP_SPLV 0x00007f80 /* Slot Power Limit Value */ 560#define PCI_EXP_SLTCAP_SPLS 0x00018000 /* Slot Power Limit Scale */ 561#define PCI_EXP_SLTCAP_EIP 0x00020000 /* Electromechanical Interlock Present */ 562#define PCI_EXP_SLTCAP_NCCS 0x00040000 /* No Command Completed Support */ 563#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ 564#define PCI_EXP_SLTCTL 24 /* Slot Control */ 565#define PCI_EXP_SLTCTL_ABPE 0x0001 /* Attention Button Pressed Enable */ 566#define PCI_EXP_SLTCTL_PFDE 0x0002 /* Power Fault Detected Enable */ 567#define PCI_EXP_SLTCTL_MRLSCE 0x0004 /* MRL Sensor Changed Enable */ 568#define PCI_EXP_SLTCTL_PDCE 0x0008 /* Presence Detect Changed Enable */ 569#define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */ 570#define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */ 571#define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */ 572#define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 /* Attention Indicator on */ 573#define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking */ 574#define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 /* Attention Indicator off */ 575#define PCI_EXP_SLTCTL_PIC 0x0300 /* Power Indicator Control */ 576#define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100 /* Power Indicator on */ 577#define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200 /* Power Indicator blinking */ 578#define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300 /* Power Indicator off */ 579#define PCI_EXP_SLTCTL_PCC 0x0400 /* Power Controller Control */ 580#define PCI_EXP_SLTCTL_PWR_ON 0x0000 /* Power On */ 581#define PCI_EXP_SLTCTL_PWR_OFF 0x0400 /* Power Off */ 582#define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */ 583#define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */ 584#define PCI_EXP_SLTSTA 26 /* Slot Status */ 585#define PCI_EXP_SLTSTA_ABP 0x0001 /* Attention Button Pressed */ 586#define PCI_EXP_SLTSTA_PFD 0x0002 /* Power Fault Detected */ 587#define PCI_EXP_SLTSTA_MRLSC 0x0004 /* MRL Sensor Changed */ 588#define PCI_EXP_SLTSTA_PDC 0x0008 /* Presence Detect Changed */ 589#define PCI_EXP_SLTSTA_CC 0x0010 /* Command Completed */ 590#define PCI_EXP_SLTSTA_MRLSS 0x0020 /* MRL Sensor State */ 591#define PCI_EXP_SLTSTA_PDS 0x0040 /* Presence Detect State */ 592#define PCI_EXP_SLTSTA_EIS 0x0080 /* Electromechanical Interlock Status */ 593#define PCI_EXP_SLTSTA_DLLSC 0x0100 /* Data Link Layer State Changed */ 594#define PCI_EXP_RTCTL 28 /* Root Control */ 595#define PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */ 596#define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */ 597#define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */ 598#define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */ 599#define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */ 600#define PCI_EXP_RTCAP 30 /* Root Capabilities */ 601#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ 602#define PCI_EXP_RTSTA 32 /* Root Status */ 603#define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */ 604#define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */ 605/* 606 * The Device Capabilities 2, Device Status 2, Device Control 2, 607 * Link Capabilities 2, Link Status 2, Link Control 2, 608 * Slot Capabilities 2, Slot Status 2, and Slot Control 2 registers 609 * are only present on devices with PCIe Capability version 2. 610 * Use pcie_capability_read_word() and similar interfaces to use them 611 * safely. 612 */ 613#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ 614#define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */ 615#define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */ 616#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ 617#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ 618#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */ 619#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ 620#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */ 621#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ 622#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */ 623#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */ 624#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */ 625#define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000 /* Enable OBFF Message type A */ 626#define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 /* Enable OBFF Message type B */ 627#define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ 628#define PCI_EXP_DEVSTA2 42 /* Device Status 2 */ 629#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */ 630#define PCI_EXP_LNKCAP2 44 /* Link Capabilities 2 */ 631#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */ 632#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5.0GT/s */ 633#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8.0GT/s */ 634#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ 635#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ 636#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ 637#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ 638#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */ 639#define PCI_EXP_SLTSTA2 58 /* Slot Status 2 */ 640 641/* Extended Capabilities (PCI-X 2.0 and Express) */ 642#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 643#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 644#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 645 646#define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ 647#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */ 648#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ 649#define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */ 650#define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */ 651#define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */ 652#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ 653#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ 654#define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ 655#define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ 656#define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */ 657#define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ 658#define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ 659#define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ 660#define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */ 661#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ 662#define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ 663#define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ 664#define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ 665#define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */ 666#define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */ 667#define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */ 668#define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */ 669#define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */ 670#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */ 671#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ 672#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ 673#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID 674 675#define PCI_EXT_CAP_DSN_SIZEOF 12 676#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 677 678/* Advanced Error Reporting */ 679#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ 680#define PCI_ERR_UNC_UND 0x00000001 /* Undefined */ 681#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ 682#define PCI_ERR_UNC_SURPDN 0x00000020 /* Surprise Down */ 683#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ 684#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ 685#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ 686#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */ 687#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */ 688#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */ 689#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ 690#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ 691#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ 692#define PCI_ERR_UNC_ACSV 0x00200000 /* ACS Violation */ 693#define PCI_ERR_UNC_INTN 0x00400000 /* internal error */ 694#define PCI_ERR_UNC_MCBTLP 0x00800000 /* MC blocked TLP */ 695#define PCI_ERR_UNC_ATOMEG 0x01000000 /* Atomic egress blocked */ 696#define PCI_ERR_UNC_TLPPRE 0x02000000 /* TLP prefix blocked */ 697#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */ 698 /* Same bits as above */ 699#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */ 700 /* Same bits as above */ 701#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */ 702#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */ 703#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */ 704#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ 705#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ 706#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ 707#define PCI_ERR_COR_ADV_NFAT 0x00002000 /* Advisory Non-Fatal */ 708#define PCI_ERR_COR_INTERNAL 0x00004000 /* Corrected Internal */ 709#define PCI_ERR_COR_LOG_OVER 0x00008000 /* Header Log Overflow */ 710#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */ 711 /* Same bits as above */ 712#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */ 713#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */ 714#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */ 715#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */ 716#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */ 717#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ 718#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */ 719#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */ 720/* Correctable Err Reporting Enable */ 721#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 722/* Non-fatal Err Reporting Enable */ 723#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 724/* Fatal Err Reporting Enable */ 725#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 726#define PCI_ERR_ROOT_STATUS 48 727#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ 728/* Multi ERR_COR Received */ 729#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 730/* ERR_FATAL/NONFATAL Received */ 731#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 732/* Multi ERR_FATAL/NONFATAL Received */ 733#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 734#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */ 735#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ 736#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ 737#define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ 738 739/* Virtual Channel */ 740#define PCI_VC_PORT_CAP1 4 741#define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */ 742#define PCI_VC_CAP1_LPEVCC 0x00000070 /* low prio extended VC count */ 743#define PCI_VC_CAP1_ARB_SIZE 0x00000c00 744#define PCI_VC_PORT_CAP2 8 745#define PCI_VC_CAP2_32_PHASE 0x00000002 746#define PCI_VC_CAP2_64_PHASE 0x00000004 747#define PCI_VC_CAP2_128_PHASE 0x00000008 748#define PCI_VC_CAP2_ARB_OFF 0xff000000 749#define PCI_VC_PORT_CTRL 12 750#define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 751#define PCI_VC_PORT_STATUS 14 752#define PCI_VC_PORT_STATUS_TABLE 0x00000001 753#define PCI_VC_RES_CAP 16 754#define PCI_VC_RES_CAP_32_PHASE 0x00000002 755#define PCI_VC_RES_CAP_64_PHASE 0x00000004 756#define PCI_VC_RES_CAP_128_PHASE 0x00000008 757#define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010 758#define PCI_VC_RES_CAP_256_PHASE 0x00000020 759#define PCI_VC_RES_CAP_ARB_OFF 0xff000000 760#define PCI_VC_RES_CTRL 20 761#define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000 762#define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000 763#define PCI_VC_RES_CTRL_ID 0x07000000 764#define PCI_VC_RES_CTRL_ENABLE 0x80000000 765#define PCI_VC_RES_STATUS 26 766#define PCI_VC_RES_STATUS_TABLE 0x00000001 767#define PCI_VC_RES_STATUS_NEGO 0x00000002 768#define PCI_CAP_VC_BASE_SIZEOF 0x10 769#define PCI_CAP_VC_PER_VC_SIZEOF 0x0C 770 771/* Power Budgeting */ 772#define PCI_PWR_DSR 4 /* Data Select Register */ 773#define PCI_PWR_DATA 8 /* Data Register */ 774#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ 775#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ 776#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ 777#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ 778#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ 779#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ 780#define PCI_PWR_CAP 12 /* Capability */ 781#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ 782#define PCI_EXT_CAP_PWR_SIZEOF 16 783 784/* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */ 785#define PCI_VNDR_HEADER 4 /* Vendor-Specific Header */ 786#define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff) 787#define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf) 788#define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) 789 790/* 791 * HyperTransport sub capability types 792 * 793 * Unfortunately there are both 3 bit and 5 bit capability types defined 794 * in the HT spec, catering for that is a little messy. You probably don't 795 * want to use these directly, just use pci_find_ht_capability() and it 796 * will do the right thing for you. 797 */ 798#define HT_3BIT_CAP_MASK 0xE0 799#define HT_CAPTYPE_SLAVE 0x00 /* Slave/Primary link configuration */ 800#define HT_CAPTYPE_HOST 0x20 /* Host/Secondary link configuration */ 801 802#define HT_5BIT_CAP_MASK 0xF8 803#define HT_CAPTYPE_IRQ 0x80 /* IRQ Configuration */ 804#define HT_CAPTYPE_REMAPPING_40 0xA0 /* 40 bit address remapping */ 805#define HT_CAPTYPE_REMAPPING_64 0xA2 /* 64 bit address remapping */ 806#define HT_CAPTYPE_UNITID_CLUMP 0x90 /* Unit ID clumping */ 807#define HT_CAPTYPE_EXTCONF 0x98 /* Extended Configuration Space Access */ 808#define HT_CAPTYPE_MSI_MAPPING 0xA8 /* MSI Mapping Capability */ 809#define HT_MSI_FLAGS 0x02 /* Offset to flags */ 810#define HT_MSI_FLAGS_ENABLE 0x1 /* Mapping enable */ 811#define HT_MSI_FLAGS_FIXED 0x2 /* Fixed mapping only */ 812#define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL /* Fixed addr */ 813#define HT_MSI_ADDR_LO 0x04 /* Offset to low addr bits */ 814#define HT_MSI_ADDR_LO_MASK 0xFFF00000 /* Low address bit mask */ 815#define HT_MSI_ADDR_HI 0x08 /* Offset to high addr bits */ 816#define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */ 817#define HT_CAPTYPE_VCSET 0xB8 /* Virtual Channel configuration */ 818#define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */ 819#define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 HyperTransport configuration */ 820#define HT_CAPTYPE_PM 0xE0 /* HyperTransport power management configuration */ 821#define HT_CAP_SIZEOF_LONG 28 /* slave & primary */ 822#define HT_CAP_SIZEOF_SHORT 24 /* host & secondary */ 823 824/* Alternative Routing-ID Interpretation */ 825#define PCI_ARI_CAP 0x04 /* ARI Capability Register */ 826#define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */ 827#define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */ 828#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */ 829#define PCI_ARI_CTRL 0x06 /* ARI Control Register */ 830#define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */ 831#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ 832#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ 833#define PCI_EXT_CAP_ARI_SIZEOF 8 834 835/* Address Translation Service */ 836#define PCI_ATS_CAP 0x04 /* ATS Capability Register */ 837#define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) /* Invalidate Queue Depth */ 838#define PCI_ATS_MAX_QDEP 32 /* Max Invalidate Queue Depth */ 839#define PCI_ATS_CTRL 0x06 /* ATS Control Register */ 840#define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */ 841#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */ 842#define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */ 843#define PCI_EXT_CAP_ATS_SIZEOF 8 844 845/* Page Request Interface */ 846#define PCI_PRI_CTRL 0x04 /* PRI control register */ 847#define PCI_PRI_CTRL_ENABLE 0x01 /* Enable */ 848#define PCI_PRI_CTRL_RESET 0x02 /* Reset */ 849#define PCI_PRI_STATUS 0x06 /* PRI status register */ 850#define PCI_PRI_STATUS_RF 0x001 /* Response Failure */ 851#define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */ 852#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */ 853#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */ 854#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ 855#define PCI_EXT_CAP_PRI_SIZEOF 16 856 857/* Process Address Space ID */ 858#define PCI_PASID_CAP 0x04 /* PASID feature register */ 859#define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */ 860#define PCI_PASID_CAP_PRIV 0x04 /* Privilege Mode Supported */ 861#define PCI_PASID_CTRL 0x06 /* PASID control register */ 862#define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ 863#define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ 864#define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */ 865#define PCI_EXT_CAP_PASID_SIZEOF 8 866 867/* Single Root I/O Virtualization */ 868#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ 869#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */ 870#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */ 871#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ 872#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */ 873#define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */ 874#define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */ 875#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */ 876#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */ 877#define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */ 878#define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */ 879#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ 880#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ 881#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ 882#define PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */ 883#define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */ 884#define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */ 885#define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ 886#define PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */ 887#define PCI_SRIOV_SYS_PGSIZE 0x20 /* System Page Size */ 888#define PCI_SRIOV_BAR 0x24 /* VF BAR0 */ 889#define PCI_SRIOV_NUM_BARS 6 /* Number of VF BARs */ 890#define PCI_SRIOV_VFM 0x3c /* VF Migration State Array Offset*/ 891#define PCI_SRIOV_VFM_BIR(x) ((x) & 7) /* State BIR */ 892#define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) /* State Offset */ 893#define PCI_SRIOV_VFM_UA 0x0 /* Inactive.Unavailable */ 894#define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */ 895#define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */ 896#define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */ 897#define PCI_EXT_CAP_SRIOV_SIZEOF 64 898 899#define PCI_LTR_MAX_SNOOP_LAT 0x4 900#define PCI_LTR_MAX_NOSNOOP_LAT 0x6 901#define PCI_LTR_VALUE_MASK 0x000003ff 902#define PCI_LTR_SCALE_MASK 0x00001c00 903#define PCI_LTR_SCALE_SHIFT 10 904#define PCI_EXT_CAP_LTR_SIZEOF 8 905 906/* Access Control Service */ 907#define PCI_ACS_CAP 0x04 /* ACS Capability Register */ 908#define PCI_ACS_SV 0x01 /* Source Validation */ 909#define PCI_ACS_TB 0x02 /* Translation Blocking */ 910#define PCI_ACS_RR 0x04 /* P2P Request Redirect */ 911#define PCI_ACS_CR 0x08 /* P2P Completion Redirect */ 912#define PCI_ACS_UF 0x10 /* Upstream Forwarding */ 913#define PCI_ACS_EC 0x20 /* P2P Egress Control */ 914#define PCI_ACS_DT 0x40 /* Direct Translated P2P */ 915#define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */ 916#define PCI_ACS_CTRL 0x06 /* ACS Control Register */ 917#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ 918 919#define PCI_VSEC_HDR 4 /* extended cap - vendor-specific */ 920#define PCI_VSEC_HDR_LEN_SHIFT 20 /* shift for length field */ 921 922/* SATA capability */ 923#define PCI_SATA_REGS 4 /* SATA REGs specifier */ 924#define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */ 925#define PCI_SATA_REGS_INLINE 0xF /* REGS in config space */ 926#define PCI_SATA_SIZEOF_SHORT 8 927#define PCI_SATA_SIZEOF_LONG 16 928 929/* Resizable BARs */ 930#define PCI_REBAR_CTRL 8 /* control register */ 931#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) /* mask for # bars */ 932#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # bars */ 933 934/* Dynamic Power Allocation */ 935#define PCI_DPA_CAP 4 /* capability register */ 936#define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */ 937#define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */ 938 939/* TPH Requester */ 940#define PCI_TPH_CAP 4 /* capability register */ 941#define PCI_TPH_CAP_LOC_MASK 0x600 /* location mask */ 942#define PCI_TPH_LOC_NONE 0x000 /* no location */ 943#define PCI_TPH_LOC_CAP 0x200 /* in capability */ 944#define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */ 945#define PCI_TPH_CAP_ST_MASK 0x07FF0000 /* st table mask */ 946#define PCI_TPH_CAP_ST_SHIFT 16 /* st table shift */ 947#define PCI_TPH_BASE_SIZEOF 12 /* size with no st table */ 948 949#endif /* LINUX_PCI_REGS_H */ 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