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21#ifndef _V4L2_DV_TIMINGS_H
22#define _V4L2_DV_TIMINGS_H
23
24#if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6))
25
26
27
28
29#define V4L2_INIT_BT_TIMINGS(_width, args...) \
30 { .bt = { _width , ## args } }
31#else
32#define V4L2_INIT_BT_TIMINGS(_width, args...) \
33 .bt = { _width , ## args }
34#endif
35
36
37
38#define V4L2_DV_BT_CEA_640X480P59_94 { \
39 .type = V4L2_DV_BT_656_1120, \
40 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
41 25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \
42 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, 0) \
43}
44
45
46
47#define V4L2_DV_BT_CEA_720X480I59_94 { \
48 .type = V4L2_DV_BT_656_1120, \
49 V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \
50 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \
51 V4L2_DV_BT_STD_CEA861, \
52 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO) \
53}
54
55#define V4L2_DV_BT_CEA_720X480P59_94 { \
56 .type = V4L2_DV_BT_656_1120, \
57 V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
58 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
59 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
60}
61
62
63
64#define V4L2_DV_BT_CEA_720X576I50 { \
65 .type = V4L2_DV_BT_656_1120, \
66 V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \
67 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \
68 V4L2_DV_BT_STD_CEA861, \
69 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO) \
70}
71
72#define V4L2_DV_BT_CEA_720X576P50 { \
73 .type = V4L2_DV_BT_656_1120, \
74 V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
75 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
76 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
77}
78
79#define V4L2_DV_BT_CEA_1280X720P24 { \
80 .type = V4L2_DV_BT_656_1120, \
81 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
82 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
83 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
84 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
85 V4L2_DV_FL_CAN_REDUCE_FPS) \
86}
87
88#define V4L2_DV_BT_CEA_1280X720P25 { \
89 .type = V4L2_DV_BT_656_1120, \
90 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
91 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
92 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \
93 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
94}
95
96#define V4L2_DV_BT_CEA_1280X720P30 { \
97 .type = V4L2_DV_BT_656_1120, \
98 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
99 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
100 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
101 V4L2_DV_BT_STD_CEA861, \
102 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
103}
104
105#define V4L2_DV_BT_CEA_1280X720P50 { \
106 .type = V4L2_DV_BT_656_1120, \
107 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
108 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
109 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \
110 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
111}
112
113#define V4L2_DV_BT_CEA_1280X720P60 { \
114 .type = V4L2_DV_BT_656_1120, \
115 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
116 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
117 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \
118 V4L2_DV_BT_STD_CEA861, \
119 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
120}
121
122#define V4L2_DV_BT_CEA_1920X1080P24 { \
123 .type = V4L2_DV_BT_656_1120, \
124 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
125 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
126 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
127 V4L2_DV_BT_STD_CEA861, \
128 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
129}
130
131#define V4L2_DV_BT_CEA_1920X1080P25 { \
132 .type = V4L2_DV_BT_656_1120, \
133 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
134 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
135 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
136 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
137}
138
139#define V4L2_DV_BT_CEA_1920X1080P30 { \
140 .type = V4L2_DV_BT_656_1120, \
141 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
142 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
143 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
144 V4L2_DV_BT_STD_CEA861, \
145 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
146}
147
148#define V4L2_DV_BT_CEA_1920X1080I50 { \
149 .type = V4L2_DV_BT_656_1120, \
150 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
151 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
152 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \
153 V4L2_DV_BT_STD_CEA861, \
154 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO) \
155}
156
157#define V4L2_DV_BT_CEA_1920X1080P50 { \
158 .type = V4L2_DV_BT_656_1120, \
159 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
160 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
161 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
162 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
163}
164
165#define V4L2_DV_BT_CEA_1920X1080I60 { \
166 .type = V4L2_DV_BT_656_1120, \
167 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
168 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
169 74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \
170 V4L2_DV_BT_STD_CEA861, \
171 V4L2_DV_FL_CAN_REDUCE_FPS | \
172 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO) \
173}
174
175#define V4L2_DV_BT_CEA_1920X1080P60 { \
176 .type = V4L2_DV_BT_656_1120, \
177 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
178 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
179 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
180 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
181 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
182}
183
184#define V4L2_DV_BT_CEA_3840X2160P24 { \
185 .type = V4L2_DV_BT_656_1120, \
186 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
187 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
188 297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
189 V4L2_DV_BT_STD_CEA861, \
190 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
191}
192
193#define V4L2_DV_BT_CEA_3840X2160P25 { \
194 .type = V4L2_DV_BT_656_1120, \
195 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
196 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
197 297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
198 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
199}
200
201#define V4L2_DV_BT_CEA_3840X2160P30 { \
202 .type = V4L2_DV_BT_656_1120, \
203 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
204 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
205 297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
206 V4L2_DV_BT_STD_CEA861, \
207 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
208}
209
210#define V4L2_DV_BT_CEA_3840X2160P50 { \
211 .type = V4L2_DV_BT_656_1120, \
212 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
213 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
214 594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
215 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
216}
217
218#define V4L2_DV_BT_CEA_3840X2160P60 { \
219 .type = V4L2_DV_BT_656_1120, \
220 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
221 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
222 594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
223 V4L2_DV_BT_STD_CEA861, \
224 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
225}
226
227#define V4L2_DV_BT_CEA_4096X2160P24 { \
228 .type = V4L2_DV_BT_656_1120, \
229 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
230 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
231 297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \
232 V4L2_DV_BT_STD_CEA861, \
233 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
234}
235
236#define V4L2_DV_BT_CEA_4096X2160P25 { \
237 .type = V4L2_DV_BT_656_1120, \
238 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
239 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
240 297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
241 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
242}
243
244#define V4L2_DV_BT_CEA_4096X2160P30 { \
245 .type = V4L2_DV_BT_656_1120, \
246 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
247 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
248 297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
249 V4L2_DV_BT_STD_CEA861, \
250 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
251}
252
253#define V4L2_DV_BT_CEA_4096X2160P50 { \
254 .type = V4L2_DV_BT_656_1120, \
255 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
256 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
257 594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
258 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
259}
260
261#define V4L2_DV_BT_CEA_4096X2160P60 { \
262 .type = V4L2_DV_BT_656_1120, \
263 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
264 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
265 594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
266 V4L2_DV_BT_STD_CEA861, \
267 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
268}
269
270
271
272
273#define V4L2_DV_BT_DMT_640X350P85 { \
274 .type = V4L2_DV_BT_656_1120, \
275 V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \
276 31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \
277 V4L2_DV_BT_STD_DMT, 0) \
278}
279
280#define V4L2_DV_BT_DMT_640X400P85 { \
281 .type = V4L2_DV_BT_656_1120, \
282 V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
283 31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \
284 V4L2_DV_BT_STD_DMT, 0) \
285}
286
287#define V4L2_DV_BT_DMT_720X400P85 { \
288 .type = V4L2_DV_BT_656_1120, \
289 V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
290 35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \
291 V4L2_DV_BT_STD_DMT, 0) \
292}
293
294
295#define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94
296
297#define V4L2_DV_BT_DMT_640X480P72 { \
298 .type = V4L2_DV_BT_656_1120, \
299 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
300 31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \
301 V4L2_DV_BT_STD_DMT, 0) \
302}
303
304#define V4L2_DV_BT_DMT_640X480P75 { \
305 .type = V4L2_DV_BT_656_1120, \
306 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
307 31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \
308 V4L2_DV_BT_STD_DMT, 0) \
309}
310
311#define V4L2_DV_BT_DMT_640X480P85 { \
312 .type = V4L2_DV_BT_656_1120, \
313 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
314 36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \
315 V4L2_DV_BT_STD_DMT, 0) \
316}
317
318
319#define V4L2_DV_BT_DMT_800X600P56 { \
320 .type = V4L2_DV_BT_656_1120, \
321 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
322 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
323 36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \
324 V4L2_DV_BT_STD_DMT, 0) \
325}
326
327#define V4L2_DV_BT_DMT_800X600P60 { \
328 .type = V4L2_DV_BT_656_1120, \
329 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
330 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
331 40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \
332 V4L2_DV_BT_STD_DMT, 0) \
333}
334
335#define V4L2_DV_BT_DMT_800X600P72 { \
336 .type = V4L2_DV_BT_656_1120, \
337 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
338 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
339 50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \
340 V4L2_DV_BT_STD_DMT, 0) \
341}
342
343#define V4L2_DV_BT_DMT_800X600P75 { \
344 .type = V4L2_DV_BT_656_1120, \
345 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
346 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
347 49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \
348 V4L2_DV_BT_STD_DMT, 0) \
349}
350
351#define V4L2_DV_BT_DMT_800X600P85 { \
352 .type = V4L2_DV_BT_656_1120, \
353 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
354 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
355 56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \
356 V4L2_DV_BT_STD_DMT, 0) \
357}
358
359#define V4L2_DV_BT_DMT_800X600P120_RB { \
360 .type = V4L2_DV_BT_656_1120, \
361 V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \
362 73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \
363 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
364 V4L2_DV_FL_REDUCED_BLANKING) \
365}
366
367#define V4L2_DV_BT_DMT_848X480P60 { \
368 .type = V4L2_DV_BT_656_1120, \
369 V4L2_INIT_BT_TIMINGS(848, 480, 0, \
370 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
371 33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \
372 V4L2_DV_BT_STD_DMT, 0) \
373}
374
375#define V4L2_DV_BT_DMT_1024X768I43 { \
376 .type = V4L2_DV_BT_656_1120, \
377 V4L2_INIT_BT_TIMINGS(1024, 768, 1, \
378 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
379 44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \
380 V4L2_DV_BT_STD_DMT, 0) \
381}
382
383
384#define V4L2_DV_BT_DMT_1024X768P60 { \
385 .type = V4L2_DV_BT_656_1120, \
386 V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
387 65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \
388 V4L2_DV_BT_STD_DMT, 0) \
389}
390
391#define V4L2_DV_BT_DMT_1024X768P70 { \
392 .type = V4L2_DV_BT_656_1120, \
393 V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
394 75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \
395 V4L2_DV_BT_STD_DMT, 0) \
396}
397
398#define V4L2_DV_BT_DMT_1024X768P75 { \
399 .type = V4L2_DV_BT_656_1120, \
400 V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
401 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
402 78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \
403 V4L2_DV_BT_STD_DMT, 0) \
404}
405
406#define V4L2_DV_BT_DMT_1024X768P85 { \
407 .type = V4L2_DV_BT_656_1120, \
408 V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
409 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
410 94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \
411 V4L2_DV_BT_STD_DMT, 0) \
412}
413
414#define V4L2_DV_BT_DMT_1024X768P120_RB { \
415 .type = V4L2_DV_BT_656_1120, \
416 V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \
417 115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \
418 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
419 V4L2_DV_FL_REDUCED_BLANKING) \
420}
421
422
423#define V4L2_DV_BT_DMT_1152X864P75 { \
424 .type = V4L2_DV_BT_656_1120, \
425 V4L2_INIT_BT_TIMINGS(1152, 864, 0, \
426 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
427 108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \
428 V4L2_DV_BT_STD_DMT, 0) \
429}
430
431#define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60
432
433
434#define V4L2_DV_BT_DMT_1280X768P60_RB { \
435 .type = V4L2_DV_BT_656_1120, \
436 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
437 68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \
438 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
439 V4L2_DV_FL_REDUCED_BLANKING) \
440}
441
442#define V4L2_DV_BT_DMT_1280X768P60 { \
443 .type = V4L2_DV_BT_656_1120, \
444 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
445 79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \
446 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
447}
448
449#define V4L2_DV_BT_DMT_1280X768P75 { \
450 .type = V4L2_DV_BT_656_1120, \
451 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
452 102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \
453 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
454}
455
456#define V4L2_DV_BT_DMT_1280X768P85 { \
457 .type = V4L2_DV_BT_656_1120, \
458 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
459 117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \
460 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
461}
462
463#define V4L2_DV_BT_DMT_1280X768P120_RB { \
464 .type = V4L2_DV_BT_656_1120, \
465 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
466 140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \
467 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
468 V4L2_DV_FL_REDUCED_BLANKING) \
469}
470
471#define V4L2_DV_BT_DMT_1280X800P60_RB { \
472 .type = V4L2_DV_BT_656_1120, \
473 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
474 71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \
475 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
476 V4L2_DV_FL_REDUCED_BLANKING) \
477}
478
479#define V4L2_DV_BT_DMT_1280X800P60 { \
480 .type = V4L2_DV_BT_656_1120, \
481 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
482 83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \
483 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
484}
485
486#define V4L2_DV_BT_DMT_1280X800P75 { \
487 .type = V4L2_DV_BT_656_1120, \
488 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
489 106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \
490 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
491}
492
493#define V4L2_DV_BT_DMT_1280X800P85 { \
494 .type = V4L2_DV_BT_656_1120, \
495 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
496 122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \
497 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
498}
499
500#define V4L2_DV_BT_DMT_1280X800P120_RB { \
501 .type = V4L2_DV_BT_656_1120, \
502 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
503 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \
504 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
505 V4L2_DV_FL_REDUCED_BLANKING) \
506}
507
508#define V4L2_DV_BT_DMT_1280X960P60 { \
509 .type = V4L2_DV_BT_656_1120, \
510 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
511 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
512 108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \
513 V4L2_DV_BT_STD_DMT, 0) \
514}
515
516#define V4L2_DV_BT_DMT_1280X960P85 { \
517 .type = V4L2_DV_BT_656_1120, \
518 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
519 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
520 148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \
521 V4L2_DV_BT_STD_DMT, 0) \
522}
523
524#define V4L2_DV_BT_DMT_1280X960P120_RB { \
525 .type = V4L2_DV_BT_656_1120, \
526 V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \
527 175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \
528 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
529 V4L2_DV_FL_REDUCED_BLANKING) \
530}
531
532
533#define V4L2_DV_BT_DMT_1280X1024P60 { \
534 .type = V4L2_DV_BT_656_1120, \
535 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
536 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
537 108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \
538 V4L2_DV_BT_STD_DMT, 0) \
539}
540
541#define V4L2_DV_BT_DMT_1280X1024P75 { \
542 .type = V4L2_DV_BT_656_1120, \
543 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
544 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
545 135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \
546 V4L2_DV_BT_STD_DMT, 0) \
547}
548
549#define V4L2_DV_BT_DMT_1280X1024P85 { \
550 .type = V4L2_DV_BT_656_1120, \
551 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
552 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
553 157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \
554 V4L2_DV_BT_STD_DMT, 0) \
555}
556
557#define V4L2_DV_BT_DMT_1280X1024P120_RB { \
558 .type = V4L2_DV_BT_656_1120, \
559 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \
560 187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \
561 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
562 V4L2_DV_FL_REDUCED_BLANKING) \
563}
564
565#define V4L2_DV_BT_DMT_1360X768P60 { \
566 .type = V4L2_DV_BT_656_1120, \
567 V4L2_INIT_BT_TIMINGS(1360, 768, 0, \
568 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
569 85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \
570 V4L2_DV_BT_STD_DMT, 0) \
571}
572
573#define V4L2_DV_BT_DMT_1360X768P120_RB { \
574 .type = V4L2_DV_BT_656_1120, \
575 V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \
576 148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \
577 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
578 V4L2_DV_FL_REDUCED_BLANKING) \
579}
580
581#define V4L2_DV_BT_DMT_1366X768P60 { \
582 .type = V4L2_DV_BT_656_1120, \
583 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
584 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
585 85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \
586 V4L2_DV_BT_STD_DMT, 0) \
587}
588
589#define V4L2_DV_BT_DMT_1366X768P60_RB { \
590 .type = V4L2_DV_BT_656_1120, \
591 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
592 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
593 72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \
594 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
595}
596
597
598#define V4L2_DV_BT_DMT_1400X1050P60_RB { \
599 .type = V4L2_DV_BT_656_1120, \
600 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
601 101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \
602 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
603 V4L2_DV_FL_REDUCED_BLANKING) \
604}
605
606#define V4L2_DV_BT_DMT_1400X1050P60 { \
607 .type = V4L2_DV_BT_656_1120, \
608 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
609 121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \
610 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
611}
612
613#define V4L2_DV_BT_DMT_1400X1050P75 { \
614 .type = V4L2_DV_BT_656_1120, \
615 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
616 156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \
617 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
618}
619
620#define V4L2_DV_BT_DMT_1400X1050P85 { \
621 .type = V4L2_DV_BT_656_1120, \
622 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
623 179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \
624 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
625}
626
627#define V4L2_DV_BT_DMT_1400X1050P120_RB { \
628 .type = V4L2_DV_BT_656_1120, \
629 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
630 208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \
631 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
632 V4L2_DV_FL_REDUCED_BLANKING) \
633}
634
635
636#define V4L2_DV_BT_DMT_1440X900P60_RB { \
637 .type = V4L2_DV_BT_656_1120, \
638 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
639 88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \
640 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
641 V4L2_DV_FL_REDUCED_BLANKING) \
642}
643
644#define V4L2_DV_BT_DMT_1440X900P60 { \
645 .type = V4L2_DV_BT_656_1120, \
646 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
647 106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \
648 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
649}
650
651#define V4L2_DV_BT_DMT_1440X900P75 { \
652 .type = V4L2_DV_BT_656_1120, \
653 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
654 136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \
655 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
656}
657
658#define V4L2_DV_BT_DMT_1440X900P85 { \
659 .type = V4L2_DV_BT_656_1120, \
660 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
661 157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \
662 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
663}
664
665#define V4L2_DV_BT_DMT_1440X900P120_RB { \
666 .type = V4L2_DV_BT_656_1120, \
667 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
668 182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \
669 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
670 V4L2_DV_FL_REDUCED_BLANKING) \
671}
672
673#define V4L2_DV_BT_DMT_1600X900P60_RB { \
674 .type = V4L2_DV_BT_656_1120, \
675 V4L2_INIT_BT_TIMINGS(1600, 900, 0, \
676 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
677 108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \
678 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
679}
680
681
682#define V4L2_DV_BT_DMT_1600X1200P60 { \
683 .type = V4L2_DV_BT_656_1120, \
684 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
685 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
686 162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
687 V4L2_DV_BT_STD_DMT, 0) \
688}
689
690#define V4L2_DV_BT_DMT_1600X1200P65 { \
691 .type = V4L2_DV_BT_656_1120, \
692 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
693 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
694 175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
695 V4L2_DV_BT_STD_DMT, 0) \
696}
697
698#define V4L2_DV_BT_DMT_1600X1200P70 { \
699 .type = V4L2_DV_BT_656_1120, \
700 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
701 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
702 189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
703 V4L2_DV_BT_STD_DMT, 0) \
704}
705
706#define V4L2_DV_BT_DMT_1600X1200P75 { \
707 .type = V4L2_DV_BT_656_1120, \
708 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
709 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
710 202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
711 V4L2_DV_BT_STD_DMT, 0) \
712}
713
714#define V4L2_DV_BT_DMT_1600X1200P85 { \
715 .type = V4L2_DV_BT_656_1120, \
716 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
717 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
718 229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
719 V4L2_DV_BT_STD_DMT, 0) \
720}
721
722#define V4L2_DV_BT_DMT_1600X1200P120_RB { \
723 .type = V4L2_DV_BT_656_1120, \
724 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
725 268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \
726 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
727 V4L2_DV_FL_REDUCED_BLANKING) \
728}
729
730
731#define V4L2_DV_BT_DMT_1680X1050P60_RB { \
732 .type = V4L2_DV_BT_656_1120, \
733 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
734 119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \
735 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
736 V4L2_DV_FL_REDUCED_BLANKING) \
737}
738
739#define V4L2_DV_BT_DMT_1680X1050P60 { \
740 .type = V4L2_DV_BT_656_1120, \
741 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
742 146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \
743 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
744}
745
746#define V4L2_DV_BT_DMT_1680X1050P75 { \
747 .type = V4L2_DV_BT_656_1120, \
748 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
749 187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \
750 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
751}
752
753#define V4L2_DV_BT_DMT_1680X1050P85 { \
754 .type = V4L2_DV_BT_656_1120, \
755 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
756 214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \
757 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
758}
759
760#define V4L2_DV_BT_DMT_1680X1050P120_RB { \
761 .type = V4L2_DV_BT_656_1120, \
762 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
763 245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \
764 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
765 V4L2_DV_FL_REDUCED_BLANKING) \
766}
767
768#define V4L2_DV_BT_DMT_1792X1344P60 { \
769 .type = V4L2_DV_BT_656_1120, \
770 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
771 204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \
772 V4L2_DV_BT_STD_DMT, 0) \
773}
774
775#define V4L2_DV_BT_DMT_1792X1344P75 { \
776 .type = V4L2_DV_BT_656_1120, \
777 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
778 261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \
779 V4L2_DV_BT_STD_DMT, 0) \
780}
781
782#define V4L2_DV_BT_DMT_1792X1344P120_RB { \
783 .type = V4L2_DV_BT_656_1120, \
784 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \
785 333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \
786 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
787 V4L2_DV_FL_REDUCED_BLANKING) \
788}
789
790#define V4L2_DV_BT_DMT_1856X1392P60 { \
791 .type = V4L2_DV_BT_656_1120, \
792 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
793 218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \
794 V4L2_DV_BT_STD_DMT, 0) \
795}
796
797#define V4L2_DV_BT_DMT_1856X1392P75 { \
798 .type = V4L2_DV_BT_656_1120, \
799 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
800 288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \
801 V4L2_DV_BT_STD_DMT, 0) \
802}
803
804#define V4L2_DV_BT_DMT_1856X1392P120_RB { \
805 .type = V4L2_DV_BT_656_1120, \
806 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \
807 356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \
808 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
809 V4L2_DV_FL_REDUCED_BLANKING) \
810}
811
812#define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60
813
814
815#define V4L2_DV_BT_DMT_1920X1200P60_RB { \
816 .type = V4L2_DV_BT_656_1120, \
817 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
818 154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \
819 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
820 V4L2_DV_FL_REDUCED_BLANKING) \
821}
822
823#define V4L2_DV_BT_DMT_1920X1200P60 { \
824 .type = V4L2_DV_BT_656_1120, \
825 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
826 193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \
827 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
828}
829
830#define V4L2_DV_BT_DMT_1920X1200P75 { \
831 .type = V4L2_DV_BT_656_1120, \
832 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
833 245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \
834 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
835}
836
837#define V4L2_DV_BT_DMT_1920X1200P85 { \
838 .type = V4L2_DV_BT_656_1120, \
839 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
840 281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \
841 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
842}
843
844#define V4L2_DV_BT_DMT_1920X1200P120_RB { \
845 .type = V4L2_DV_BT_656_1120, \
846 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
847 317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \
848 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
849 V4L2_DV_FL_REDUCED_BLANKING) \
850}
851
852#define V4L2_DV_BT_DMT_1920X1440P60 { \
853 .type = V4L2_DV_BT_656_1120, \
854 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
855 234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \
856 V4L2_DV_BT_STD_DMT, 0) \
857}
858
859#define V4L2_DV_BT_DMT_1920X1440P75 { \
860 .type = V4L2_DV_BT_656_1120, \
861 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
862 297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \
863 V4L2_DV_BT_STD_DMT, 0) \
864}
865
866#define V4L2_DV_BT_DMT_1920X1440P120_RB { \
867 .type = V4L2_DV_BT_656_1120, \
868 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \
869 380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \
870 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
871 V4L2_DV_FL_REDUCED_BLANKING) \
872}
873
874#define V4L2_DV_BT_DMT_2048X1152P60_RB { \
875 .type = V4L2_DV_BT_656_1120, \
876 V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \
877 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
878 162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \
879 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
880}
881
882
883#define V4L2_DV_BT_DMT_2560X1600P60_RB { \
884 .type = V4L2_DV_BT_656_1120, \
885 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
886 268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \
887 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
888 V4L2_DV_FL_REDUCED_BLANKING) \
889}
890
891#define V4L2_DV_BT_DMT_2560X1600P60 { \
892 .type = V4L2_DV_BT_656_1120, \
893 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
894 348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \
895 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
896}
897
898#define V4L2_DV_BT_DMT_2560X1600P75 { \
899 .type = V4L2_DV_BT_656_1120, \
900 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
901 443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \
902 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
903}
904
905#define V4L2_DV_BT_DMT_2560X1600P85 { \
906 .type = V4L2_DV_BT_656_1120, \
907 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
908 505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \
909 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
910}
911
912#define V4L2_DV_BT_DMT_2560X1600P120_RB { \
913 .type = V4L2_DV_BT_656_1120, \
914 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
915 552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \
916 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
917 V4L2_DV_FL_REDUCED_BLANKING) \
918}
919
920
921#define V4L2_DV_BT_DMT_4096X2160P60_RB { \
922 .type = V4L2_DV_BT_656_1120, \
923 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
924 556744000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \
925 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
926 V4L2_DV_FL_REDUCED_BLANKING) \
927}
928
929#define V4L2_DV_BT_DMT_4096X2160P59_94_RB { \
930 .type = V4L2_DV_BT_656_1120, \
931 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
932 556188000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \
933 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
934 V4L2_DV_FL_REDUCED_BLANKING) \
935}
936
937#endif
938
