1/* 2 * Xilinx Controls Header 3 * 4 * Copyright (C) 2013-2015 Ideas on Board 5 * Copyright (C) 2013-2015 Xilinx, Inc. 6 * 7 * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> 8 * Laurent Pinchart <laurent.pinchart@ideasonboard.com> 9 * 10 * This software is licensed under the terms of the GNU General Public 11 * License version 2, as published by the Free Software Foundation, and 12 * may be copied, distributed, and modified under those terms. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20#ifndef __UAPI_XILINX_V4L2_CONTROLS_H__ 21#define __UAPI_XILINX_V4L2_CONTROLS_H__ 22 23#include <linux/v4l2-controls.h> 24 25#define V4L2_CID_XILINX_OFFSET 0xc000 26#define V4L2_CID_XILINX_BASE (V4L2_CID_USER_BASE + V4L2_CID_XILINX_OFFSET) 27 28/* 29 * Private Controls for Xilinx Video IPs 30 */ 31 32/* 33 * Xilinx TPG Video IP 34 */ 35 36#define V4L2_CID_XILINX_TPG (V4L2_CID_USER_BASE + 0xc000) 37 38/* Draw cross hairs */ 39#define V4L2_CID_XILINX_TPG_CROSS_HAIRS (V4L2_CID_XILINX_TPG + 1) 40/* Enable a moving box */ 41#define V4L2_CID_XILINX_TPG_MOVING_BOX (V4L2_CID_XILINX_TPG + 2) 42/* Mask out a color component */ 43#define V4L2_CID_XILINX_TPG_COLOR_MASK (V4L2_CID_XILINX_TPG + 3) 44/* Enable a stuck pixel feature */ 45#define V4L2_CID_XILINX_TPG_STUCK_PIXEL (V4L2_CID_XILINX_TPG + 4) 46/* Enable a noisy output */ 47#define V4L2_CID_XILINX_TPG_NOISE (V4L2_CID_XILINX_TPG + 5) 48/* Enable the motion feature */ 49#define V4L2_CID_XILINX_TPG_MOTION (V4L2_CID_XILINX_TPG + 6) 50/* Configure the motion speed of moving patterns */ 51#define V4L2_CID_XILINX_TPG_MOTION_SPEED (V4L2_CID_XILINX_TPG + 7) 52/* The row of horizontal cross hair location */ 53#define V4L2_CID_XILINX_TPG_CROSS_HAIR_ROW (V4L2_CID_XILINX_TPG + 8) 54/* The colum of vertical cross hair location */ 55#define V4L2_CID_XILINX_TPG_CROSS_HAIR_COLUMN (V4L2_CID_XILINX_TPG + 9) 56/* Set starting point of sine wave for horizontal component */ 57#define V4L2_CID_XILINX_TPG_ZPLATE_HOR_START (V4L2_CID_XILINX_TPG + 10) 58/* Set speed of the horizontal component */ 59#define V4L2_CID_XILINX_TPG_ZPLATE_HOR_SPEED (V4L2_CID_XILINX_TPG + 11) 60/* Set starting point of sine wave for vertical component */ 61#define V4L2_CID_XILINX_TPG_ZPLATE_VER_START (V4L2_CID_XILINX_TPG + 12) 62/* Set speed of the vertical component */ 63#define V4L2_CID_XILINX_TPG_ZPLATE_VER_SPEED (V4L2_CID_XILINX_TPG + 13) 64/* Moving box size */ 65#define V4L2_CID_XILINX_TPG_BOX_SIZE (V4L2_CID_XILINX_TPG + 14) 66/* Moving box color */ 67#define V4L2_CID_XILINX_TPG_BOX_COLOR (V4L2_CID_XILINX_TPG + 15) 68/* Upper limit count of generated stuck pixels */ 69#define V4L2_CID_XILINX_TPG_STUCK_PIXEL_THRESH (V4L2_CID_XILINX_TPG + 16) 70/* Noise level */ 71#define V4L2_CID_XILINX_TPG_NOISE_GAIN (V4L2_CID_XILINX_TPG + 17) 72/* Foreground pattern (HLS)*/ 73#define V4L2_CID_XILINX_TPG_HLS_FG_PATTERN (V4L2_CID_XILINX_TPG + 18) 74 75 76/* 77 * Xilinx CRESAMPLE Video IP 78 */ 79 80#define V4L2_CID_XILINX_CRESAMPLE (V4L2_CID_USER_BASE + 0xc020) 81 82/* The field parity for interlaced video */ 83#define V4L2_CID_XILINX_CRESAMPLE_FIELD_PARITY (V4L2_CID_XILINX_CRESAMPLE + 1) 84/* Specify if the first line of video contains the Chroma infomation */ 85#define V4L2_CID_XILINX_CRESAMPLE_CHROMA_PARITY (V4L2_CID_XILINX_CRESAMPLE + 2) 86 87/* 88 * Xilinx RGB2YUV Video IPs 89 */ 90 91#define V4L2_CID_XILINX_RGB2YUV (V4L2_CID_USER_BASE + 0xc040) 92 93/* Maximum Luma(Y) value */ 94#define V4L2_CID_XILINX_RGB2YUV_YMAX (V4L2_CID_XILINX_RGB2YUV + 1) 95/* Minimum Luma(Y) value */ 96#define V4L2_CID_XILINX_RGB2YUV_YMIN (V4L2_CID_XILINX_RGB2YUV + 2) 97/* Maximum Cb Chroma value */ 98#define V4L2_CID_XILINX_RGB2YUV_CBMAX (V4L2_CID_XILINX_RGB2YUV + 3) 99/* Minimum Cb Chroma value */ 100#define V4L2_CID_XILINX_RGB2YUV_CBMIN (V4L2_CID_XILINX_RGB2YUV + 4) 101/* Maximum Cr Chroma value */ 102#define V4L2_CID_XILINX_RGB2YUV_CRMAX (V4L2_CID_XILINX_RGB2YUV + 5) 103/* Minimum Cr Chroma value */ 104#define V4L2_CID_XILINX_RGB2YUV_CRMIN (V4L2_CID_XILINX_RGB2YUV + 6) 105/* The offset compensation value for Luma(Y) */ 106#define V4L2_CID_XILINX_RGB2YUV_YOFFSET (V4L2_CID_XILINX_RGB2YUV + 7) 107/* The offset compensation value for Cb Chroma */ 108#define V4L2_CID_XILINX_RGB2YUV_CBOFFSET (V4L2_CID_XILINX_RGB2YUV + 8) 109/* The offset compensation value for Cr Chroma */ 110#define V4L2_CID_XILINX_RGB2YUV_CROFFSET (V4L2_CID_XILINX_RGB2YUV + 9) 111 112/* Y = CA * R + (1 - CA - CB) * G + CB * B */ 113 114/* CA coefficient */ 115#define V4L2_CID_XILINX_RGB2YUV_ACOEF (V4L2_CID_XILINX_RGB2YUV + 10) 116/* CB coefficient */ 117#define V4L2_CID_XILINX_RGB2YUV_BCOEF (V4L2_CID_XILINX_RGB2YUV + 11) 118/* CC coefficient */ 119#define V4L2_CID_XILINX_RGB2YUV_CCOEF (V4L2_CID_XILINX_RGB2YUV + 12) 120/* CD coefficient */ 121#define V4L2_CID_XILINX_RGB2YUV_DCOEF (V4L2_CID_XILINX_RGB2YUV + 13) 122 123/* 124 * Xilinx HLS Video IP 125 */ 126 127#define V4L2_CID_XILINX_HLS (V4L2_CID_USER_BASE + 0xc060) 128 129/* The IP model */ 130#define V4L2_CID_XILINX_HLS_MODEL (V4L2_CID_XILINX_HLS + 1) 131 132/* 133 * Xilinx MIPI CSI2 Rx Subsystem 134 */ 135 136/* Base ID */ 137#define V4L2_CID_XILINX_MIPICSISS (V4L2_CID_USER_BASE + 0xc080) 138 139/* Active Lanes */ 140#define V4L2_CID_XILINX_MIPICSISS_ACT_LANES (V4L2_CID_XILINX_MIPICSISS + 1) 141/* Frames received since streaming is set */ 142#define V4L2_CID_XILINX_MIPICSISS_FRAME_COUNTER (V4L2_CID_XILINX_MIPICSISS + 2) 143/* Reset all event counters */ 144#define V4L2_CID_XILINX_MIPICSISS_RESET_COUNTERS (V4L2_CID_XILINX_MIPICSISS + 3) 145 146#endif /* __UAPI_XILINX_V4L2_CONTROLS_H__ */ 147