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20#ifndef _XCL_ZOCL_IOCTL_H_
21#define _XCL_ZOCL_IOCTL_H_
22
23enum {
24 DRM_ZOCL_CREATE_BO = 0,
25 DRM_ZOCL_MAP_BO,
26 DRM_ZOCL_SYNC_BO,
27 DRM_ZOCL_INFO_BO,
28 DRM_ZOCL_PWRITE_BO,
29 DRM_ZOCL_PREAD_BO,
30 DRM_ZOCL_NUM_IOCTLS
31};
32
33enum drm_zocl_sync_bo_dir {
34 DRM_ZOCL_SYNC_BO_TO_DEVICE,
35 DRM_ZOCL_SYNC_BO_FROM_DEVICE
36};
37
38#define DRM_ZOCL_BO_FLAGS_COHERENT 0x00000001
39#define DRM_ZOCL_BO_FLAGS_CMA 0x00000002
40
41struct drm_zocl_create_bo {
42 uint64_t size;
43 uint32_t handle;
44 uint32_t flags;
45};
46
47struct drm_zocl_map_bo {
48 uint32_t handle;
49 uint32_t pad;
50 uint64_t offset;
51};
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60struct drm_zocl_sync_bo {
61 uint32_t handle;
62 enum drm_zocl_sync_bo_dir dir;
63 uint64_t offset;
64 uint64_t size;
65};
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73struct drm_zocl_info_bo {
74 uint32_t handle;
75 uint64_t size;
76 uint64_t paddr;
77};
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87struct drm_zocl_pwrite_bo {
88 uint32_t handle;
89 uint32_t pad;
90 uint64_t offset;
91 uint64_t size;
92 uint64_t data_ptr;
93};
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103struct drm_zocl_pread_bo {
104 uint32_t handle;
105 uint32_t pad;
106 uint64_t offset;
107 uint64_t size;
108 uint64_t data_ptr;
109};
110
111#define DRM_IOCTL_ZOCL_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + \
112 DRM_ZOCL_CREATE_BO, \
113 struct drm_zocl_create_bo)
114#define DRM_IOCTL_ZOCL_MAP_BO DRM_IOWR(DRM_COMMAND_BASE + \
115 DRM_ZOCL_MAP_BO, struct drm_zocl_map_bo)
116#define DRM_IOCTL_ZOCL_SYNC_BO DRM_IOWR(DRM_COMMAND_BASE + \
117 DRM_ZOCL_SYNC_BO, struct drm_zocl_sync_bo)
118#define DRM_IOCTL_ZOCL_INFO_BO DRM_IOWR(DRM_COMMAND_BASE + \
119 DRM_ZOCL_INFO_BO, struct drm_zocl_info_bo)
120#define DRM_IOCTL_ZOCL_PWRITE_BO DRM_IOWR(DRM_COMMAND_BASE + \
121 DRM_ZOCL_PWRITE_BO, \
122 struct drm_zocl_pwrite_bo)
123#define DRM_IOCTL_ZOCL_PREAD_BO DRM_IOWR(DRM_COMMAND_BASE + \
124 DRM_ZOCL_PREAD_BO, struct drm_zocl_pread_bo)
125#endif
126