LXR linux/samples/xilinx

   1#ifndef XAXIPMON_H /* Prevent circular inclusions */
   2#define XAXIPMON_H /* by using protection macros  */
   3
   4#ifdef __cplusplus
   5extern "C" {
   6#endif
   7
   8#include <stdint.h>
   9#include <stdbool.h>
  10
  11
  12#define XST_SUCCESS     0
  13#define XST_FAILURE     1
  14
  15#ifndef TRUE
  16#define TRUE            1
  17#endif
  18
  19#ifndef FALSE
  20#define FALSE           0
  21#endif
  22
  23#ifndef NULL
  24#define NULL            0
  25#endif
  26
  27#define XAPM_GCC_HIGH_OFFSET            0x0000  /* Global Clock Counter
  28                                                        32 to 63 bits  */
  29#define XAPM_GCC_LOW_OFFSET             0x0004  /* Global Clock Counter Lower
  30                                                        0-31 bits  */
  31#define XAPM_SI_HIGH_OFFSET             0x0020  /* Sample Interval MSB */
  32#define XAPM_SI_LOW_OFFSET              0x0024  /* Sample Interval LSB */
  33#define XAPM_SICR_OFFSET                0x0028  /* Sample Interval Control
  34                                                        Register */
  35#define XAPM_SR_OFFSET                  0x002C  /* Sample Register */
  36#define XAPM_GIE_OFFSET                 0x0030  /* Global Interrupt Enable
  37                                                        Register */
  38#define XAPM_IE_OFFSET                  0x0034  /* Interrupt Enable Register */
  39#define XAPM_IS_OFFSET                  0x0038  /* Interrupt Status Register */
  40
  41#define XAPM_MSR0_OFFSET                0x0044  /* Metric Selector 0 Register*/
  42#define XAPM_MSR1_OFFSET                0x0048  /* Metric Selector 1 Register*/
  43#define XAPM_MSR2_OFFSET                0x004C  /* Metric Selector 2 Register*/
  44
  45#define XAPM_MC0_OFFSET                 0x0100  /* Metric Counter 0 Register */
  46#define XAPM_INC0_OFFSET                0x0104  /* Incrementer 0 Register */
  47#define XAPM_RANGE0_OFFSET              0x0108  /* Range 0 Register */
  48#define XAPM_MC0LOGEN_OFFSET            0x010C  /* Metric Counter 0
  49                                                        Log Enable Register */
  50#define XAPM_MC1_OFFSET                 0x0110  /* Metric Counter 1 Register */
  51#define XAPM_INC1_OFFSET                0x0114  /* Incrementer 1 Register */
  52#define XAPM_RANGE1_OFFSET              0x0118  /* Range 1 Register */
  53#define XAPM_MC1LOGEN_OFFSET            0x011C  /* Metric Counter 1
  54                                                        Log Enable Register */
  55#define XAPM_MC2_OFFSET                 0x0120  /* Metric Counter 2 Register */
  56#define XAPM_INC2_OFFSET                0x0124  /* Incrementer 2 Register */
  57#define XAPM_RANGE2_OFFSET              0x0128  /* Range 2 Register */
  58#define XAPM_MC2LOGEN_OFFSET            0x012C  /* Metric Counter 2
  59                                                        Log Enable Register */
  60#define XAPM_MC3_OFFSET                 0x0130  /* Metric Counter 3 Register */
  61#define XAPM_INC3_OFFSET                0x0134  /* Incrementer 3 Register */
  62#define XAPM_RANGE3_OFFSET              0x0138  /* Range 3 Register */
  63#define XAPM_MC3LOGEN_OFFSET            0x013C  /* Metric Counter 3
  64                                                        Log Enable Register */
  65#define XAPM_MC4_OFFSET                 0x0140  /* Metric Counter 4 Register */
  66#define XAPM_INC4_OFFSET                0x0144  /* Incrementer 4 Register */
  67#define XAPM_RANGE4_OFFSET              0x0148  /* Range 4 Register */
  68#define XAPM_MC4LOGEN_OFFSET            0x014C  /* Metric Counter 4
  69                                                        Log Enable Register */
  70#define XAPM_MC5_OFFSET                 0x0150  /* Metric Counter 5
  71                                                        Register */
  72#define XAPM_INC5_OFFSET                0x0154  /* Incrementer 5 Register */
  73#define XAPM_RANGE5_OFFSET              0x0158  /* Range 5 Register */
  74#define XAPM_MC5LOGEN_OFFSET            0x015C  /* Metric Counter 5
  75                                                        Log Enable Register */
  76#define XAPM_MC6_OFFSET                 0x0160  /* Metric Counter 6
  77                                                        Register */
  78#define XAPM_INC6_OFFSET                0x0164  /* Incrementer 6 Register */
  79#define XAPM_RANGE6_OFFSET              0x0168  /* Range 6 Register */
  80#define XAPM_MC6LOGEN_OFFSET            0x016C  /* Metric Counter 6
  81                                                        Log Enable Register */
  82#define XAPM_MC7_OFFSET                 0x0170  /* Metric Counter 7
  83                                                        Register */
  84#define XAPM_INC7_OFFSET                0x0174  /* Incrementer 7 Register */
  85#define XAPM_RANGE7_OFFSET              0x0178  /* Range 7 Register */
  86#define XAPM_MC7LOGEN_OFFSET            0x017C  /* Metric Counter 7
  87                                                        Log Enable Register */
  88#define XAPM_MC8_OFFSET                 0x0180  /* Metric Counter 8
  89                                                        Register */
  90#define XAPM_INC8_OFFSET                0x0184  /* Incrementer 8 Register */
  91#define XAPM_RANGE8_OFFSET              0x0188  /* Range 8 Register */
  92#define XAPM_MC8LOGEN_OFFSET            0x018C  /* Metric Counter 8
  93                                                        Log Enable Register */
  94#define XAPM_MC9_OFFSET                 0x0190  /* Metric Counter 9
  95                                                        Register */
  96#define XAPM_INC9_OFFSET                0x0194  /* Incrementer 9 Register */
  97#define XAPM_RANGE9_OFFSET              0x0198  /* Range 9 Register */
  98#define XAPM_MC9LOGEN_OFFSET            0x019C  /* Metric Counter 9
  99                                                        Log Enable Register */
 100
 101#define XAPM_MC10_OFFSET                0x01A0  /* Metric Counter 10
 102                                                        Register */
 103#define XAPM_MC11_OFFSET                0x01B0  /* Metric Counter 11
 104                                                        Register */
 105#define XAPM_MC12_OFFSET                0x0500  /* Metric Counter 12
 106                                                        Register */
 107#define XAPM_MC13_OFFSET                0x0510  /* Metric Counter 13
 108                                                        Register */
 109#define XAPM_MC14_OFFSET                0x0520  /* Metric Counter 14
 110                                                        Register */
 111#define XAPM_MC15_OFFSET                0x0530  /* Metric Counter 15
 112                                                        Register */
 113#define XAPM_MC16_OFFSET                0x0540  /* Metric Counter 16
 114                                                        Register */
 115#define XAPM_MC17_OFFSET                0x0550  /* Metric Counter 17
 116                                                        Register */
 117#define XAPM_MC18_OFFSET                0x0560  /* Metric Counter 18
 118                                                        Register */
 119#define XAPM_MC19_OFFSET                0x0570  /* Metric Counter 19
 120                                                        Register */
 121#define XAPM_MC20_OFFSET                0x0580  /* Metric Counter 20
 122                                                        Register */
 123#define XAPM_MC21_OFFSET                0x0590  /* Metric Counter 21
 124                                                        Register */
 125#define XAPM_MC22_OFFSET                0x05A0  /* Metric Counter 22
 126                                                        Register */
 127#define XAPM_MC23_OFFSET                0x05B0  /* Metric Counter 23
 128                                                        Register */
 129#define XAPM_MC24_OFFSET                0x0700  /* Metric Counter 24
 130                                                        Register */
 131#define XAPM_MC25_OFFSET                0x0710  /* Metric Counter 25
 132                                                        Register */
 133#define XAPM_MC26_OFFSET                0x0720  /* Metric Counter 26
 134                                                        Register */
 135#define XAPM_MC27_OFFSET                0x0730  /* Metric Counter 27
 136                                                        Register */
 137#define XAPM_MC28_OFFSET                0x0740  /* Metric Counter 28
 138                                                        Register */
 139#define XAPM_MC29_OFFSET                0x0750  /* Metric Counter 29
 140                                                        Register */
 141#define XAPM_MC30_OFFSET                0x0760  /* Metric Counter 30
 142                                                        Register */
 143#define XAPM_MC31_OFFSET                0x0770  /* Metric Counter 31
 144                                                        Register */
 145#define XAPM_MC32_OFFSET                0x0780  /* Metric Counter 32
 146                                                        Register */
 147#define XAPM_MC33_OFFSET                0x0790  /* Metric Counter 33
 148                                                        Register */
 149#define XAPM_MC34_OFFSET                0x07A0  /* Metric Counter 34
 150                                                        Register */
 151#define XAPM_MC35_OFFSET                0x07B0  /* Metric Counter 35
 152                                                        Register */
 153#define XAPM_MC36_OFFSET                0x0900  /* Metric Counter 36
 154                                                        Register */
 155#define XAPM_MC37_OFFSET                0x0910  /* Metric Counter 37
 156                                                        Register */
 157#define XAPM_MC38_OFFSET                0x0920  /* Metric Counter 38
 158                                                        Register */
 159#define XAPM_MC39_OFFSET                0x0930  /* Metric Counter 39
 160                                                        Register */
 161#define XAPM_MC40_OFFSET                0x0940  /* Metric Counter 40
 162                                                        Register */
 163#define XAPM_MC41_OFFSET                0x0950  /* Metric Counter 41
 164                                                        Register */
 165#define XAPM_MC42_OFFSET                0x0960  /* Metric Counter 42
 166                                                        Register */
 167#define XAPM_MC43_OFFSET                0x0970  /* Metric Counter 43
 168                                                        Register */
 169#define XAPM_MC44_OFFSET                0x0980  /* Metric Counter 44
 170                                                        Register */
 171#define XAPM_MC45_OFFSET                0x0990  /* Metric Counter 45
 172                                                        Register */
 173#define XAPM_MC46_OFFSET                0x09A0  /* Metric Counter 46
 174                                                        Register */
 175#define XAPM_MC47_OFFSET                0x09B0  /* Metric Counter 47
 176                                                        Register */
 177
 178#define XAPM_SMC0_OFFSET                0x0200  /* Sampled Metric Counter
 179                                                        0 Register */
 180#define XAPM_SINC0_OFFSET               0x0204  /* Sampled Incrementer
 181                                                        0 Register */
 182#define XAPM_SMC1_OFFSET                0x0210  /* Sampled Metric Counter
 183                                                        1 Register */
 184#define XAPM_SINC1_OFFSET               0x0214  /* Sampled Incrementer
 185                                                        1 Register */
 186#define XAPM_SMC2_OFFSET                0x0220  /* Sampled Metric Counter
 187                                                        2 Register */
 188#define XAPM_SINC2_OFFSET               0x0224  /* Sampled Incrementer
 189                                                        2 Register */
 190#define XAPM_SMC3_OFFSET                0x0230  /* Sampled Metric Counter
 191                                                        3 Register */
 192#define XAPM_SINC3_OFFSET               0x0234  /* Sampled Incrementer
 193                                                        3 Register */
 194#define XAPM_SMC4_OFFSET                0x0240  /* Sampled Metric Counter
 195                                                        4 Register */
 196#define XAPM_SINC4_OFFSET               0x0244  /* Sampled Incrementer
 197                                                        4 Register */
 198#define XAPM_SMC5_OFFSET                0x0250  /* Sampled Metric Counter
 199                                                        5 Register */
 200#define XAPM_SINC5_OFFSET               0x0254  /* Sampled Incrementer
 201                                                        5 Register */
 202#define XAPM_SMC6_OFFSET                0x0260  /* Sampled Metric Counter
 203                                                        6 Register */
 204#define XAPM_SINC6_OFFSET               0x0264  /* Sampled Incrementer
 205                                                        6 Register */
 206#define XAPM_SMC7_OFFSET                0x0270  /* Sampled Metric Counter
 207                                                        7 Register */
 208#define XAPM_SINC7_OFFSET               0x0274  /* Sampled Incrementer
 209                                                        7 Register */
 210#define XAPM_SMC8_OFFSET                0x0280  /* Sampled Metric Counter
 211                                                        8 Register */
 212#define XAPM_SINC8_OFFSET               0x0284  /* Sampled Incrementer
 213                                                        8 Register */
 214#define XAPM_SMC9_OFFSET                0x0290  /* Sampled Metric Counter
 215                                                        9 Register */
 216#define XAPM_SINC9_OFFSET               0x0294  /* Sampled Incrementer
 217                                                        9 Register */
 218#define XAPM_SMC10_OFFSET               0x02A0  /* Sampled Metric Counter
 219                                                        10 Register */
 220#define XAPM_SMC11_OFFSET               0x02B0  /* Sampled Metric Counter
 221                                                        11 Register */
 222#define XAPM_SMC12_OFFSET               0x0600  /* Sampled Metric Counter
 223                                                        12 Register */
 224#define XAPM_SMC13_OFFSET               0x0610  /* Sampled Metric Counter
 225                                                        13 Register */
 226#define XAPM_SMC14_OFFSET               0x0620  /* Sampled Metric Counter
 227                                                        14 Register */
 228#define XAPM_SMC15_OFFSET               0x0630  /* Sampled Metric Counter
 229                                                        15 Register */
 230#define XAPM_SMC16_OFFSET               0x0640  /* Sampled Metric Counter
 231                                                        16 Register */
 232#define XAPM_SMC17_OFFSET               0x0650  /* Sampled Metric Counter
 233                                                        17 Register */
 234#define XAPM_SMC18_OFFSET               0x0660  /* Sampled Metric Counter
 235                                                        18 Register */
 236#define XAPM_SMC19_OFFSET               0x0670  /* Sampled Metric Counter
 237                                                        19 Register */
 238#define XAPM_SMC20_OFFSET               0x0680  /* Sampled Metric Counter
 239                                                        20 Register */
 240#define XAPM_SMC21_OFFSET               0x0690  /* Sampled Metric Counter
 241                                                        21 Register */
 242#define XAPM_SMC22_OFFSET               0x06A0  /* Sampled Metric Counter
 243                                                        22 Register */
 244#define XAPM_SMC23_OFFSET               0x06B0  /* Sampled Metric Counter
 245                                                        23 Register */
 246#define XAPM_SMC24_OFFSET               0x0800  /* Sampled Metric Counter
 247                                                        24 Register */
 248#define XAPM_SMC25_OFFSET               0x0810  /* Sampled Metric Counter
 249                                                        25 Register */
 250#define XAPM_SMC26_OFFSET               0x0820  /* Sampled Metric Counter
 251                                                        26 Register */
 252#define XAPM_SMC27_OFFSET               0x0830  /* Sampled Metric Counter
 253                                                        27 Register */
 254#define XAPM_SMC28_OFFSET               0x0840  /* Sampled Metric Counter
 255                                                        28 Register */
 256#define XAPM_SMC29_OFFSET               0x0850  /* Sampled Metric Counter
 257                                                        29 Register */
 258#define XAPM_SMC30_OFFSET               0x0860  /* Sampled Metric Counter
 259                                                        30 Register */
 260#define XAPM_SMC31_OFFSET               0x0870  /* Sampled Metric Counter
 261                                                        31 Register */
 262#define XAPM_SMC32_OFFSET               0x0880  /* Sampled Metric Counter
 263                                                        32 Register */
 264#define XAPM_SMC33_OFFSET               0x0890  /* Sampled Metric Counter
 265                                                        33 Register */
 266#define XAPM_SMC34_OFFSET               0x08A0  /* Sampled Metric Counter
 267                                                        34 Register */
 268#define XAPM_SMC35_OFFSET               0x08B0  /* Sampled Metric Counter
 269                                                        35 Register */
 270#define XAPM_SMC36_OFFSET               0x0A00  /* Sampled Metric Counter
 271                                                        36 Register */
 272#define XAPM_SMC37_OFFSET               0x0A10  /* Sampled Metric Counter
 273                                                        37 Register */
 274#define XAPM_SMC38_OFFSET               0x0A20  /* Sampled Metric Counter
 275                                                        38 Register */
 276#define XAPM_SMC39_OFFSET               0x0A30  /* Sampled Metric Counter
 277                                                        39 Register */
 278#define XAPM_SMC40_OFFSET               0x0A40  /* Sampled Metric Counter
 279                                                        40 Register */
 280#define XAPM_SMC41_OFFSET               0x0A50  /* Sampled Metric Counter
 281                                                        41 Register */
 282#define XAPM_SMC42_OFFSET               0x0A60  /* Sampled Metric Counter
 283                                                        42 Register */
 284#define XAPM_SMC43_OFFSET               0x0A70  /* Sampled Metric Counter
 285                                                        43 Register */
 286#define XAPM_SMC44_OFFSET               0x0A80  /* Sampled Metric Counter
 287                                                        44 Register */
 288#define XAPM_SMC45_OFFSET               0x0A90  /* Sampled Metric Counter
 289                                                        45 Register */
 290#define XAPM_SMC46_OFFSET               0x0AA0  /* Sampled Metric Counter
 291                                                        46 Register */
 292#define XAPM_SMC47_OFFSET               0x0AB0  /* Sampled Metric Counter
 293                                                        47 Register */
 294
 295#define XAPM_CTL_OFFSET                 0x0300  /* Control Register */
 296
 297#define XAPM_ID_OFFSET                  0x0304  /* Latency ID Register */
 298
 299#define XAPM_IDMASK_OFFSET              0x0308  /* ID Mask Register */
 300
 301#define XAPM_RID_OFFSET                 0x030C  /* Latency Write ID Register */
 302
 303#define XAPM_RIDMASK_OFFSET             0x0310  /* Read ID mask register */
 304
 305#define XAPM_FEC_OFFSET                 0x0400  /* flag Enable
 306                                                        Control Register */
 307
 308#define XAPM_SWD_OFFSET                 0x0404  /* Software-written
 309                                                        Data Register */
 310
 311#define XAPM_SICR_MCNTR_RST_MASK        0x00000100 /* Enable the Metric
 312                                                        Counter Reset */
 313#define XAPM_SICR_LOAD_MASK             0x00000002 /* Load the Sample Interval
 314                                                        Register Value into
 315                                                        the counter */
 316#define XAPM_SICR_ENABLE_MASK           0x00000001 /* Enable the downcounter */
 317
 318#define XAPM_IXR_MC9_OVERFLOW_MASK      0x00001000      /**< Metric Counter 9
 319                                                          *  Overflow> */
 320#define XAPM_IXR_MC8_OVERFLOW_MASK      0x00000800      /**< Metric Counter 8
 321                                                          *  Overflow> */
 322#define XAPM_IXR_MC7_OVERFLOW_MASK      0x00000400      /**< Metric Counter 7
 323                                                          *  Overflow> */
 324#define XAPM_IXR_MC6_OVERFLOW_MASK      0x00000200      /**< Metric Counter 6
 325                                                          *  Overflow> */
 326#define XAPM_IXR_MC5_OVERFLOW_MASK      0x00000100      /**< Metric Counter 5
 327                                                          *  Overflow> */
 328#define XAPM_IXR_MC4_OVERFLOW_MASK      0x00000080      /**< Metric Counter 4
 329                                                          *  Overflow> */
 330#define XAPM_IXR_MC3_OVERFLOW_MASK      0x00000040      /**< Metric Counter 3
 331                                                          *  Overflow> */
 332#define XAPM_IXR_MC2_OVERFLOW_MASK      0x00000020      /**< Metric Counter 2
 333                                                          *  Overflow> */
 334#define XAPM_IXR_MC1_OVERFLOW_MASK      0x00000010      /**< Metric Counter 1
 335                                                          *  Overflow> */
 336#define XAPM_IXR_MC0_OVERFLOW_MASK      0x00000008      /**< Metric Counter 0
 337                                                          *  Overflow> */
 338#define XAPM_IXR_FIFO_FULL_MASK         0x00000004      /**< Event Log FIFO
 339                                                          *  full> */
 340#define XAPM_IXR_SIC_OVERFLOW_MASK      0x00000002      /**< Sample Interval
 341                                                          * Counter Overflow */
 342#define XAPM_IXR_GCC_OVERFLOW_MASK      0x00000001      /**< Global Clock
 343                                                        Counter Overflow */
 344#define XAPM_IXR_ALL_MASK               (XAPM_IXR_SIC_OVERFLOW_MASK | \
 345                                        XAPM_IXR_GCC_OVERFLOW_MASK |  \
 346                                        XAPM_IXR_FIFO_FULL_MASK | \
 347                                        XAPM_IXR_MC0_OVERFLOW_MASK | \
 348                                        XAPM_IXR_MC1_OVERFLOW_MASK | \
 349                                        XAPM_IXR_MC2_OVERFLOW_MASK | \
 350                                        XAPM_IXR_MC3_OVERFLOW_MASK | \
 351                                        XAPM_IXR_MC4_OVERFLOW_MASK | \
 352                                        XAPM_IXR_MC5_OVERFLOW_MASK | \
 353                                        XAPM_IXR_MC6_OVERFLOW_MASK | \
 354                                        XAPM_IXR_MC7_OVERFLOW_MASK | \
 355                                        XAPM_IXR_MC8_OVERFLOW_MASK | \
 356                                        XAPM_IXR_MC9_OVERFLOW_MASK)
 357
 358#define XAPM_CR_FIFO_RESET_MASK                 0x02000000
 359                                                /**< FIFO Reset */
 360#define XAPM_CR_MUXSEL_MASK                     0x01000000
 361                                                /**< Mux Selector mask */
 362#define XAPM_CR_GCC_RESET_MASK                  0x00020000
 363                                                /**< Global Clk
 364                                                  Counter Reset */
 365#define XAPM_CR_GCC_ENABLE_MASK                 0x00010000
 366                                                /**< Global Clk
 367                                                   Counter Enable */
 368#define XAPM_CR_EVTLOG_EXTTRIGGER_MASK          0x00000200
 369                                                /**< Enable External trigger
 370                                                to start event Log */
 371#define XAPM_CR_EVENTLOG_ENABLE_MASK            0x00000100
 372                                                /**< Event Log Enable */
 373#define XAPM_CR_RDLATENCY_END_MASK              0x00000080
 374                                                /**< Write Latency
 375                                                        End point */
 376#define XAPM_CR_RDLATENCY_START_MASK            0x00000040
 377                                                /**< Read Latency
 378                                                        Start point */
 379#define XAPM_CR_WRLATENCY_END_MASK              0x00000020
 380                                                /**< Write Latency
 381                                                        End point */
 382#define XAPM_CR_WRLATENCY_START_MASK            0x00000010
 383                                                /**< Write Latency
 384                                                        Start point */
 385#define XAPM_CR_IDFILTER_ENABLE_MASK            0x00000008
 386                                                /**< ID Filter Enable */
 387#define XAPM_CR_MCNTR_EXTTRIGGER_MASK           0x00000004
 388                                                /**< Enable External
 389                                                   trigger to start
 390                                                   Metric Counters  */
 391#define XAPM_CR_MCNTR_RESET_MASK                0x00000002
 392                                                /**< Metrics Counter
 393                                                   Reset */
 394#define XAPM_CR_MCNTR_ENABLE_MASK               0x00000001
 395                                                /**< Metrics Counter
 396                                                        Enable */
 397
 398#define XAPM_ID_RID_MASK                        0xFFFF0000 /**< Read ID */
 399
 400#define XAPM_ID_WID_MASK                        0x0000FFFF /**< Write ID */
 401
 402#define XAPM_MASKID_RID_MASK                    0xFFFF0000 /**< Read ID Mask */
 403
 404#define XAPM_MASKID_WID_MASK                    0x0000FFFF /**< Write ID Mask*/
 405
 406
 407#define XAPM_MAX_COUNTERS               10 /**< Maximum number of Counters */
 408#define XAPM_MAX_COUNTERS_PROFILE       48 /**< Maximum number of Counters in
 409                                                profile mode */
 410
 411#define XAPM_METRIC_COUNTER_0   0 /**< Metric Counter 0 Register Index */
 412#define XAPM_METRIC_COUNTER_1   1 /**< Metric Counter 1 Register Index */
 413#define XAPM_METRIC_COUNTER_2   2 /**< Metric Counter 2 Register Index */
 414#define XAPM_METRIC_COUNTER_3   3 /**< Metric Counter 3 Register Index */
 415#define XAPM_METRIC_COUNTER_4   4 /**< Metric Counter 4 Register Index */
 416#define XAPM_METRIC_COUNTER_5   5 /**< Metric Counter 5 Register Index */
 417#define XAPM_METRIC_COUNTER_6   6 /**< Metric Counter 6 Register Index */
 418#define XAPM_METRIC_COUNTER_7   7 /**< Metric Counter 7 Register Index */
 419#define XAPM_METRIC_COUNTER_8   8 /**< Metric Counter 8 Register Index */
 420#define XAPM_METRIC_COUNTER_9   9 /**< Metric Counter 9 Register Index */
 421
 422#define XAPM_INCREMENTER_0      0 /**< Metric Counter 0 Register Index */
 423#define XAPM_INCREMENTER_1      1 /**< Metric Counter 0 Register Index */
 424#define XAPM_INCREMENTER_2      2 /**< Metric Counter 0 Register Index */
 425#define XAPM_INCREMENTER_3      3 /**< Metric Counter 0 Register Index */
 426#define XAPM_INCREMENTER_4      4 /**< Metric Counter 0 Register Index */
 427#define XAPM_INCREMENTER_5      5 /**< Metric Counter 0 Register Index */
 428#define XAPM_INCREMENTER_6      6 /**< Metric Counter 0 Register Index */
 429#define XAPM_INCREMENTER_7      7 /**< Metric Counter 0 Register Index */
 430#define XAPM_INCREMENTER_8      8 /**< Metric Counter 0 Register Index */
 431#define XAPM_INCREMENTER_9      9 /**< Metric Counter 0 Register Index */
 432
 433#define XAPM_METRIC_SET_0       0 /**< Write Transaction Count */
 434#define XAPM_METRIC_SET_1       1 /**< Read Transaction Count */
 435#define XAPM_METRIC_SET_2       2 /**< Write Byte Count */
 436#define XAPM_METRIC_SET_3       3 /**< Read Byte Count */
 437#define XAPM_METRIC_SET_4       4 /**< Write Beat Count */
 438#define XAPM_METRIC_SET_5       5 /**< Total Read Latency */
 439#define XAPM_METRIC_SET_6       6 /**< Total Write Latency */
 440#define XAPM_METRIC_SET_7       7 /**< Slv_Wr_Idle_Cnt */
 441#define XAPM_METRIC_SET_8       8 /**< Mst_Rd_Idle_Cnt */
 442#define XAPM_METRIC_SET_9       9 /**< Num_BValids */
 443#define XAPM_METRIC_SET_10      10 /**< Num_WLasts */
 444#define XAPM_METRIC_SET_11      11 /**< Num_RLasts */
 445#define XAPM_METRIC_SET_12      12 /**< Minimum Write Latency */
 446#define XAPM_METRIC_SET_13      13 /**< Maximum Write Latency */
 447#define XAPM_METRIC_SET_14      14 /**< Minimum Read Latency */
 448#define XAPM_METRIC_SET_15      15 /**< Maximum Read Latency */
 449#define XAPM_METRIC_SET_16      16 /**< Transfer Cycle Count */
 450#define XAPM_METRIC_SET_17      17 /**< Packet Count */
 451#define XAPM_METRIC_SET_18      18 /**< Data Byte Count */
 452#define XAPM_METRIC_SET_19      19 /**< Position Byte Count */
 453#define XAPM_METRIC_SET_20      20 /**< Null Byte Count */
 454#define XAPM_METRIC_SET_21      21 /**< Slv_Idle_Cnt */
 455#define XAPM_METRIC_SET_22      22 /**< Mst_Idle_Cnt */
 456#define XAPM_METRIC_SET_30      30 /**< External event count */
 457
 458#define XAPM_MAX_AGENTS         8 /**< Maximum number of Agents */
 459
 460#define XAPM_FLAG_WRADDR        0x00000001 /**< Write Address flag */
 461#define XAPM_FLAG_FIRSTWR       0x00000002 /**< First Write flag */
 462#define XAPM_FLAG_LASTWR        0x00000004 /**< Last Write flag */
 463#define XAPM_FLAG_RESPONSE      0x00000008 /**< Response flag */
 464#define XAPM_FLAG_RDADDR        0x00000010 /**< Read Address flag */
 465#define XAPM_FLAG_FIRSTRD       0x00000020 /**< First Read flag */
 466#define XAPM_FLAG_LASTRD        0x00000040 /**< Last Read flag */
 467#define XAPM_FLAG_SWDATA        0x00010000 /**< Software-written Data flag */
 468#define XAPM_FLAG_EVENT         0x00020000 /**< Last Read flag */
 469#define XAPM_FLAG_EVNTSTOP      0x00040000 /**< Last Read flag */
 470#define XAPM_FLAG_EVNTSTART     0x00080000 /**< Last Read flag */
 471#define XAPM_FLAG_GCCOVF        0x00100000 /**< Global Clock Counter Overflow
 472                                             *  flag */
 473#define XAPM_FLAG_SCLAPSE       0x00200000 /**< Sample Counter Lapse flag */
 474#define XAPM_FLAG_MC0           0x00400000 /**< Metric Counter 0 flag */
 475#define XAPM_FLAG_MC1           0x00800000 /**< Metric Counter 1 flag */
 476#define XAPM_FLAG_MC2           0x01000000 /**< Metric Counter 2 flag */
 477#define XAPM_FLAG_MC3           0x02000000 /**< Metric Counter 3 flag */
 478#define XAPM_FLAG_MC4           0x04000000 /**< Metric Counter 4 flag */
 479#define XAPM_FLAG_MC5           0x08000000 /**< Metric Counter 5 flag */
 480#define XAPM_FLAG_MC6           0x10000000 /**< Metric Counter 6 flag */
 481#define XAPM_FLAG_MC7           0x20000000 /**< Metric Counter 7 flag */
 482#define XAPM_FLAG_MC8           0x40000000 /**< Metric Counter 8 flag */
 483#define XAPM_FLAG_MC9           0x80000000 /**< Metric Counter 9 flag */
 484
 485#define XAPM_LATENCY_ADDR_ISSUE         0 /**< Address Issue as start
 486                                        point for Latency calculation*/
 487#define XAPM_LATENCY_ADDR_ACCEPT        1 /**< Address Acceptance as start
 488                                        point for Latency calculation*/
 489#define XAPM_LATENCY_LASTRD             0 /**< Last Read as end point for
 490                                        Latency calculation */
 491#define XAPM_LATENCY_LASTWR             0 /**< Last Write as end point for
 492                                        Latency calculation */
 493#define XAPM_LATENCY_FIRSTRD            1 /**< First Read as end point for
 494                                        Latency calculation */
 495#define XAPM_LATENCY_FIRSTWR            1 /**< First Write as end point for
 496                                        Latency calculation */
 497
 498#define XAPM_MODE_TRACE                 2 /**< APM in Trace mode */
 499
 500#define XAPM_MODE_PROFILE               1 /**< APM in Profile mode */
 501
 502#define XAPM_MODE_ADVANCED              0 /**< APM in Advanced mode */
 503
 504typedef unsigned char u8;
 505typedef uint16_t u16;
 506typedef uint32_t u32;
 507typedef unsigned long ulong;
 508
 509ulong baseaddr;
 510
 511struct xapm_param {
 512        u32     mode;
 513        u32     maxslots;
 514        u32     eventcnt;
 515        u32     eventlog;
 516        u32     sampledcnt;
 517        u32     numcounters;
 518        u32     metricwidth;
 519        u32     sampledwidth;
 520        u32     globalcntwidth;
 521        u32     scalefactor;
 522        u32     isr;
 523        bool    is_32bit_filter;
 524};
 525
 526static struct xapm_param *params;
 527
 528/*****************************************************************************/
 529/**
 530*
 531* Read a register of the AXI Performance Monitor device. This macro provides
 532* register access to all registers using the register offsets defined above.
 533*
 534* @param        baseaddr contains the base address of the device.
 535* @param        regoffset is the offset of the register to read.
 536*
 537* @return       The contents of the register.
 538*
 539* @note         C-style Signature:
 540*               u32 readreg(u32 baseaddr, u32 regoffset);
 541*
 542******************************************************************************/
 543#define readreg(baseaddr, regoffset) \
 544                        (*(u32 *)(baseaddr + regoffset))
 545
 546/*****************************************************************************/
 547/**
 548*
 549* Write a register of the AXI Performance Monitor device. This macro provides
 550* register access to all registers using the register offsets defined above.
 551*
 552* @param        baseaddr contains the base address of the device.
 553* @param        regoffset is the offset of the register to write.
 554* @param        data is the value to write to the register.
 555*
 556* @return       None.
 557*
 558* @note         C-style Signature:
 559*               void writereg(u32 baseaddr,
 560*                                       u32 regoffset,u32 Data)
 561*
 562******************************************************************************/
 563#define writereg(baseaddr, regoffset, data) \
 564                                (*(u32 *)(baseaddr + regoffset) = data)
 565
 566/****************************************************************************/
 567/**
 568*
 569* This routine enables the Global Interrupt.
 570*
 571* @note         C-Style signature:
 572*               void intrglobalenable()
 573*
 574*****************************************************************************/
 575#define intrglobalenable()                      \
 576                writereg(baseaddr, XAPM_GIE_OFFSET, 1)
 577
 578
 579/****************************************************************************/
 580/**
 581*
 582* This routine disables the Global Interrupt.
 583*
 584* @note         C-Style signature:
 585*               void intrglobaldisable(void)
 586*
 587*****************************************************************************/
 588#define intrglobaldisable()                             \
 589                writereg(baseaddr, XAPM_GIE_OFFSET, 0)
 590
 591/****************************************************************************/
 592/**
 593*
 594* This routine enables interrupt(s). Use the XAPM_IXR_* constants defined in
 595* xaxipmon_hw.h to create the bit-mask to enable interrupts.
 596*
 597* @param        mask is the mask to enable. Bit positions of 1 will be enabled.
 598*               Bit positions of 0 will keep the previous setting. This mask is
 599*               formed by OR'ing XAPM_IXR__* bits defined in xaxipmon_hw.h.
 600*
 601* @return       None.
 602*
 603* @note         C-Style signature:
 604*               void intrenable(u32 mask)
 605*
 606*****************************************************************************/
 607#define intrenable(mask)                                     \
 608        writereg(baseaddr, XAPM_IE_OFFSET, readreg(baseaddr, \
 609                        XAPM_IE_OFFSET) | mask);
 610
 611
 612/****************************************************************************/
 613/**
 614*
 615* This routine disable interrupt(s). Use the XAPM_IXR_* constants defined in
 616* xaxipmon_hw.h to create the bit-mask to disable interrupts.
 617*
 618* @param        mask is the mask to disable. Bit positions of 1 will be
 619*               disabled. Bit positions of 0 will keep the previous setting.
 620*               This mask is formed by OR'ing XAPM_IXR_* bits defined in
 621*               xaxipmon_hw.h.
 622*
 623* @return       None.
 624*
 625* @note         C-Style signature:
 626*               void intrdisable(u32 mask)
 627*
 628*****************************************************************************/
 629#define intrdisable(mask)                                    \
 630        writereg(baseaddr, XAPM_IE_OFFSET, readreg(baseaddr, \
 631                                                XAPM_IE_OFFSET) | mask);
 632
 633/****************************************************************************/
 634/**
 635*
 636* This routine clears the specified interrupt(s).
 637*
 638* @param        mask is the mask to clear. Bit positions of 1 will be cleared.
 639*               This mask is formed by OR'ing XAPM_IXR_* bits defined in
 640*               xaxipmon_hw.h.
 641*
 642* @return       None.
 643*
 644* @note         C-Style signature:
 645*               void intrclear(u32 mask)
 646*
 647*****************************************************************************/
 648#define intrclear(mask)                              \
 649        writereg(baseaddr, XAPM_IS_OFFSET, readreg(baseaddr, \
 650                                XAPM_IS_OFFSET) | mask);
 651
 652/****************************************************************************/
 653/**
 654*
 655* This routine returns the Interrupt Status Register.
 656*
 657* @return       isr value updated by kernel driver
 658*
 659* @note         This macro returns isr value updated by kernel driver.
 660*               C-Style signature:
 661*               void intrgetstatus(void)
 662*
 663*****************************************************************************/
 664#define intrgetstatus()         (params->isr)
 665
 666/****************************************************************************/
 667/**
 668*
 669* This routine returns the Interrupt Status Register.
 670*
 671* @return       Interrupt Status Register contents
 672*
 673* @note         C-Style signature:
 674*               void intrhwgetstatus(void)
 675*
 676*****************************************************************************/
 677#define intrhwgetstatus()         (params->isr)
 678
 679/****************************************************************************/
 680/**
 681*
 682* This function enables the Global Clock Counter.
 683*
 684* @note         C-Style signature:
 685*               void enablegcc(void);
 686*
 687*****************************************************************************/
 688#define enablegcc() \
 689        writereg(baseaddr, XAPM_CTL_OFFSET, readreg(baseaddr, \
 690                        XAPM_CTL_OFFSET) | XAPM_CR_GCC_ENABLE_MASK);
 691
 692/****************************************************************************/
 693/**
 694*
 695* This function disbles the Global Clock Counter.
 696*
 697* @note         C-Style signature:
 698*               void disablegcc(void);
 699*
 700*****************************************************************************/
 701#define disablegcc() \
 702        writereg(baseaddr, XAPM_CTL_OFFSET, readreg(baseaddr, \
 703                        XAPM_CTL_OFFSET) & ~(XAPM_CR_GCC_ENABLE_MASK));
 704
 705/****************************************************************************/
 706/**
 707*
 708* This function enables the specified flag in flag Control Register.
 709*
 710* @param        flag is one of the XAPM_FLAG_* masks defined in xaxipmon.h
 711*
 712* @return       None
 713*
 714* @note         C-Style signature:
 715*               void enableflag(void);
 716*
 717*****************************************************************************/
 718#define enableflag(flag) \
 719        writereg(baseaddr, XAPM_FEC_OFFSET, \
 720                        readreg(baseaddr, XAPM_FEC_OFFSET) | flag);
 721
 722/****************************************************************************/
 723/**
 724*
 725* This function disables the specified flag in flag Control Register.
 726*
 727* @param        flag is one of the XAPM_FLAG_* masks defined in xaxipmon.h*
 728* @return       None
 729*
 730* @note         C-Style signature:
 731*               void disableflag(void);
 732*
 733*****************************************************************************/
 734#define disableflag(flag) \
 735        writereg(baseaddr, XAPM_FEC_OFFSET, \
 736                        readreg(baseaddr, XAPM_FEC_OFFSET) & ~(flag));
 737
 738/****************************************************************************/
 739/**
 740*
 741* This function loads the sample interval register value into the sample
 742* interval counter.
 743*
 744* @note         C-Style signature:
 745*               void loadsic(void);
 746*
 747*****************************************************************************/
 748#define loadsic() \
 749                writereg(baseaddr, XAPM_SICR_OFFSET, XAPM_SICR_LOAD_MASK)
 750
 751
 752/****************************************************************************/
 753/**
 754*
 755* This enables the down count of the sample interval counter.
 756*
 757* @note         C-Style signature:
 758*          void enablesic(void);
 759*
 760*****************************************************************************/
 761#define enablesic() \
 762        writereg(baseaddr, XAPM_SICR_OFFSET, XAPM_SICR_ENABLE_MASK)
 763
 764/****************************************************************************/
 765/**
 766*
 767* This disables the down count of the sample interval counter.
 768*
 769* @note         C-Style signature:
 770*           void disablesic(void);
 771*
 772*****************************************************************************/
 773#define disablesic() \
 774        writereg(baseaddr, XAPM_SICR_OFFSET, \
 775        readreg(baseaddr, XAPM_SICR_OFFSET) & ~(XAPM_SICR_ENABLE_MASK));
 776
 777/****************************************************************************/
 778/**
 779*
 780* This enables Reset of Metric Counters when Sample Interval Counter lapses.
 781*
 782* @note         C-Style signature:
 783*               void enablemcreset(void);
 784*
 785*****************************************************************************/
 786#define enablemcreset() \
 787        writereg(baseaddr, XAPM_SICR_OFFSET, XAPM_SICR_MCNTR_RST_MASK);
 788
 789/****************************************************************************/
 790/**
 791*
 792* This disables the down count of the sample interval counter.
 793*
 794* @note         C-Style signature:
 795*               void disablemcreset(void);
 796*
 797*****************************************************************************/
 798#define disablemcreset() \
 799        writereg(baseaddr, XAPM_SICR_OFFSET, \
 800        readreg(baseaddr, XAPM_SICR_OFFSET) & ~(XAPM_SICR_MCNTR_RST_MASK));
 801
 802/****************************************************************************/
 803/**
 804*
 805* This function enables the ID Filter Masking.
 806*
 807* @note         C-Style signature:
 808*               void enableidfilter(void);
 809*
 810*****************************************************************************/
 811#define enableidfilter()                        \
 812        writereg(baseaddr, XAPM_CTL_OFFSET, readreg(baseaddr, \
 813                        XAPM_CTL_OFFSET) | XAPM_CR_IDFILTER_ENABLE_MASK);
 814
 815/****************************************************************************/
 816/**
 817*
 818* This function disbles the ID Filter masking.
 819*
 820* @note         C-Style signature:
 821*               void disableidfilter(void);
 822*
 823*****************************************************************************/
 824#define disableidfilter() \
 825        writereg(baseaddr, XAPM_CTL_OFFSET, readreg(baseaddr, \
 826                        XAPM_CTL_OFFSET) & ~(XAPM_CR_IDFILTER_ENABLE_MASK));
 827
 828/****************************************************************************/
 829/**
 830*
 831* This function samples Metric Counters to Sampled Metric Counters by
 832* reading Sample Register and also returns interval. i.e. the number of
 833* clocks in between previous read to the current read of sample register.
 834*
 835* @return       Interval. i.e. the number of clocks in between previous
 836*               read to the current read of sample register.
 837*
 838* @note         C-Style signature:
 839*               u32 samplemetrics(void);
 840*
 841*****************************************************************************/
 842#define samplemetrics()         readreg(baseaddr, XAPM_SR_OFFSET);
 843
 844
 845/************************** Function Prototypes *****************************/
 846
 847int resetmetriccounter(void);
 848
 849void resetglobalclkcounter(void);
 850
 851int resetfifo(void);
 852
 853void setincrementerrange(u8 incrementer, u16 rangehigh, u16 rangelow);
 854
 855void getincrementerrange(u8 incrementer, u16 *rangehigh, u16 *rangelow);
 856
 857void setsampleinterval(u32 sampleinterval);
 858
 859void getsampleinterval(u32 *sampleinterval);
 860
 861int setmetrics(u8 slot, u8 metrics, u8 counter);
 862
 863int getmetrics(u8 counter, u8 *metrics, u8 *slot);
 864void getglobalclkcounter(u32 *cnthigh, u32 *cntlow);
 865
 866u32 getmetriccounter(u32 counter);
 867
 868u32 getsampledmetriccounter(u32 counter);
 869
 870u32 getincrementer(u32 incrementer);
 871
 872u32 getsampledincrementer(u32 incrementer);
 873
 874void setswdatareg(u32 swdata);
 875
 876u32 getswdatareg(void);
 877
 878int starteventlog(u32 flagenables);
 879
 880int stopeventlog(void);
 881
 882int startcounters(u32 sampleinterval);
 883
 884int stopcounters(void);
 885
 886void enablemetricscounter(void);
 887
 888void disablemetricscounter(void);
 889
 890void setlogenableranges(u32 counter, u16 rangehigh, u16 rangelow);
 891
 892void getlogenableranges(u32 counter, u16 *rangehigh, u16 *rangelow);
 893
 894void enableeventlog(void);
 895
 896void enablemctrigger(void);
 897
 898void disablemctrigger(void);
 899
 900void enableeventlogtrigger(void);
 901
 902void disableeventlogtrigger(void);
 903
 904const char *getmetricname(u8 metrics);
 905
 906void setwriteid(u32 writeid);
 907
 908void setreadid(u32 readid);
 909
 910u32 getwriteid(void);
 911
 912u32 getreadid(void);
 913
 914void setwrlatencystart(u8 param);
 915
 916void setwrlatencyend(u8 param);
 917
 918void setrdlatencystart(u8 param);
 919
 920void setrdlatencyend(u8 param);
 921
 922u8 getwrlatencystart(void);
 923
 924u8 getwrlatencyend(void);
 925
 926u8 getrdlatencystart(void);
 927
 928u8 getrdlatencyend(void);
 929
 930void setwriteidmask(u32 wrmask);
 931
 932void setreadidmask(u32 rdmask);
 933
 934u32 getwriteidmask(void);
 935
 936u32 getreadidmask(void);
 937
 938
 939#ifdef __cplusplus
 940}
 941#endif
 942
 943#endif  /* End of protection macro. */
 944