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19#ifndef __HDA_TPLG_INTERFACE_H__
20#define __HDA_TPLG_INTERFACE_H__
21
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25
26#define SKL_CONTROL_TYPE_BYTE_TLV 0x100
27
28#define HDA_SST_CFG_MAX 900
29#define MAX_IN_QUEUE 8
30#define MAX_OUT_QUEUE 8
31
32#define SKL_UUID_STR_SZ 40
33
34
35enum skl_event_types {
36 SKL_EVENT_NONE = 0,
37 SKL_MIXER_EVENT,
38 SKL_MUX_EVENT,
39 SKL_VMIXER_EVENT,
40 SKL_PGA_EVENT
41};
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59
60enum skl_ch_cfg {
61 SKL_CH_CFG_MONO = 0,
62 SKL_CH_CFG_STEREO = 1,
63 SKL_CH_CFG_2_1 = 2,
64 SKL_CH_CFG_3_0 = 3,
65 SKL_CH_CFG_3_1 = 4,
66 SKL_CH_CFG_QUATRO = 5,
67 SKL_CH_CFG_4_0 = 6,
68 SKL_CH_CFG_5_0 = 7,
69 SKL_CH_CFG_5_1 = 8,
70 SKL_CH_CFG_DUAL_MONO = 9,
71 SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10,
72 SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11,
73 SKL_CH_CFG_4_CHANNEL = 12,
74 SKL_CH_CFG_INVALID
75};
76
77enum skl_module_type {
78 SKL_MODULE_TYPE_MIXER = 0,
79 SKL_MODULE_TYPE_COPIER,
80 SKL_MODULE_TYPE_UPDWMIX,
81 SKL_MODULE_TYPE_SRCINT,
82 SKL_MODULE_TYPE_ALGO,
83 SKL_MODULE_TYPE_BASE_OUTFMT
84};
85
86enum skl_core_affinity {
87 SKL_AFFINITY_CORE_0 = 0,
88 SKL_AFFINITY_CORE_1,
89 SKL_AFFINITY_CORE_MAX
90};
91
92enum skl_pipe_conn_type {
93 SKL_PIPE_CONN_TYPE_NONE = 0,
94 SKL_PIPE_CONN_TYPE_FE,
95 SKL_PIPE_CONN_TYPE_BE
96};
97
98enum skl_hw_conn_type {
99 SKL_CONN_NONE = 0,
100 SKL_CONN_SOURCE = 1,
101 SKL_CONN_SINK = 2
102};
103
104enum skl_dev_type {
105 SKL_DEVICE_BT = 0x0,
106 SKL_DEVICE_DMIC = 0x1,
107 SKL_DEVICE_I2S = 0x2,
108 SKL_DEVICE_SLIMBUS = 0x3,
109 SKL_DEVICE_HDALINK = 0x4,
110 SKL_DEVICE_HDAHOST = 0x5,
111 SKL_DEVICE_NONE
112};
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119
120enum skl_interleaving {
121 SKL_INTERLEAVING_PER_CHANNEL = 0,
122 SKL_INTERLEAVING_PER_SAMPLE = 1,
123};
124
125enum skl_sample_type {
126 SKL_SAMPLE_TYPE_INT_MSB = 0,
127 SKL_SAMPLE_TYPE_INT_LSB = 1,
128 SKL_SAMPLE_TYPE_INT_SIGNED = 2,
129 SKL_SAMPLE_TYPE_INT_UNSIGNED = 3,
130 SKL_SAMPLE_TYPE_FLOAT = 4
131};
132
133enum module_pin_type {
134
135
136
137 SKL_PIN_TYPE_HOMOGENEOUS,
138
139
140
141 SKL_PIN_TYPE_HETEROGENEOUS,
142};
143
144enum skl_module_param_type {
145 SKL_PARAM_DEFAULT = 0,
146 SKL_PARAM_INIT,
147 SKL_PARAM_SET,
148 SKL_PARAM_BIND
149};
150
151struct skl_dfw_module_pin {
152 u16 module_id;
153 u16 instance_id;
154} __packed;
155
156struct skl_dfw_module_fmt {
157 u32 channels;
158 u32 freq;
159 u32 bit_depth;
160 u32 valid_bit_depth;
161 u32 ch_cfg;
162 u32 interleaving_style;
163 u32 sample_type;
164 u32 ch_map;
165} __packed;
166
167struct skl_dfw_module_caps {
168 u32 set_params:2;
169 u32 rsvd:30;
170 u32 param_id;
171 u32 caps_size;
172 u32 caps[HDA_SST_CFG_MAX];
173};
174
175struct skl_dfw_pipe {
176 u8 pipe_id;
177 u8 pipe_priority;
178 u16 conn_type:4;
179 u16 rsvd:4;
180 u16 memory_pages:8;
181} __packed;
182
183struct skl_dfw_module {
184 char uuid[SKL_UUID_STR_SZ];
185
186 u16 module_id;
187 u16 instance_id;
188 u32 max_mcps;
189 u32 mem_pages;
190 u32 obs;
191 u32 ibs;
192 u32 vbus_id;
193
194 u32 max_in_queue:8;
195 u32 max_out_queue:8;
196 u32 time_slot:8;
197 u32 core_id:4;
198 u32 rsvd1:4;
199
200 u32 module_type:8;
201 u32 conn_type:4;
202 u32 dev_type:4;
203 u32 hw_conn_type:4;
204 u32 rsvd2:12;
205
206 u32 params_fixup:8;
207 u32 converter:8;
208 u32 input_pin_type:1;
209 u32 output_pin_type:1;
210 u32 is_dynamic_in_pin:1;
211 u32 is_dynamic_out_pin:1;
212 u32 is_loadable:1;
213 u32 rsvd3:11;
214
215 struct skl_dfw_pipe pipe;
216 struct skl_dfw_module_fmt in_fmt[MAX_IN_QUEUE];
217 struct skl_dfw_module_fmt out_fmt[MAX_OUT_QUEUE];
218 struct skl_dfw_module_pin in_pin[MAX_IN_QUEUE];
219 struct skl_dfw_module_pin out_pin[MAX_OUT_QUEUE];
220 struct skl_dfw_module_caps caps;
221} __packed;
222
223struct skl_dfw_algo_data {
224 u32 set_params:2;
225 u32 rsvd:30;
226 u32 param_id;
227 u32 max;
228 char params[0];
229} __packed;
230
231#endif
232
