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11#ifndef __ASM_ARCH_MXC_COMMON_H__
12#define __ASM_ARCH_MXC_COMMON_H__
13
14#include <linux/reboot.h>
15
16struct irq_data;
17struct platform_device;
18struct pt_regs;
19struct clk;
20struct device_node;
21enum mxc_cpu_pwr_mode;
22struct of_device_id;
23
24void mx21_map_io(void);
25void mx27_map_io(void);
26void mx31_map_io(void);
27void mx35_map_io(void);
28void imx21_init_early(void);
29void imx27_init_early(void);
30void imx31_init_early(void);
31void imx35_init_early(void);
32void mxc_init_irq(void __iomem *);
33void mx21_init_irq(void);
34void mx27_init_irq(void);
35void mx31_init_irq(void);
36void mx35_init_irq(void);
37void imx21_soc_init(void);
38void imx27_soc_init(void);
39void imx31_soc_init(void);
40void imx35_soc_init(void);
41void epit_timer_init(void __iomem *base, int irq);
42int mx21_clocks_init(unsigned long lref, unsigned long fref);
43int mx27_clocks_init(unsigned long fref);
44int mx31_clocks_init(unsigned long fref);
45int mx35_clocks_init(void);
46int mx31_clocks_init_dt(void);
47struct platform_device *mxc_register_gpio(char *name, int id,
48 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
49void mxc_set_cpu_type(unsigned int type);
50void mxc_restart(enum reboot_mode, const char *);
51void mxc_arch_reset_init(void __iomem *);
52void imx1_reset_init(void __iomem *);
53void imx_set_aips(void __iomem *);
54void imx_aips_allow_unprivileged_access(const char *compat);
55int mxc_device_init(void);
56void imx_set_soc_revision(unsigned int rev);
57void imx_init_revision_from_anatop(void);
58struct device *imx_soc_device_init(void);
59void imx6_enable_rbc(bool enable);
60void imx_gpc_check_dt(void);
61void imx_gpc_set_arm_power_in_lpm(bool power_off);
62void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
63void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
64void imx25_pm_init(void);
65void imx27_pm_init(void);
66
67enum mxc_cpu_pwr_mode {
68 WAIT_CLOCKED,
69 WAIT_UNCLOCKED,
70 WAIT_UNCLOCKED_POWER_OFF,
71 STOP_POWER_ON,
72 STOP_POWER_OFF,
73};
74
75enum mx3_cpu_pwr_mode {
76 MX3_RUN,
77 MX3_WAIT,
78 MX3_DOZE,
79 MX3_SLEEP,
80};
81
82void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
83
84void imx_enable_cpu(int cpu, bool enable);
85void imx_set_cpu_jump(int cpu, void *jump_addr);
86u32 imx_get_cpu_arg(int cpu);
87void imx_set_cpu_arg(int cpu, u32 arg);
88#ifdef CONFIG_SMP
89void v7_secondary_startup(void);
90void imx_scu_map_io(void);
91void imx_smp_prepare(void);
92#else
93static inline void imx_scu_map_io(void) {}
94static inline void imx_smp_prepare(void) {}
95#endif
96void imx_src_init(void);
97void imx_gpc_pre_suspend(bool arm_power_off);
98void imx_gpc_post_resume(void);
99void imx_gpc_mask_all(void);
100void imx_gpc_restore_all(void);
101void imx_gpc_hwirq_mask(unsigned int hwirq);
102void imx_gpc_hwirq_unmask(unsigned int hwirq);
103void imx_anatop_init(void);
104void imx_anatop_pre_suspend(void);
105void imx_anatop_post_resume(void);
106int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
107void imx6_set_int_mem_clk_lpm(bool enable);
108void imx6sl_set_wait_clk(bool enter);
109int imx_mmdc_get_ddr_type(void);
110
111void imx_cpu_die(unsigned int cpu);
112int imx_cpu_kill(unsigned int cpu);
113
114#ifdef CONFIG_SUSPEND
115void v7_cpu_resume(void);
116void imx53_suspend(void __iomem *ocram_vbase);
117extern const u32 imx53_suspend_sz;
118void imx6_suspend(void __iomem *ocram_vbase);
119#else
120static inline void v7_cpu_resume(void) {}
121static inline void imx53_suspend(void __iomem *ocram_vbase) {}
122static const u32 imx53_suspend_sz;
123static inline void imx6_suspend(void __iomem *ocram_vbase) {}
124#endif
125
126void imx6_pm_ccm_init(const char *ccm_compat);
127void imx6q_pm_init(void);
128void imx6dl_pm_init(void);
129void imx6sl_pm_init(void);
130void imx6sx_pm_init(void);
131void imx6ul_pm_init(void);
132
133#ifdef CONFIG_PM
134void imx51_pm_init(void);
135void imx53_pm_init(void);
136#else
137static inline void imx51_pm_init(void) {}
138static inline void imx53_pm_init(void) {}
139#endif
140
141#ifdef CONFIG_NEON
142int mx51_neon_fixup(void);
143#else
144static inline int mx51_neon_fixup(void) { return 0; }
145#endif
146
147#ifdef CONFIG_CACHE_L2X0
148void imx_init_l2cache(void);
149#else
150static inline void imx_init_l2cache(void) {}
151#endif
152
153extern const struct smp_operations imx_smp_ops;
154extern const struct smp_operations ls1021a_smp_ops;
155
156#endif
157