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21#include <linux/mm.h>
22#include <linux/init.h>
23#include <linux/pinctrl/machine.h>
24#include <asm/pgtable.h>
25#include <asm/mach/map.h>
26
27#include "common.h"
28#include "devices/devices-common.h"
29#include "hardware.h"
30#include "iomux-v1.h"
31
32
33static struct map_desc imx27_io_desc[] __initdata = {
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40
41
42 imx_map_entry(MX27, AIPI, MT_DEVICE),
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46
47
48 imx_map_entry(MX27, SAHB1, MT_DEVICE),
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52
53 imx_map_entry(MX27, X_MEMC, MT_DEVICE),
54};
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58
59
60
61void __init mx27_map_io(void)
62{
63 iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc));
64}
65
66void __init imx27_init_early(void)
67{
68 mxc_set_cpu_type(MXC_CPU_MX27);
69 imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR),
70 MX27_NUM_GPIO_PORT);
71}
72
73void __init mx27_init_irq(void)
74{
75 mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
76}
77
78static const struct resource imx27_audmux_res[] __initconst = {
79 DEFINE_RES_MEM(MX27_AUDMUX_BASE_ADDR, SZ_4K),
80};
81
82void __init imx27_soc_init(void)
83{
84 mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
85 mxc_device_init();
86
87
88 mxc_register_gpio("imx21-gpio", 0, MX27_GPIO1_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
89 mxc_register_gpio("imx21-gpio", 1, MX27_GPIO2_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
90 mxc_register_gpio("imx21-gpio", 2, MX27_GPIO3_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
91 mxc_register_gpio("imx21-gpio", 3, MX27_GPIO4_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
92 mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
93 mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
94
95 pinctrl_provide_dummies();
96 imx_add_imx_dma("imx27-dma", MX27_DMA_BASE_ADDR,
97 MX27_INT_DMACH0, 0);
98
99 platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res,
100 ARRAY_SIZE(imx27_audmux_res));
101
102 imx27_pm_init();
103}
104