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12#include <linux/init.h>
13#include <linux/device.h>
14#include <linux/errno.h>
15#include <linux/io.h>
16#include <linux/irqchip.h>
17#include <linux/irqdomain.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20
21#include <asm/mach/irq.h>
22#include <asm/exception.h>
23
24#include "common.h"
25#include "hardware.h"
26#include "irq-common.h"
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32
33
34#define TZIC_INTCNTL 0x0000
35#define TZIC_INTTYPE 0x0004
36#define TZIC_IMPID 0x0008
37#define TZIC_PRIOMASK 0x000C
38#define TZIC_SYNCCTRL 0x0010
39#define TZIC_DSMINT 0x0014
40#define TZIC_INTSEC0(i) (0x0080 + ((i) << 2))
41#define TZIC_ENSET0(i) (0x0100 + ((i) << 2))
42#define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2))
43#define TZIC_SRCSET0 0x0200
44#define TZIC_SRCCLAR0 0x0280
45#define TZIC_PRIORITY0 0x0400
46#define TZIC_PND0 0x0D00
47#define TZIC_HIPND(i) (0x0D80+ ((i) << 2))
48#define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2))
49#define TZIC_SWINT 0x0F00
50#define TZIC_ID0 0x0FD0
51
52static void __iomem *tzic_base;
53static struct irq_domain *domain;
54
55#define TZIC_NUM_IRQS 128
56
57#ifdef CONFIG_FIQ
58static int tzic_set_irq_fiq(unsigned int hwirq, unsigned int type)
59{
60 unsigned int index, mask, value;
61
62 index = hwirq >> 5;
63 if (unlikely(index >= 4))
64 return -EINVAL;
65 mask = 1U << (hwirq & 0x1F);
66
67 value = imx_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
68 if (type)
69 value &= ~mask;
70 imx_writel(value, tzic_base + TZIC_INTSEC0(index));
71
72 return 0;
73}
74#else
75#define tzic_set_irq_fiq NULL
76#endif
77
78#ifdef CONFIG_PM
79static void tzic_irq_suspend(struct irq_data *d)
80{
81 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
82 int idx = d->hwirq >> 5;
83
84 imx_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
85}
86
87static void tzic_irq_resume(struct irq_data *d)
88{
89 int idx = d->hwirq >> 5;
90
91 imx_writel(imx_readl(tzic_base + TZIC_ENSET0(idx)),
92 tzic_base + TZIC_WAKEUP0(idx));
93}
94
95#else
96#define tzic_irq_suspend NULL
97#define tzic_irq_resume NULL
98#endif
99
100static struct mxc_extra_irq tzic_extra_irq = {
101#ifdef CONFIG_FIQ
102 .set_irq_fiq = tzic_set_irq_fiq,
103#endif
104};
105
106static __init void tzic_init_gc(int idx, unsigned int irq_start)
107{
108 struct irq_chip_generic *gc;
109 struct irq_chip_type *ct;
110
111 gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
112 handle_level_irq);
113 gc->private = &tzic_extra_irq;
114 gc->wake_enabled = IRQ_MSK(32);
115
116 ct = gc->chip_types;
117 ct->chip.irq_mask = irq_gc_mask_disable_reg;
118 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
119 ct->chip.irq_set_wake = irq_gc_set_wake;
120 ct->chip.irq_suspend = tzic_irq_suspend;
121 ct->chip.irq_resume = tzic_irq_resume;
122 ct->regs.disable = TZIC_ENCLEAR0(idx);
123 ct->regs.enable = TZIC_ENSET0(idx);
124
125 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
126}
127
128static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
129{
130 u32 stat;
131 int i, irqofs, handled;
132
133 do {
134 handled = 0;
135
136 for (i = 0; i < 4; i++) {
137 stat = imx_readl(tzic_base + TZIC_HIPND(i)) &
138 imx_readl(tzic_base + TZIC_INTSEC0(i));
139
140 while (stat) {
141 handled = 1;
142 irqofs = fls(stat) - 1;
143 handle_domain_irq(domain, irqofs + i * 32, regs);
144 stat &= ~(1 << irqofs);
145 }
146 }
147 } while (handled);
148}
149
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154
155static int __init tzic_init_dt(struct device_node *np, struct device_node *p)
156{
157 int irq_base;
158 int i;
159
160 tzic_base = of_iomap(np, 0);
161 WARN_ON(!tzic_base);
162
163
164
165
166 i = imx_readl(tzic_base + TZIC_INTCNTL);
167
168 imx_writel(0x80010001, tzic_base + TZIC_INTCNTL);
169 imx_writel(0x1f, tzic_base + TZIC_PRIOMASK);
170 imx_writel(0x02, tzic_base + TZIC_SYNCCTRL);
171
172 for (i = 0; i < 4; i++)
173 imx_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
174
175
176 for (i = 0; i < 4; i++)
177 imx_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
178
179
180
181 irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());
182 WARN_ON(irq_base < 0);
183
184 domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,
185 &irq_domain_simple_ops, NULL);
186 WARN_ON(!domain);
187
188 for (i = 0; i < 4; i++, irq_base += 32)
189 tzic_init_gc(i, irq_base);
190
191 set_handle_irq(tzic_handle_irq);
192
193#ifdef CONFIG_FIQ
194
195 init_FIQ(FIQ_START);
196#endif
197
198 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
199
200 return 0;
201}
202IRQCHIP_DECLARE(tzic, "fsl,tzic", tzic_init_dt);
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212
213int tzic_enable_wake(void)
214{
215 unsigned int i;
216
217 imx_writel(1, tzic_base + TZIC_DSMINT);
218 if (unlikely(imx_readl(tzic_base + TZIC_DSMINT) == 0))
219 return -EAGAIN;
220
221 for (i = 0; i < 4; i++)
222 imx_writel(imx_readl(tzic_base + TZIC_ENSET0(i)),
223 tzic_base + TZIC_WAKEUP0(i));
224
225 return 0;
226}
227