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25#include <linux/sched.h>
26#include <linux/cpuidle.h>
27#include <linux/export.h>
28#include <linux/cpu_pm.h>
29#include <asm/cpuidle.h>
30
31#include "powerdomain.h"
32#include "clockdomain.h"
33
34#include "pm.h"
35#include "control.h"
36#include "common.h"
37#include "soc.h"
38
39
40struct omap3_idle_statedata {
41 u8 mpu_state;
42 u8 core_state;
43 u8 per_min_state;
44 u8 flags;
45};
46
47static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
48
49
50
51
52
53
54
55
56
57
58#define OMAP_CPUIDLE_CX_NO_CLKDM_IDLE BIT(0)
59
60
61
62
63
64static struct omap3_idle_statedata omap3_idle_data[] = {
65 {
66 .mpu_state = PWRDM_POWER_ON,
67 .core_state = PWRDM_POWER_ON,
68
69 .per_min_state = PWRDM_POWER_ON,
70 .flags = OMAP_CPUIDLE_CX_NO_CLKDM_IDLE,
71 },
72 {
73 .mpu_state = PWRDM_POWER_ON,
74 .core_state = PWRDM_POWER_ON,
75 .per_min_state = PWRDM_POWER_RET,
76 },
77 {
78 .mpu_state = PWRDM_POWER_RET,
79 .core_state = PWRDM_POWER_ON,
80 .per_min_state = PWRDM_POWER_RET,
81 },
82 {
83 .mpu_state = PWRDM_POWER_OFF,
84 .core_state = PWRDM_POWER_ON,
85 .per_min_state = PWRDM_POWER_RET,
86 },
87 {
88 .mpu_state = PWRDM_POWER_RET,
89 .core_state = PWRDM_POWER_RET,
90 .per_min_state = PWRDM_POWER_OFF,
91 },
92 {
93 .mpu_state = PWRDM_POWER_OFF,
94 .core_state = PWRDM_POWER_RET,
95 .per_min_state = PWRDM_POWER_OFF,
96 },
97 {
98 .mpu_state = PWRDM_POWER_OFF,
99 .core_state = PWRDM_POWER_OFF,
100 .per_min_state = PWRDM_POWER_OFF,
101 },
102};
103
104
105
106
107
108
109
110static int omap3_enter_idle(struct cpuidle_device *dev,
111 struct cpuidle_driver *drv,
112 int index)
113{
114 struct omap3_idle_statedata *cx = &omap3_idle_data[index];
115
116 if (omap_irq_pending() || need_resched())
117 goto return_sleep_time;
118
119
120 if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE) {
121 clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]);
122 } else {
123 pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
124 pwrdm_set_next_pwrst(core_pd, cx->core_state);
125 }
126
127
128
129
130
131 if (cx->mpu_state == PWRDM_POWER_OFF)
132 cpu_pm_enter();
133
134
135 omap_sram_idle();
136
137
138
139
140
141 if (cx->mpu_state == PWRDM_POWER_OFF &&
142 pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
143 cpu_pm_exit();
144
145
146 if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE)
147 clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
148
149return_sleep_time:
150
151 return index;
152}
153
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165
166
167static int next_valid_state(struct cpuidle_device *dev,
168 struct cpuidle_driver *drv, int index)
169{
170 struct omap3_idle_statedata *cx = &omap3_idle_data[index];
171 u32 mpu_deepest_state = PWRDM_POWER_RET;
172 u32 core_deepest_state = PWRDM_POWER_RET;
173 int idx;
174 int next_index = 0;
175
176 if (enable_off_mode) {
177 mpu_deepest_state = PWRDM_POWER_OFF;
178
179
180
181
182
183 if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
184 core_deepest_state = PWRDM_POWER_OFF;
185 }
186
187
188 if ((cx->mpu_state >= mpu_deepest_state) &&
189 (cx->core_state >= core_deepest_state))
190 return index;
191
192
193
194
195
196 for (idx = index - 1; idx >= 0; idx--) {
197 cx = &omap3_idle_data[idx];
198 if ((cx->mpu_state >= mpu_deepest_state) &&
199 (cx->core_state >= core_deepest_state)) {
200 next_index = idx;
201 break;
202 }
203 }
204
205 return next_index;
206}
207
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215
216
217static int omap3_enter_idle_bm(struct cpuidle_device *dev,
218 struct cpuidle_driver *drv,
219 int index)
220{
221 int new_state_idx, ret;
222 u8 per_next_state, per_saved_state;
223 struct omap3_idle_statedata *cx;
224
225
226
227
228
229 if (pwrdm_read_pwrst(cam_pd) == PWRDM_POWER_ON)
230 new_state_idx = drv->safe_state_index;
231 else
232 new_state_idx = next_valid_state(dev, drv, index);
233
234
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239
240
241
242
243 cx = &omap3_idle_data[new_state_idx];
244
245 per_next_state = pwrdm_read_next_pwrst(per_pd);
246 per_saved_state = per_next_state;
247 if (per_next_state < cx->per_min_state) {
248 per_next_state = cx->per_min_state;
249 pwrdm_set_next_pwrst(per_pd, per_next_state);
250 }
251
252 ret = omap3_enter_idle(dev, drv, new_state_idx);
253
254
255 if (per_next_state != per_saved_state)
256 pwrdm_set_next_pwrst(per_pd, per_saved_state);
257
258 return ret;
259}
260
261static struct cpuidle_driver omap3_idle_driver = {
262 .name = "omap3_idle",
263 .owner = THIS_MODULE,
264 .states = {
265 {
266 .enter = omap3_enter_idle_bm,
267 .exit_latency = 2 + 2,
268 .target_residency = 5,
269 .name = "C1",
270 .desc = "MPU ON + CORE ON",
271 },
272 {
273 .enter = omap3_enter_idle_bm,
274 .exit_latency = 10 + 10,
275 .target_residency = 30,
276 .name = "C2",
277 .desc = "MPU ON + CORE ON",
278 },
279 {
280 .enter = omap3_enter_idle_bm,
281 .exit_latency = 50 + 50,
282 .target_residency = 300,
283 .name = "C3",
284 .desc = "MPU RET + CORE ON",
285 },
286 {
287 .enter = omap3_enter_idle_bm,
288 .exit_latency = 1500 + 1800,
289 .target_residency = 4000,
290 .name = "C4",
291 .desc = "MPU OFF + CORE ON",
292 },
293 {
294 .enter = omap3_enter_idle_bm,
295 .exit_latency = 2500 + 7500,
296 .target_residency = 12000,
297 .name = "C5",
298 .desc = "MPU RET + CORE RET",
299 },
300 {
301 .enter = omap3_enter_idle_bm,
302 .exit_latency = 3000 + 8500,
303 .target_residency = 15000,
304 .name = "C6",
305 .desc = "MPU OFF + CORE RET",
306 },
307 {
308 .enter = omap3_enter_idle_bm,
309 .exit_latency = 10000 + 30000,
310 .target_residency = 30000,
311 .name = "C7",
312 .desc = "MPU OFF + CORE OFF",
313 },
314 },
315 .state_count = ARRAY_SIZE(omap3_idle_data),
316 .safe_state_index = 0,
317};
318
319
320
321
322
323
324static struct cpuidle_driver omap3430_idle_driver = {
325 .name = "omap3430_idle",
326 .owner = THIS_MODULE,
327 .states = {
328 {
329 .enter = omap3_enter_idle_bm,
330 .exit_latency = 110 + 162,
331 .target_residency = 5,
332 .name = "C1",
333 .desc = "MPU ON + CORE ON",
334 },
335 {
336 .enter = omap3_enter_idle_bm,
337 .exit_latency = 106 + 180,
338 .target_residency = 309,
339 .name = "C2",
340 .desc = "MPU ON + CORE ON",
341 },
342 {
343 .enter = omap3_enter_idle_bm,
344 .exit_latency = 107 + 410,
345 .target_residency = 46057,
346 .name = "C3",
347 .desc = "MPU RET + CORE ON",
348 },
349 {
350 .enter = omap3_enter_idle_bm,
351 .exit_latency = 121 + 3374,
352 .target_residency = 46057,
353 .name = "C4",
354 .desc = "MPU OFF + CORE ON",
355 },
356 {
357 .enter = omap3_enter_idle_bm,
358 .exit_latency = 855 + 1146,
359 .target_residency = 46057,
360 .name = "C5",
361 .desc = "MPU RET + CORE RET",
362 },
363 {
364 .enter = omap3_enter_idle_bm,
365 .exit_latency = 7580 + 4134,
366 .target_residency = 484329,
367 .name = "C6",
368 .desc = "MPU OFF + CORE RET",
369 },
370 {
371 .enter = omap3_enter_idle_bm,
372 .exit_latency = 7505 + 15274,
373 .target_residency = 484329,
374 .name = "C7",
375 .desc = "MPU OFF + CORE OFF",
376 },
377 },
378 .state_count = ARRAY_SIZE(omap3_idle_data),
379 .safe_state_index = 0,
380};
381
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384
385
386
387
388
389
390int __init omap3_idle_init(void)
391{
392 mpu_pd = pwrdm_lookup("mpu_pwrdm");
393 core_pd = pwrdm_lookup("core_pwrdm");
394 per_pd = pwrdm_lookup("per_pwrdm");
395 cam_pd = pwrdm_lookup("cam_pwrdm");
396
397 if (!mpu_pd || !core_pd || !per_pd || !cam_pd)
398 return -ENODEV;
399
400 if (cpu_is_omap3430())
401 return cpuidle_register(&omap3430_idle_driver, NULL);
402 else
403 return cpuidle_register(&omap3_idle_driver, NULL);
404}
405