LXR linux/arch/arm64/include/asm/perf

   1/*
   2 * Copyright (C) 2012 ARM Ltd.
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License version 2 as
   6 * published by the Free Software Foundation.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 *
  13 * You should have received a copy of the GNU General Public License
  14 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15 */
  16
  17#ifndef __ASM_PERF_EVENT_H
  18#define __ASM_PERF_EVENT_H
  19
  20#define ARMV8_PMU_MAX_COUNTERS  32
  21#define ARMV8_PMU_COUNTER_MASK  (ARMV8_PMU_MAX_COUNTERS - 1)
  22
  23/*
  24 * Per-CPU PMCR: config reg
  25 */
  26#define ARMV8_PMU_PMCR_E        (1 << 0) /* Enable all counters */
  27#define ARMV8_PMU_PMCR_P        (1 << 1) /* Reset all counters */
  28#define ARMV8_PMU_PMCR_C        (1 << 2) /* Cycle counter reset */
  29#define ARMV8_PMU_PMCR_D        (1 << 3) /* CCNT counts every 64th cpu cycle */
  30#define ARMV8_PMU_PMCR_X        (1 << 4) /* Export to ETM */
  31#define ARMV8_PMU_PMCR_DP       (1 << 5) /* Disable CCNT if non-invasive debug*/
  32#define ARMV8_PMU_PMCR_LC       (1 << 6) /* Overflow on 64 bit cycle counter */
  33#define ARMV8_PMU_PMCR_N_SHIFT  11       /* Number of counters supported */
  34#define ARMV8_PMU_PMCR_N_MASK   0x1f
  35#define ARMV8_PMU_PMCR_MASK     0x7f     /* Mask for writable bits */
  36
  37/*
  38 * PMOVSR: counters overflow flag status reg
  39 */
  40#define ARMV8_PMU_OVSR_MASK             0xffffffff      /* Mask for writable bits */
  41#define ARMV8_PMU_OVERFLOWED_MASK       ARMV8_PMU_OVSR_MASK
  42
  43/*
  44 * PMXEVTYPER: Event selection reg
  45 */
  46#define ARMV8_PMU_EVTYPE_MASK   0xc800ffff      /* Mask for writable bits */
  47#define ARMV8_PMU_EVTYPE_EVENT  0xffff          /* Mask for EVENT bits */
  48
  49/*
  50 * PMUv3 event types: required events
  51 */
  52#define ARMV8_PMUV3_PERFCTR_SW_INCR                             0x00
  53#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL                    0x03
  54#define ARMV8_PMUV3_PERFCTR_L1D_CACHE                           0x04
  55#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED                         0x10
  56#define ARMV8_PMUV3_PERFCTR_CPU_CYCLES                          0x11
  57#define ARMV8_PMUV3_PERFCTR_BR_PRED                             0x12
  58
  59/*
  60 * Event filters for PMUv3
  61 */
  62#define ARMV8_PMU_EXCLUDE_EL1   (1 << 31)
  63#define ARMV8_PMU_EXCLUDE_EL0   (1 << 30)
  64#define ARMV8_PMU_INCLUDE_EL2   (1 << 27)
  65
  66/*
  67 * PMUSERENR: user enable reg
  68 */
  69#define ARMV8_PMU_USERENR_MASK  0xf             /* Mask for writable bits */
  70#define ARMV8_PMU_USERENR_EN    (1 << 0) /* PMU regs can be accessed at EL0 */
  71#define ARMV8_PMU_USERENR_SW    (1 << 1) /* PMSWINC can be written at EL0 */
  72#define ARMV8_PMU_USERENR_CR    (1 << 2) /* Cycle counter can be read at EL0 */
  73#define ARMV8_PMU_USERENR_ER    (1 << 3) /* Event counter can be read at EL0 */
  74
  75#ifdef CONFIG_PERF_EVENTS
  76struct pt_regs;
  77extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
  78extern unsigned long perf_misc_flags(struct pt_regs *regs);
  79#define perf_misc_flags(regs)   perf_misc_flags(regs)
  80#endif
  81
  82#define perf_arch_fetch_caller_regs(regs, __ip) { \
  83        (regs)->pc = (__ip);    \
  84        (regs)->regs[29] = (unsigned long) __builtin_frame_address(0); \
  85        (regs)->sp = current_stack_pointer; \
  86        (regs)->pstate = PSR_MODE_EL1h; \
  87}
  88
  89#endif
  90