LXR linux/arch/blackfin/mach-bf518/include/mach/portmux.h

   1/*
   2 * Copyright 2008-2009 Analog Devices Inc.
   3 *
   4 * Licensed under the GPL-2 or later
   5 */
   6
   7#ifndef _MACH_PORTMUX_H_
   8#define _MACH_PORTMUX_H_
   9
  10#define MAX_RESOURCES   MAX_BLACKFIN_GPIOS
  11
  12/* EMAC MII/RMII Port Mux */
  13#define P_MII0_ETxD2    (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
  14#define P_MII0_ERxD2    (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
  15#define P_MII0_ETxD3    (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
  16#define P_MII0_ERxD3    (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
  17#define P_MII0_ERxCLK   (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
  18#define P_MII0_ERxDV    (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
  19#define P_MII0_COL      (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
  20
  21#define P_MII0_MDC      (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
  22#define P_MII0_MDIO     (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
  23#define P_MII0_ETxD0    (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
  24#define P_MII0_ERxD0    (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
  25#define P_MII0_ETxD1    (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
  26#define P_MII0_ERxD1    (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
  27#define P_MII0_ETxEN    (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
  28#define P_MII0_PHYINT   (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
  29#define P_MII0_CRS      (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
  30#define P_MII0_ERxER    (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
  31#define P_MII0_TxCLK    (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
  32
  33#define P_MII0 {\
  34        P_MII0_ETxD0, \
  35        P_MII0_ETxD1, \
  36        P_MII0_ETxD2, \
  37        P_MII0_ETxD3, \
  38        P_MII0_ETxEN, \
  39        P_MII0_TxCLK, \
  40        P_MII0_PHYINT, \
  41        P_MII0_COL, \
  42        P_MII0_ERxD0, \
  43        P_MII0_ERxD1, \
  44        P_MII0_ERxD2, \
  45        P_MII0_ERxD3, \
  46        P_MII0_ERxDV, \
  47        P_MII0_ERxCLK, \
  48        P_MII0_ERxER, \
  49        P_MII0_CRS, \
  50        P_MII0_MDC, \
  51        P_MII0_MDIO, 0}
  52
  53#define P_RMII0 {\
  54        P_MII0_ETxD0, \
  55        P_MII0_ETxD1, \
  56        P_MII0_ETxEN, \
  57        P_MII0_ERxD0, \
  58        P_MII0_ERxD1, \
  59        P_MII0_ERxER, \
  60        P_MII0_TxCLK, \
  61        P_MII0_PHYINT, \
  62        P_MII0_CRS, \
  63        P_MII0_MDC, \
  64        P_MII0_MDIO, 0}
  65
  66/* PPI Port Mux */
  67#define P_PPI0_D0       (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
  68#define P_PPI0_D1       (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
  69#define P_PPI0_D2       (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
  70#define P_PPI0_D3       (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
  71#define P_PPI0_D4       (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
  72#define P_PPI0_D5       (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
  73#define P_PPI0_D6       (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
  74#define P_PPI0_D7       (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
  75#define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
  76#define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
  77#define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
  78#define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
  79#define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
  80#define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
  81#define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
  82#define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
  83
  84#ifndef CONFIG_BF518_PPI_TMR_PG12
  85#define P_PPI0_CLK      (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
  86#define P_PPI0_FS1      (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
  87#define P_PPI0_FS2      (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
  88#else
  89#define P_PPI0_CLK      (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
  90#define P_PPI0_FS1      (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
  91#define P_PPI0_FS2      (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
  92#endif
  93#define P_PPI0_FS3      (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
  94
  95/* SPI Port Mux */
  96#define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
  97#define P_SPI0_SCK      (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
  98#define P_SPI0_MISO     (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
  99#define P_SPI0_MOSI     (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
 100
 101#define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
 102#define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
 103#define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
 104#define P_SPI0_SSEL4    (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
 105#define P_SPI0_SSEL5    (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
 106
 107#define P_SPI1_SS       (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
 108#define P_SPI1_SCK      (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
 109#define P_SPI1_MISO     (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
 110#define P_SPI1_MOSI     (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
 111
 112#define P_SPI1_SSEL1    (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
 113#define P_SPI1_SSEL2    (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
 114#define P_SPI1_SSEL3    (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
 115#define P_SPI1_SSEL4    (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
 116#define P_SPI1_SSEL5    (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
 117
 118#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG15
 119#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
 120
 121/* SPORT Port Mux */
 122#define P_SPORT0_DRPRI  (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
 123#define P_SPORT0_RSCLK  (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
 124#define P_SPORT0_RFS    (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
 125#define P_SPORT0_TFS    (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
 126#define P_SPORT0_DTPRI  (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
 127#define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
 128#define P_SPORT0_DTSEC  (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
 129#define P_SPORT0_DRSEC  (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
 130
 131#define P_SPORT1_DRPRI  (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
 132#define P_SPORT1_RFS    (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
 133#define P_SPORT1_RSCLK  (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
 134#define P_SPORT1_DTPRI  (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
 135#define P_SPORT1_TFS    (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
 136#define P_SPORT1_TSCLK  (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
 137#define P_SPORT1_DTSEC  (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
 138#define P_SPORT1_DRSEC  (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
 139
 140/* UART Port Mux */
 141#define P_UART0_TX      (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
 142#define P_UART0_RX      (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
 143
 144#define P_UART1_TX      (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
 145#define P_UART1_RX      (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
 146
 147/* Timer */
 148#ifndef CONFIG_BF518_PPI_TMR_PG12
 149#define P_TMRCLK        (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
 150#define P_TMR0          (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
 151#define P_TMR1          (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
 152#else
 153#define P_TMRCLK        (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
 154#define P_TMR0          (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
 155#define P_TMR1          (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
 156#endif
 157#define P_TMR2          (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
 158#define P_TMR3          (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
 159#define P_TMR4          (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
 160#define P_TMR5          (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
 161#define P_TMR6          (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
 162#define P_TMR7          (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
 163
 164/* DMA */
 165#define P_DMAR1         (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
 166#define P_DMAR0         (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
 167
 168/* TWI */
 169#define P_TWI0_SCL      (P_DONTCARE)
 170#define P_TWI0_SDA      (P_DONTCARE)
 171
 172/* PWM */
 173#ifndef CONFIG_BF518_PWM_PORTF_PORTG
 174#define P_PWM_AH                (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
 175#define P_PWM_AL                (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
 176#define P_PWM_BH                (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
 177#define P_PWM_BL                (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
 178#define P_PWM_CH                (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
 179#define P_PWM_CL                (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
 180#else
 181#define P_PWM_AH                (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
 182#define P_PWM_AL                (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
 183#define P_PWM_BH                (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
 184#define P_PWM_BL                (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
 185#define P_PWM_CH                (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
 186#define P_PWM_CL                (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
 187#endif
 188
 189#ifndef CONFIG_BF518_PWM_SYNC_PF15
 190#define P_PWM_SYNC              (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
 191#else
 192#define P_PWM_SYNC              (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
 193#endif
 194
 195#ifndef CONFIG_BF518_PWM_TRIPB_PG14
 196#define P_PWM_TRIPB             (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2))
 197#else
 198#define P_PWM_TRIPB             (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
 199#endif
 200
 201/* RSI */
 202#define P_RSI_DATA0             (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
 203#define P_RSI_DATA1             (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
 204#define P_RSI_DATA2             (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
 205#define P_RSI_DATA3             (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
 206#define P_RSI_DATA4             (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
 207#define P_RSI_DATA5             (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
 208#define P_RSI_DATA6             (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
 209#define P_RSI_DATA7             (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
 210#define P_RSI_CMD               (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
 211#define P_RSI_CLK               (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
 212
 213/* PTP */
 214#define P_PTP_PPS               (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
 215#define P_PTP_CLKOUT            (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
 216
 217/* AMS */
 218#define P_AMS2                  (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
 219#define P_AMS3                  (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
 220
 221#define P_HWAIT                 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1))
 222
 223#endif                          /* _MACH_PORTMUX_H_ */
 224