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9#include <linux/device.h>
10#include <linux/platform_device.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h>
13#include <linux/mtd/physmap.h>
14#include <linux/spi/spi.h>
15#include <linux/spi/flash.h>
16#include <linux/irq.h>
17#include <linux/i2c.h>
18#include <linux/interrupt.h>
19#include <linux/usb/musb.h>
20#include <linux/pinctrl/machine.h>
21#include <linux/pinctrl/pinconf-generic.h>
22#include <linux/platform_data/pinctrl-adi2.h>
23#include <linux/spi/adi_spi3.h>
24#include <linux/gpio.h>
25#include <asm/dma.h>
26#include <asm/nand.h>
27#include <asm/dpmc.h>
28#include <asm/portmux.h>
29#include <asm/bfin_sdh.h>
30#include <linux/input.h>
31#include <linux/spi/ad7877.h>
32
33
34
35
36const char bfin_board_name[] = "ADI BF609-EZKIT";
37
38
39
40
41
42#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
43#include <linux/usb/isp1760.h>
44static struct resource bfin_isp1760_resources[] = {
45 [0] = {
46 .start = 0x2C0C0000,
47 .end = 0x2C0C0000 + 0xfffff,
48 .flags = IORESOURCE_MEM,
49 },
50 [1] = {
51 .start = IRQ_PG7,
52 .end = IRQ_PG7,
53 .flags = IORESOURCE_IRQ,
54 },
55};
56
57static struct isp1760_platform_data isp1760_priv = {
58 .is_isp1761 = 0,
59 .bus_width_16 = 1,
60 .port1_otg = 0,
61 .analog_oc = 0,
62 .dack_polarity_high = 0,
63 .dreq_polarity_high = 0,
64};
65
66static struct platform_device bfin_isp1760_device = {
67 .name = "isp1760",
68 .id = 0,
69 .dev = {
70 .platform_data = &isp1760_priv,
71 },
72 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
73 .resource = bfin_isp1760_resources,
74};
75#endif
76
77#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
78#include <linux/platform_data/bfin_rotary.h>
79
80static struct bfin_rotary_platform_data bfin_rotary_data = {
81
82
83 .rotary_rel_code = REL_WHEEL,
84 .rotary_button_key = KEY_ENTER,
85 .debounce = 10,
86 .mode = ROT_QUAD_ENC | ROT_DEBE,
87};
88
89static struct resource bfin_rotary_resources[] = {
90 {
91 .start = CNT_CONFIG,
92 .end = CNT_CONFIG + 0xff,
93 .flags = IORESOURCE_MEM,
94 },
95 {
96 .start = IRQ_CNT,
97 .end = IRQ_CNT,
98 .flags = IORESOURCE_IRQ,
99 },
100};
101
102static struct platform_device bfin_rotary_device = {
103 .name = "bfin-rotary",
104 .id = -1,
105 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
106 .resource = bfin_rotary_resources,
107 .dev = {
108 .platform_data = &bfin_rotary_data,
109 },
110};
111#endif
112
113#if IS_ENABLED(CONFIG_STMMAC_ETH)
114#include <linux/stmmac.h>
115#include <linux/phy.h>
116
117static struct stmmac_mdio_bus_data phy_private_data = {
118 .phy_mask = 1,
119};
120
121static struct stmmac_dma_cfg eth_dma_cfg = {
122 .pbl = 2,
123};
124
125int stmmac_ptp_clk_init(struct platform_device *pdev, void *priv)
126{
127 bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0);
128 return 0;
129}
130
131static struct plat_stmmacenet_data eth_private_data = {
132 .has_gmac = 1,
133 .bus_id = 0,
134 .enh_desc = 1,
135 .phy_addr = 1,
136 .mdio_bus_data = &phy_private_data,
137 .dma_cfg = ð_dma_cfg,
138 .force_thresh_dma_mode = 1,
139 .interface = PHY_INTERFACE_MODE_RMII,
140 .init = stmmac_ptp_clk_init,
141};
142
143static struct platform_device bfin_eth_device = {
144 .name = "stmmaceth",
145 .id = 0,
146 .num_resources = 2,
147 .resource = (struct resource[]) {
148 {
149 .start = EMAC0_MACCFG,
150 .end = EMAC0_MACCFG + 0x1274,
151 .flags = IORESOURCE_MEM,
152 },
153 {
154 .name = "macirq",
155 .start = IRQ_EMAC0_STAT,
156 .end = IRQ_EMAC0_STAT,
157 .flags = IORESOURCE_IRQ,
158 },
159 },
160 .dev = {
161 .power.can_wakeup = 1,
162 .platform_data = ð_private_data,
163 }
164};
165#endif
166
167#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
168#include <linux/input/adxl34x.h>
169static const struct adxl34x_platform_data adxl34x_info = {
170 .x_axis_offset = 0,
171 .y_axis_offset = 0,
172 .z_axis_offset = 0,
173 .tap_threshold = 0x31,
174 .tap_duration = 0x10,
175 .tap_latency = 0x60,
176 .tap_window = 0xF0,
177 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
178 .act_axis_control = 0xFF,
179 .activity_threshold = 5,
180 .inactivity_threshold = 3,
181 .inactivity_time = 4,
182 .free_fall_threshold = 0x7,
183 .free_fall_time = 0x20,
184 .data_rate = 0x8,
185 .data_range = ADXL_FULL_RES,
186
187 .ev_type = EV_ABS,
188 .ev_code_x = ABS_X,
189 .ev_code_y = ABS_Y,
190 .ev_code_z = ABS_Z,
191
192 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH},
193
194
195
196 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
197 .fifo_mode = ADXL_FIFO_STREAM,
198 .orientation_enable = ADXL_EN_ORIENTATION_3D,
199 .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
200 .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
201
202 .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
203};
204#endif
205
206#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
207static struct platform_device rtc_device = {
208 .name = "rtc-bfin",
209 .id = -1,
210};
211#endif
212
213#if IS_ENABLED(CONFIG_SERIAL_BFIN)
214#ifdef CONFIG_SERIAL_BFIN_UART0
215static struct resource bfin_uart0_resources[] = {
216 {
217 .start = UART0_REVID,
218 .end = UART0_RXDIV+4,
219 .flags = IORESOURCE_MEM,
220 },
221#ifdef CONFIG_EARLY_PRINTK
222 {
223 .start = PORTD_FER,
224 .end = PORTD_FER+2,
225 .flags = IORESOURCE_REG,
226 },
227 {
228 .start = PORTD_MUX,
229 .end = PORTD_MUX+3,
230 .flags = IORESOURCE_REG,
231 },
232#endif
233 {
234 .start = IRQ_UART0_TX,
235 .end = IRQ_UART0_TX,
236 .flags = IORESOURCE_IRQ,
237 },
238 {
239 .start = IRQ_UART0_RX,
240 .end = IRQ_UART0_RX,
241 .flags = IORESOURCE_IRQ,
242 },
243 {
244 .start = IRQ_UART0_STAT,
245 .end = IRQ_UART0_STAT,
246 .flags = IORESOURCE_IRQ,
247 },
248 {
249 .start = CH_UART0_TX,
250 .end = CH_UART0_TX,
251 .flags = IORESOURCE_DMA,
252 },
253 {
254 .start = CH_UART0_RX,
255 .end = CH_UART0_RX,
256 .flags = IORESOURCE_DMA,
257 },
258#ifdef CONFIG_BFIN_UART0_CTSRTS
259 {
260 .start = GPIO_PD10,
261 .end = GPIO_PD10,
262 .flags = IORESOURCE_IO,
263 },
264 {
265 .start = GPIO_PD9,
266 .end = GPIO_PD9,
267 .flags = IORESOURCE_IO,
268 },
269#endif
270};
271
272static unsigned short bfin_uart0_peripherals[] = {
273 P_UART0_TX, P_UART0_RX,
274#ifdef CONFIG_BFIN_UART0_CTSRTS
275 P_UART0_RTS, P_UART0_CTS,
276#endif
277 0
278};
279
280static struct platform_device bfin_uart0_device = {
281 .name = "bfin-uart",
282 .id = 0,
283 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
284 .resource = bfin_uart0_resources,
285 .dev = {
286 .platform_data = &bfin_uart0_peripherals,
287 },
288};
289#endif
290#ifdef CONFIG_SERIAL_BFIN_UART1
291static struct resource bfin_uart1_resources[] = {
292 {
293 .start = UART1_REVID,
294 .end = UART1_RXDIV+4,
295 .flags = IORESOURCE_MEM,
296 },
297#ifdef CONFIG_EARLY_PRINTK
298 {
299 .start = PORTG_FER_SET,
300 .end = PORTG_FER_SET+2,
301 .flags = IORESOURCE_REG,
302 },
303#endif
304 {
305 .start = IRQ_UART1_TX,
306 .end = IRQ_UART1_TX,
307 .flags = IORESOURCE_IRQ,
308 },
309 {
310 .start = IRQ_UART1_RX,
311 .end = IRQ_UART1_RX,
312 .flags = IORESOURCE_IRQ,
313 },
314 {
315 .start = IRQ_UART1_STAT,
316 .end = IRQ_UART1_STAT,
317 .flags = IORESOURCE_IRQ,
318 },
319 {
320 .start = CH_UART1_TX,
321 .end = CH_UART1_TX,
322 .flags = IORESOURCE_DMA,
323 },
324 {
325 .start = CH_UART1_RX,
326 .end = CH_UART1_RX,
327 .flags = IORESOURCE_DMA,
328 },
329#ifdef CONFIG_BFIN_UART1_CTSRTS
330 {
331 .start = GPIO_PG13,
332 .end = GPIO_PG13,
333 .flags = IORESOURCE_IO,
334 },
335 {
336 .start = GPIO_PG10,
337 .end = GPIO_PG10,
338 .flags = IORESOURCE_IO,
339 },
340#endif
341};
342
343static unsigned short bfin_uart1_peripherals[] = {
344 P_UART1_TX, P_UART1_RX,
345#ifdef CONFIG_BFIN_UART1_CTSRTS
346 P_UART1_RTS, P_UART1_CTS,
347#endif
348 0
349};
350
351static struct platform_device bfin_uart1_device = {
352 .name = "bfin-uart",
353 .id = 1,
354 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
355 .resource = bfin_uart1_resources,
356 .dev = {
357 .platform_data = &bfin_uart1_peripherals,
358 },
359};
360#endif
361#endif
362
363#if IS_ENABLED(CONFIG_BFIN_SIR)
364#ifdef CONFIG_BFIN_SIR0
365static struct resource bfin_sir0_resources[] = {
366 {
367 .start = 0xFFC00400,
368 .end = 0xFFC004FF,
369 .flags = IORESOURCE_MEM,
370 },
371 {
372 .start = IRQ_UART0_TX,
373 .end = IRQ_UART0_TX+1,
374 .flags = IORESOURCE_IRQ,
375 },
376 {
377 .start = CH_UART0_TX,
378 .end = CH_UART0_TX+1,
379 .flags = IORESOURCE_DMA,
380 },
381};
382static struct platform_device bfin_sir0_device = {
383 .name = "bfin_sir",
384 .id = 0,
385 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
386 .resource = bfin_sir0_resources,
387};
388#endif
389#ifdef CONFIG_BFIN_SIR1
390static struct resource bfin_sir1_resources[] = {
391 {
392 .start = 0xFFC02000,
393 .end = 0xFFC020FF,
394 .flags = IORESOURCE_MEM,
395 },
396 {
397 .start = IRQ_UART1_TX,
398 .end = IRQ_UART1_TX+1,
399 .flags = IORESOURCE_IRQ,
400 },
401 {
402 .start = CH_UART1_TX,
403 .end = CH_UART1_TX+1,
404 .flags = IORESOURCE_DMA,
405 },
406};
407static struct platform_device bfin_sir1_device = {
408 .name = "bfin_sir",
409 .id = 1,
410 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
411 .resource = bfin_sir1_resources,
412};
413#endif
414#endif
415
416#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
417static struct resource musb_resources[] = {
418 [0] = {
419 .start = 0xFFCC1000,
420 .end = 0xFFCC1398,
421 .flags = IORESOURCE_MEM,
422 },
423 [1] = {
424 .start = IRQ_USB_STAT,
425 .end = IRQ_USB_STAT,
426 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
427 .name = "mc"
428 },
429 [2] = {
430 .start = IRQ_USB_DMA,
431 .end = IRQ_USB_DMA,
432 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
433 .name = "dma"
434 },
435};
436
437static struct musb_hdrc_config musb_config = {
438 .multipoint = 1,
439 .dyn_fifo = 0,
440 .dma = 1,
441 .num_eps = 16,
442 .dma_channels = 8,
443 .clkin = 48,
444};
445
446static struct musb_hdrc_platform_data musb_plat = {
447#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
448 .mode = MUSB_OTG,
449#elif defined(CONFIG_USB_MUSB_HDRC)
450 .mode = MUSB_HOST,
451#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
452 .mode = MUSB_PERIPHERAL,
453#endif
454 .config = &musb_config,
455};
456
457static u64 musb_dmamask = ~(u32)0;
458
459static struct platform_device musb_device = {
460 .name = "musb-blackfin",
461 .id = 0,
462 .dev = {
463 .dma_mask = &musb_dmamask,
464 .coherent_dma_mask = 0xffffffff,
465 .platform_data = &musb_plat,
466 },
467 .num_resources = ARRAY_SIZE(musb_resources),
468 .resource = musb_resources,
469};
470#endif
471
472#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
473#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
474static struct resource bfin_sport0_uart_resources[] = {
475 {
476 .start = SPORT0_TCR1,
477 .end = SPORT0_MRCS3+4,
478 .flags = IORESOURCE_MEM,
479 },
480 {
481 .start = IRQ_SPORT0_RX,
482 .end = IRQ_SPORT0_RX+1,
483 .flags = IORESOURCE_IRQ,
484 },
485 {
486 .start = IRQ_SPORT0_ERROR,
487 .end = IRQ_SPORT0_ERROR,
488 .flags = IORESOURCE_IRQ,
489 },
490};
491
492static unsigned short bfin_sport0_peripherals[] = {
493 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
494 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
495};
496
497static struct platform_device bfin_sport0_uart_device = {
498 .name = "bfin-sport-uart",
499 .id = 0,
500 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
501 .resource = bfin_sport0_uart_resources,
502 .dev = {
503 .platform_data = &bfin_sport0_peripherals,
504 },
505};
506#endif
507#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
508static struct resource bfin_sport1_uart_resources[] = {
509 {
510 .start = SPORT1_TCR1,
511 .end = SPORT1_MRCS3+4,
512 .flags = IORESOURCE_MEM,
513 },
514 {
515 .start = IRQ_SPORT1_RX,
516 .end = IRQ_SPORT1_RX+1,
517 .flags = IORESOURCE_IRQ,
518 },
519 {
520 .start = IRQ_SPORT1_ERROR,
521 .end = IRQ_SPORT1_ERROR,
522 .flags = IORESOURCE_IRQ,
523 },
524};
525
526static unsigned short bfin_sport1_peripherals[] = {
527 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
528 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
529};
530
531static struct platform_device bfin_sport1_uart_device = {
532 .name = "bfin-sport-uart",
533 .id = 1,
534 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
535 .resource = bfin_sport1_uart_resources,
536 .dev = {
537 .platform_data = &bfin_sport1_peripherals,
538 },
539};
540#endif
541#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
542static struct resource bfin_sport2_uart_resources[] = {
543 {
544 .start = SPORT2_TCR1,
545 .end = SPORT2_MRCS3+4,
546 .flags = IORESOURCE_MEM,
547 },
548 {
549 .start = IRQ_SPORT2_RX,
550 .end = IRQ_SPORT2_RX+1,
551 .flags = IORESOURCE_IRQ,
552 },
553 {
554 .start = IRQ_SPORT2_ERROR,
555 .end = IRQ_SPORT2_ERROR,
556 .flags = IORESOURCE_IRQ,
557 },
558};
559
560static unsigned short bfin_sport2_peripherals[] = {
561 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
562 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
563};
564
565static struct platform_device bfin_sport2_uart_device = {
566 .name = "bfin-sport-uart",
567 .id = 2,
568 .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
569 .resource = bfin_sport2_uart_resources,
570 .dev = {
571 .platform_data = &bfin_sport2_peripherals,
572 },
573};
574#endif
575#endif
576
577#if IS_ENABLED(CONFIG_CAN_BFIN)
578
579static unsigned short bfin_can0_peripherals[] = {
580 P_CAN0_RX, P_CAN0_TX, 0
581};
582
583static struct resource bfin_can0_resources[] = {
584 {
585 .start = 0xFFC00A00,
586 .end = 0xFFC00FFF,
587 .flags = IORESOURCE_MEM,
588 },
589 {
590 .start = IRQ_CAN0_RX,
591 .end = IRQ_CAN0_RX,
592 .flags = IORESOURCE_IRQ,
593 },
594 {
595 .start = IRQ_CAN0_TX,
596 .end = IRQ_CAN0_TX,
597 .flags = IORESOURCE_IRQ,
598 },
599 {
600 .start = IRQ_CAN0_STAT,
601 .end = IRQ_CAN0_STAT,
602 .flags = IORESOURCE_IRQ,
603 },
604};
605
606static struct platform_device bfin_can0_device = {
607 .name = "bfin_can",
608 .id = 0,
609 .num_resources = ARRAY_SIZE(bfin_can0_resources),
610 .resource = bfin_can0_resources,
611 .dev = {
612 .platform_data = &bfin_can0_peripherals,
613 },
614};
615
616#endif
617
618#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
619static struct mtd_partition partition_info[] = {
620 {
621 .name = "bootloader(nand)",
622 .offset = 0,
623 .size = 0x80000,
624 }, {
625 .name = "linux kernel(nand)",
626 .offset = MTDPART_OFS_APPEND,
627 .size = 4 * 1024 * 1024,
628 },
629 {
630 .name = "file system(nand)",
631 .offset = MTDPART_OFS_APPEND,
632 .size = MTDPART_SIZ_FULL,
633 },
634};
635
636static struct bf5xx_nand_platform bfin_nand_platform = {
637 .data_width = NFC_NWIDTH_8,
638 .partitions = partition_info,
639 .nr_partitions = ARRAY_SIZE(partition_info),
640 .rd_dly = 3,
641 .wr_dly = 3,
642};
643
644static struct resource bfin_nand_resources[] = {
645 {
646 .start = 0xFFC03B00,
647 .end = 0xFFC03B4F,
648 .flags = IORESOURCE_MEM,
649 },
650 {
651 .start = CH_NFC,
652 .end = CH_NFC,
653 .flags = IORESOURCE_IRQ,
654 },
655};
656
657static struct platform_device bfin_nand_device = {
658 .name = "bfin-nand",
659 .id = 0,
660 .num_resources = ARRAY_SIZE(bfin_nand_resources),
661 .resource = bfin_nand_resources,
662 .dev = {
663 .platform_data = &bfin_nand_platform,
664 },
665};
666#endif
667
668#if IS_ENABLED(CONFIG_SDH_BFIN)
669
670static struct bfin_sd_host bfin_sdh_data = {
671 .dma_chan = CH_RSI,
672 .irq_int0 = IRQ_RSI_INT0,
673 .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
674};
675
676static struct platform_device bfin_sdh_device = {
677 .name = "bfin-sdh",
678 .id = 0,
679 .dev = {
680 .platform_data = &bfin_sdh_data,
681 },
682};
683#endif
684
685#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
686static struct mtd_partition ezkit_partitions[] = {
687 {
688 .name = "bootloader(nor)",
689 .size = 0x80000,
690 .offset = 0,
691 }, {
692 .name = "linux kernel(nor)",
693 .size = 0x400000,
694 .offset = MTDPART_OFS_APPEND,
695 }, {
696 .name = "file system(nor)",
697 .size = 0x1000000 - 0x80000 - 0x400000,
698 .offset = MTDPART_OFS_APPEND,
699 },
700};
701
702int bf609_nor_flash_init(struct platform_device *pdev)
703{
704#define CONFIG_SMC_GCTL_VAL 0x00000010
705
706 bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
707 bfin_write32(SMC_B0CTL, 0x01002011);
708 bfin_write32(SMC_B0TIM, 0x08170977);
709 bfin_write32(SMC_B0ETIM, 0x00092231);
710 return 0;
711}
712
713void bf609_nor_flash_exit(struct platform_device *pdev)
714{
715 bfin_write32(SMC_GCTL, 0);
716}
717
718static struct physmap_flash_data ezkit_flash_data = {
719 .width = 2,
720 .parts = ezkit_partitions,
721 .init = bf609_nor_flash_init,
722 .exit = bf609_nor_flash_exit,
723 .nr_parts = ARRAY_SIZE(ezkit_partitions),
724#ifdef CONFIG_ROMKERNEL
725 .probe_type = "map_rom",
726#endif
727};
728
729static struct resource ezkit_flash_resource = {
730 .start = 0xb0000000,
731 .end = 0xb0ffffff,
732 .flags = IORESOURCE_MEM,
733};
734
735static struct platform_device ezkit_flash_device = {
736 .name = "physmap-flash",
737 .id = 0,
738 .dev = {
739 .platform_data = &ezkit_flash_data,
740 },
741 .num_resources = 1,
742 .resource = &ezkit_flash_resource,
743};
744#endif
745
746#if IS_ENABLED(CONFIG_MTD_M25P80)
747
748static struct mtd_partition bfin_spi_flash_partitions[] = {
749 {
750 .name = "bootloader(spi)",
751 .size = 0x00080000,
752 .offset = 0,
753 .mask_flags = MTD_CAP_ROM
754 }, {
755 .name = "linux kernel(spi)",
756 .size = 0x00180000,
757 .offset = MTDPART_OFS_APPEND,
758 }, {
759 .name = "file system(spi)",
760 .size = MTDPART_SIZ_FULL,
761 .offset = MTDPART_OFS_APPEND,
762 }
763};
764
765static struct flash_platform_data bfin_spi_flash_data = {
766 .name = "m25p80",
767 .parts = bfin_spi_flash_partitions,
768 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
769 .type = "w25q32",
770};
771
772static struct adi_spi3_chip spi_flash_chip_info = {
773 .enable_dma = true,
774};
775#endif
776
777#if IS_ENABLED(CONFIG_SPI_SPIDEV)
778static struct adi_spi3_chip spidev_chip_info = {
779 .enable_dma = true,
780};
781#endif
782
783#if IS_ENABLED(CONFIG_SND_BF6XX_PCM)
784static struct platform_device bfin_pcm = {
785 .name = "bfin-i2s-pcm-audio",
786 .id = -1,
787};
788#endif
789
790#if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
791#include <asm/bfin_sport3.h>
792static struct resource bfin_snd_resources[] = {
793 {
794 .start = SPORT0_CTL_A,
795 .end = SPORT0_CTL_A,
796 .flags = IORESOURCE_MEM,
797 },
798 {
799 .start = SPORT0_CTL_B,
800 .end = SPORT0_CTL_B,
801 .flags = IORESOURCE_MEM,
802 },
803 {
804 .start = CH_SPORT0_TX,
805 .end = CH_SPORT0_TX,
806 .flags = IORESOURCE_DMA,
807 },
808 {
809 .start = CH_SPORT0_RX,
810 .end = CH_SPORT0_RX,
811 .flags = IORESOURCE_DMA,
812 },
813 {
814 .start = IRQ_SPORT0_TX_STAT,
815 .end = IRQ_SPORT0_TX_STAT,
816 .flags = IORESOURCE_IRQ,
817 },
818 {
819 .start = IRQ_SPORT0_RX_STAT,
820 .end = IRQ_SPORT0_RX_STAT,
821 .flags = IORESOURCE_IRQ,
822 },
823};
824
825static const unsigned short bfin_snd_pin[] = {
826 P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
827 P_SPORT0_BFS, P_SPORT0_BD0, 0,
828};
829
830static struct bfin_snd_platform_data bfin_snd_data = {
831 .pin_req = bfin_snd_pin,
832};
833
834static struct platform_device bfin_i2s = {
835 .name = "bfin-i2s",
836 .num_resources = ARRAY_SIZE(bfin_snd_resources),
837 .resource = bfin_snd_resources,
838 .dev = {
839 .platform_data = &bfin_snd_data,
840 },
841};
842#endif
843
844#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
845static const char * const ad1836_link[] = {
846 "bfin-i2s.0",
847 "spi0.76",
848};
849static struct platform_device bfin_ad1836_machine = {
850 .name = "bfin-snd-ad1836",
851 .id = -1,
852 .dev = {
853 .platform_data = (void *)ad1836_link,
854 },
855};
856#endif
857
858#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
859static struct platform_device adau1761_device = {
860 .name = "bfin-eval-adau1x61",
861};
862#endif
863
864#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
865#include <sound/adau17x1.h>
866static struct adau1761_platform_data adau1761_info = {
867 .lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
868 .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
869};
870#endif
871
872#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
873#include <linux/videodev2.h>
874#include <media/blackfin/bfin_capture.h>
875#include <media/blackfin/ppi.h>
876
877static const unsigned short ppi_req[] = {
878 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
879 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
880 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
881 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
882#if !IS_ENABLED(CONFIG_VIDEO_VS6624)
883 P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
884 P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
885#endif
886 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
887 0,
888};
889
890static const struct ppi_info ppi_info = {
891 .type = PPI_TYPE_EPPI3,
892 .dma_ch = CH_EPPI0_CH0,
893 .irq_err = IRQ_EPPI0_STAT,
894 .base = (void __iomem *)EPPI0_STAT,
895 .pin_req = ppi_req,
896};
897
898#if IS_ENABLED(CONFIG_VIDEO_VS6624)
899static struct v4l2_input vs6624_inputs[] = {
900 {
901 .index = 0,
902 .name = "Camera",
903 .type = V4L2_INPUT_TYPE_CAMERA,
904 .std = V4L2_STD_UNKNOWN,
905 },
906};
907
908static struct bcap_route vs6624_routes[] = {
909 {
910 .input = 0,
911 .output = 0,
912 },
913};
914
915static const unsigned vs6624_ce_pin = GPIO_PE4;
916
917static struct bfin_capture_config bfin_capture_data = {
918 .card_name = "BF609",
919 .inputs = vs6624_inputs,
920 .num_inputs = ARRAY_SIZE(vs6624_inputs),
921 .routes = vs6624_routes,
922 .i2c_adapter_id = 0,
923 .board_info = {
924 .type = "vs6624",
925 .addr = 0x10,
926 .platform_data = (void *)&vs6624_ce_pin,
927 },
928 .ppi_info = &ppi_info,
929 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
930 | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
931 .blank_pixels = 4,
932};
933#endif
934
935#if IS_ENABLED(CONFIG_VIDEO_ADV7842)
936#include <media/i2c/adv7842.h>
937
938static struct v4l2_input adv7842_inputs[] = {
939 {
940 .index = 0,
941 .name = "Composite",
942 .type = V4L2_INPUT_TYPE_CAMERA,
943 .std = V4L2_STD_ALL,
944 .capabilities = V4L2_IN_CAP_STD,
945 },
946 {
947 .index = 1,
948 .name = "S-Video",
949 .type = V4L2_INPUT_TYPE_CAMERA,
950 .std = V4L2_STD_ALL,
951 .capabilities = V4L2_IN_CAP_STD,
952 },
953 {
954 .index = 2,
955 .name = "Component",
956 .type = V4L2_INPUT_TYPE_CAMERA,
957 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
958 },
959 {
960 .index = 3,
961 .name = "VGA",
962 .type = V4L2_INPUT_TYPE_CAMERA,
963 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
964 },
965 {
966 .index = 4,
967 .name = "HDMI",
968 .type = V4L2_INPUT_TYPE_CAMERA,
969 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
970 },
971};
972
973static struct bcap_route adv7842_routes[] = {
974 {
975 .input = 3,
976 .output = 0,
977 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
978 | EPPI_CTL_ACTIVE656),
979 },
980 {
981 .input = 4,
982 .output = 0,
983 },
984 {
985 .input = 2,
986 .output = 0,
987 },
988 {
989 .input = 1,
990 .output = 0,
991 },
992 {
993 .input = 0,
994 .output = 1,
995 .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
996 | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2
997 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
998 },
999};
1000
1001static struct adv7842_output_format adv7842_opf[] = {
1002 {
1003 .op_ch_sel = ADV7842_OP_CH_SEL_BRG,
1004 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8,
1005 .blank_data = 1,
1006 .insert_av_codes = 1,
1007 },
1008 {
1009 .op_ch_sel = ADV7842_OP_CH_SEL_RGB,
1010 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16,
1011 .blank_data = 1,
1012 },
1013};
1014
1015static struct adv7842_platform_data adv7842_data = {
1016 .opf = adv7842_opf,
1017 .num_opf = ARRAY_SIZE(adv7842_opf),
1018 .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
1019 .prim_mode = ADV7842_PRIM_MODE_SDP,
1020 .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
1021 .hdmi_free_run_enable = 1,
1022 .sdp_free_run_auto = 1,
1023 .llc_dll_phase = 0x10,
1024 .i2c_sdp_io = 0x40,
1025 .i2c_sdp = 0x41,
1026 .i2c_cp = 0x42,
1027 .i2c_vdp = 0x43,
1028 .i2c_afe = 0x44,
1029 .i2c_hdmi = 0x45,
1030 .i2c_repeater = 0x46,
1031 .i2c_edid = 0x47,
1032 .i2c_infoframe = 0x48,
1033 .i2c_cec = 0x49,
1034 .i2c_avlink = 0x4a,
1035};
1036
1037static struct bfin_capture_config bfin_capture_data = {
1038 .card_name = "BF609",
1039 .inputs = adv7842_inputs,
1040 .num_inputs = ARRAY_SIZE(adv7842_inputs),
1041 .routes = adv7842_routes,
1042 .i2c_adapter_id = 0,
1043 .board_info = {
1044 .type = "adv7842",
1045 .addr = 0x20,
1046 .platform_data = (void *)&adv7842_data,
1047 },
1048 .ppi_info = &ppi_info,
1049 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
1050 | EPPI_CTL_ACTIVE656),
1051};
1052#endif
1053
1054static struct platform_device bfin_capture_device = {
1055 .name = "bfin_capture",
1056 .dev = {
1057 .platform_data = &bfin_capture_data,
1058 },
1059};
1060#endif
1061
1062#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
1063#include <linux/videodev2.h>
1064#include <media/blackfin/bfin_display.h>
1065#include <media/blackfin/ppi.h>
1066
1067static const unsigned short ppi_req_disp[] = {
1068 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
1069 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
1070 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
1071 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
1072 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
1073 0,
1074};
1075
1076static const struct ppi_info ppi_info = {
1077 .type = PPI_TYPE_EPPI3,
1078 .dma_ch = CH_EPPI0_CH0,
1079 .irq_err = IRQ_EPPI0_STAT,
1080 .base = (void __iomem *)EPPI0_STAT,
1081 .pin_req = ppi_req_disp,
1082};
1083
1084#if IS_ENABLED(CONFIG_VIDEO_ADV7511)
1085#include <media/i2c/adv7511.h>
1086
1087static struct v4l2_output adv7511_outputs[] = {
1088 {
1089 .index = 0,
1090 .name = "HDMI",
1091 .type = V4L2_INPUT_TYPE_CAMERA,
1092 .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
1093 },
1094};
1095
1096static struct disp_route adv7511_routes[] = {
1097 {
1098 .output = 0,
1099 },
1100};
1101
1102static struct adv7511_platform_data adv7511_data = {
1103 .edid_addr = 0x7e,
1104};
1105
1106static struct bfin_display_config bfin_display_data = {
1107 .card_name = "BF609",
1108 .outputs = adv7511_outputs,
1109 .num_outputs = ARRAY_SIZE(adv7511_outputs),
1110 .routes = adv7511_routes,
1111 .i2c_adapter_id = 0,
1112 .board_info = {
1113 .type = "adv7511",
1114 .addr = 0x39,
1115 .platform_data = (void *)&adv7511_data,
1116 },
1117 .ppi_info = &ppi_info,
1118 .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
1119 | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3
1120 | EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2
1121 | EPPI_CTL_NON656 | EPPI_CTL_DIR),
1122};
1123#endif
1124
1125#if IS_ENABLED(CONFIG_VIDEO_ADV7343)
1126#include <media/i2c/adv7343.h>
1127
1128static struct v4l2_output adv7343_outputs[] = {
1129 {
1130 .index = 0,
1131 .name = "Composite",
1132 .type = V4L2_OUTPUT_TYPE_ANALOG,
1133 .std = V4L2_STD_ALL,
1134 .capabilities = V4L2_OUT_CAP_STD,
1135 },
1136 {
1137 .index = 1,
1138 .name = "S-Video",
1139 .type = V4L2_OUTPUT_TYPE_ANALOG,
1140 .std = V4L2_STD_ALL,
1141 .capabilities = V4L2_OUT_CAP_STD,
1142 },
1143 {
1144 .index = 2,
1145 .name = "Component",
1146 .type = V4L2_OUTPUT_TYPE_ANALOG,
1147 .std = V4L2_STD_ALL,
1148 .capabilities = V4L2_OUT_CAP_STD,
1149 },
1150
1151};
1152
1153static struct disp_route adv7343_routes[] = {
1154 {
1155 .output = ADV7343_COMPOSITE_ID,
1156 },
1157 {
1158 .output = ADV7343_SVIDEO_ID,
1159 },
1160 {
1161 .output = ADV7343_COMPONENT_ID,
1162 },
1163};
1164
1165static struct adv7343_platform_data adv7343_data = {
1166 .mode_config = {
1167 .sleep_mode = false,
1168 .pll_control = false,
1169 .dac_1 = true,
1170 .dac_2 = true,
1171 .dac_3 = true,
1172 .dac_4 = true,
1173 .dac_5 = true,
1174 .dac_6 = true,
1175 },
1176 .sd_config = {
1177 .sd_dac_out1 = false,
1178 .sd_dac_out2 = false,
1179 },
1180};
1181
1182static struct bfin_display_config bfin_display_data = {
1183 .card_name = "BF609",
1184 .outputs = adv7343_outputs,
1185 .num_outputs = ARRAY_SIZE(adv7343_outputs),
1186 .routes = adv7343_routes,
1187 .i2c_adapter_id = 0,
1188 .board_info = {
1189 .type = "adv7343",
1190 .addr = 0x2b,
1191 .platform_data = (void *)&adv7343_data,
1192 },
1193 .ppi_info = &ppi_info_disp,
1194 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1LO_FS2LO
1195 | EPPI_CTL_POLC3 | EPPI_CTL_BLANKGEN | EPPI_CTL_SYNC2
1196 | EPPI_CTL_NON656 | EPPI_CTL_DIR),
1197};
1198#endif
1199
1200static struct platform_device bfin_display_device = {
1201 .name = "bfin_display",
1202 .dev = {
1203 .platform_data = &bfin_display_data,
1204 },
1205};
1206#endif
1207
1208#if defined(CONFIG_FB_BF609_NL8048) \
1209 || defined(CONFIG_FB_BF609_NL8048_MODULE)
1210static struct resource nl8048_resources[] = {
1211 {
1212 .start = EPPI2_STAT,
1213 .end = EPPI2_STAT,
1214 .flags = IORESOURCE_MEM,
1215 },
1216 {
1217 .start = CH_EPPI2_CH0,
1218 .end = CH_EPPI2_CH0,
1219 .flags = IORESOURCE_DMA,
1220 },
1221 {
1222 .start = IRQ_EPPI2_STAT,
1223 .end = IRQ_EPPI2_STAT,
1224 .flags = IORESOURCE_IRQ,
1225 },
1226};
1227static struct platform_device bfin_fb_device = {
1228 .name = "bf609_nl8048",
1229 .num_resources = ARRAY_SIZE(nl8048_resources),
1230 .resource = nl8048_resources,
1231 .dev = {
1232 .platform_data = (void *)GPIO_PC15,
1233 },
1234};
1235#endif
1236
1237#if defined(CONFIG_BFIN_CRC)
1238#define BFIN_CRC_NAME "bfin-crc"
1239
1240static struct resource bfin_crc0_resources[] = {
1241 {
1242 .start = REG_CRC0_CTL,
1243 .end = REG_CRC0_REVID+4,
1244 .flags = IORESOURCE_MEM,
1245 },
1246 {
1247 .start = IRQ_CRC0_DCNTEXP,
1248 .end = IRQ_CRC0_DCNTEXP,
1249 .flags = IORESOURCE_IRQ,
1250 },
1251 {
1252 .start = CH_MEM_STREAM0_SRC_CRC0,
1253 .end = CH_MEM_STREAM0_SRC_CRC0,
1254 .flags = IORESOURCE_DMA,
1255 },
1256 {
1257 .start = CH_MEM_STREAM0_DEST_CRC0,
1258 .end = CH_MEM_STREAM0_DEST_CRC0,
1259 .flags = IORESOURCE_DMA,
1260 },
1261};
1262
1263static struct platform_device bfin_crc0_device = {
1264 .name = BFIN_CRC_NAME,
1265 .id = 0,
1266 .num_resources = ARRAY_SIZE(bfin_crc0_resources),
1267 .resource = bfin_crc0_resources,
1268};
1269
1270static struct resource bfin_crc1_resources[] = {
1271 {
1272 .start = REG_CRC1_CTL,
1273 .end = REG_CRC1_REVID+4,
1274 .flags = IORESOURCE_MEM,
1275 },
1276 {
1277 .start = IRQ_CRC1_DCNTEXP,
1278 .end = IRQ_CRC1_DCNTEXP,
1279 .flags = IORESOURCE_IRQ,
1280 },
1281 {
1282 .start = CH_MEM_STREAM1_SRC_CRC1,
1283 .end = CH_MEM_STREAM1_SRC_CRC1,
1284 .flags = IORESOURCE_DMA,
1285 },
1286 {
1287 .start = CH_MEM_STREAM1_DEST_CRC1,
1288 .end = CH_MEM_STREAM1_DEST_CRC1,
1289 .flags = IORESOURCE_DMA,
1290 },
1291};
1292
1293static struct platform_device bfin_crc1_device = {
1294 .name = BFIN_CRC_NAME,
1295 .id = 1,
1296 .num_resources = ARRAY_SIZE(bfin_crc1_resources),
1297 .resource = bfin_crc1_resources,
1298};
1299#endif
1300
1301#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
1302#define BFIN_CRYPTO_CRC_NAME "bfin-hmac-crc"
1303#define BFIN_CRYPTO_CRC_POLY_DATA 0x5c5c5c5c
1304
1305static struct resource bfin_crypto_crc_resources[] = {
1306 {
1307 .start = REG_CRC0_CTL,
1308 .end = REG_CRC0_REVID+4,
1309 .flags = IORESOURCE_MEM,
1310 },
1311 {
1312 .start = IRQ_CRC0_DCNTEXP,
1313 .end = IRQ_CRC0_DCNTEXP,
1314 .flags = IORESOURCE_IRQ,
1315 },
1316 {
1317 .start = CH_MEM_STREAM0_SRC_CRC0,
1318 .end = CH_MEM_STREAM0_SRC_CRC0,
1319 .flags = IORESOURCE_DMA,
1320 },
1321};
1322
1323static struct platform_device bfin_crypto_crc_device = {
1324 .name = BFIN_CRYPTO_CRC_NAME,
1325 .id = 0,
1326 .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources),
1327 .resource = bfin_crypto_crc_resources,
1328 .dev = {
1329 .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA,
1330 },
1331};
1332#endif
1333
1334#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
1335static const struct ad7877_platform_data bfin_ad7877_ts_info = {
1336 .model = 7877,
1337 .vref_delay_usecs = 50,
1338 .x_plate_ohms = 419,
1339 .y_plate_ohms = 486,
1340 .pressure_max = 1000,
1341 .pressure_min = 0,
1342 .stopacq_polarity = 1,
1343 .first_conversion_delay = 3,
1344 .acquisition_time = 1,
1345 .averaging = 1,
1346 .pen_down_acc_interval = 1,
1347};
1348#endif
1349
1350#ifdef CONFIG_PINCTRL_ADI2
1351
1352# define ADI_PINT_DEVNAME "adi-gpio-pint"
1353# define ADI_GPIO_DEVNAME "adi-gpio"
1354# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
1355
1356static struct platform_device bfin_pinctrl_device = {
1357 .name = ADI_PINCTRL_DEVNAME,
1358 .id = 0,
1359};
1360
1361static struct resource bfin_pint0_resources[] = {
1362 {
1363 .start = PINT0_MASK_SET,
1364 .end = PINT0_LATCH + 3,
1365 .flags = IORESOURCE_MEM,
1366 },
1367 {
1368 .start = IRQ_PINT0,
1369 .end = IRQ_PINT0,
1370 .flags = IORESOURCE_IRQ,
1371 },
1372};
1373
1374static struct platform_device bfin_pint0_device = {
1375 .name = ADI_PINT_DEVNAME,
1376 .id = 0,
1377 .num_resources = ARRAY_SIZE(bfin_pint0_resources),
1378 .resource = bfin_pint0_resources,
1379};
1380
1381static struct resource bfin_pint1_resources[] = {
1382 {
1383 .start = PINT1_MASK_SET,
1384 .end = PINT1_LATCH + 3,
1385 .flags = IORESOURCE_MEM,
1386 },
1387 {
1388 .start = IRQ_PINT1,
1389 .end = IRQ_PINT1,
1390 .flags = IORESOURCE_IRQ,
1391 },
1392};
1393
1394static struct platform_device bfin_pint1_device = {
1395 .name = ADI_PINT_DEVNAME,
1396 .id = 1,
1397 .num_resources = ARRAY_SIZE(bfin_pint1_resources),
1398 .resource = bfin_pint1_resources,
1399};
1400
1401static struct resource bfin_pint2_resources[] = {
1402 {
1403 .start = PINT2_MASK_SET,
1404 .end = PINT2_LATCH + 3,
1405 .flags = IORESOURCE_MEM,
1406 },
1407 {
1408 .start = IRQ_PINT2,
1409 .end = IRQ_PINT2,
1410 .flags = IORESOURCE_IRQ,
1411 },
1412};
1413
1414static struct platform_device bfin_pint2_device = {
1415 .name = ADI_PINT_DEVNAME,
1416 .id = 2,
1417 .num_resources = ARRAY_SIZE(bfin_pint2_resources),
1418 .resource = bfin_pint2_resources,
1419};
1420
1421static struct resource bfin_pint3_resources[] = {
1422 {
1423 .start = PINT3_MASK_SET,
1424 .end = PINT3_LATCH + 3,
1425 .flags = IORESOURCE_MEM,
1426 },
1427 {
1428 .start = IRQ_PINT3,
1429 .end = IRQ_PINT3,
1430 .flags = IORESOURCE_IRQ,
1431 },
1432};
1433
1434static struct platform_device bfin_pint3_device = {
1435 .name = ADI_PINT_DEVNAME,
1436 .id = 3,
1437 .num_resources = ARRAY_SIZE(bfin_pint3_resources),
1438 .resource = bfin_pint3_resources,
1439};
1440
1441static struct resource bfin_pint4_resources[] = {
1442 {
1443 .start = PINT4_MASK_SET,
1444 .end = PINT4_LATCH + 3,
1445 .flags = IORESOURCE_MEM,
1446 },
1447 {
1448 .start = IRQ_PINT4,
1449 .end = IRQ_PINT4,
1450 .flags = IORESOURCE_IRQ,
1451 },
1452};
1453
1454static struct platform_device bfin_pint4_device = {
1455 .name = ADI_PINT_DEVNAME,
1456 .id = 4,
1457 .num_resources = ARRAY_SIZE(bfin_pint4_resources),
1458 .resource = bfin_pint4_resources,
1459};
1460
1461static struct resource bfin_pint5_resources[] = {
1462 {
1463 .start = PINT5_MASK_SET,
1464 .end = PINT5_LATCH + 3,
1465 .flags = IORESOURCE_MEM,
1466 },
1467 {
1468 .start = IRQ_PINT5,
1469 .end = IRQ_PINT5,
1470 .flags = IORESOURCE_IRQ,
1471 },
1472};
1473
1474static struct platform_device bfin_pint5_device = {
1475 .name = ADI_PINT_DEVNAME,
1476 .id = 5,
1477 .num_resources = ARRAY_SIZE(bfin_pint5_resources),
1478 .resource = bfin_pint5_resources,
1479};
1480
1481static struct resource bfin_gpa_resources[] = {
1482 {
1483 .start = PORTA_FER,
1484 .end = PORTA_MUX + 3,
1485 .flags = IORESOURCE_MEM,
1486 },
1487 {
1488 .start = IRQ_PA0,
1489 .end = IRQ_PA0,
1490 .flags = IORESOURCE_IRQ,
1491 },
1492};
1493
1494static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
1495 .port_pin_base = GPIO_PA0,
1496 .port_width = GPIO_BANKSIZE,
1497 .pint_id = 0,
1498 .pint_assign = true,
1499 .pint_map = 0,
1500};
1501
1502static struct platform_device bfin_gpa_device = {
1503 .name = ADI_GPIO_DEVNAME,
1504 .id = 0,
1505 .num_resources = ARRAY_SIZE(bfin_gpa_resources),
1506 .resource = bfin_gpa_resources,
1507 .dev = {
1508 .platform_data = &bfin_gpa_pdata,
1509 },
1510};
1511
1512static struct resource bfin_gpb_resources[] = {
1513 {
1514 .start = PORTB_FER,
1515 .end = PORTB_MUX + 3,
1516 .flags = IORESOURCE_MEM,
1517 },
1518 {
1519 .start = IRQ_PB0,
1520 .end = IRQ_PB0,
1521 .flags = IORESOURCE_IRQ,
1522 },
1523};
1524
1525static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
1526 .port_pin_base = GPIO_PB0,
1527 .port_width = GPIO_BANKSIZE,
1528 .pint_id = 0,
1529 .pint_assign = false,
1530 .pint_map = 1,
1531};
1532
1533static struct platform_device bfin_gpb_device = {
1534 .name = ADI_GPIO_DEVNAME,
1535 .id = 1,
1536 .num_resources = ARRAY_SIZE(bfin_gpb_resources),
1537 .resource = bfin_gpb_resources,
1538 .dev = {
1539 .platform_data = &bfin_gpb_pdata,
1540 },
1541};
1542
1543static struct resource bfin_gpc_resources[] = {
1544 {
1545 .start = PORTC_FER,
1546 .end = PORTC_MUX + 3,
1547 .flags = IORESOURCE_MEM,
1548 },
1549 {
1550 .start = IRQ_PC0,
1551 .end = IRQ_PC0,
1552 .flags = IORESOURCE_IRQ,
1553 },
1554};
1555
1556static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
1557 .port_pin_base = GPIO_PC0,
1558 .port_width = GPIO_BANKSIZE,
1559 .pint_id = 1,
1560 .pint_assign = false,
1561 .pint_map = 1,
1562};
1563
1564static struct platform_device bfin_gpc_device = {
1565 .name = ADI_GPIO_DEVNAME,
1566 .id = 2,
1567 .num_resources = ARRAY_SIZE(bfin_gpc_resources),
1568 .resource = bfin_gpc_resources,
1569 .dev = {
1570 .platform_data = &bfin_gpc_pdata,
1571 },
1572};
1573
1574static struct resource bfin_gpd_resources[] = {
1575 {
1576 .start = PORTD_FER,
1577 .end = PORTD_MUX + 3,
1578 .flags = IORESOURCE_MEM,
1579 },
1580 {
1581 .start = IRQ_PD0,
1582 .end = IRQ_PD0,
1583 .flags = IORESOURCE_IRQ,
1584 },
1585};
1586
1587static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
1588 .port_pin_base = GPIO_PD0,
1589 .port_width = GPIO_BANKSIZE,
1590 .pint_id = 2,
1591 .pint_assign = false,
1592 .pint_map = 1,
1593};
1594
1595static struct platform_device bfin_gpd_device = {
1596 .name = ADI_GPIO_DEVNAME,
1597 .id = 3,
1598 .num_resources = ARRAY_SIZE(bfin_gpd_resources),
1599 .resource = bfin_gpd_resources,
1600 .dev = {
1601 .platform_data = &bfin_gpd_pdata,
1602 },
1603};
1604
1605static struct resource bfin_gpe_resources[] = {
1606 {
1607 .start = PORTE_FER,
1608 .end = PORTE_MUX + 3,
1609 .flags = IORESOURCE_MEM,
1610 },
1611 {
1612 .start = IRQ_PE0,
1613 .end = IRQ_PE0,
1614 .flags = IORESOURCE_IRQ,
1615 },
1616};
1617
1618static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
1619 .port_pin_base = GPIO_PE0,
1620 .port_width = GPIO_BANKSIZE,
1621 .pint_id = 3,
1622 .pint_assign = false,
1623 .pint_map = 1,
1624};
1625
1626static struct platform_device bfin_gpe_device = {
1627 .name = ADI_GPIO_DEVNAME,
1628 .id = 4,
1629 .num_resources = ARRAY_SIZE(bfin_gpe_resources),
1630 .resource = bfin_gpe_resources,
1631 .dev = {
1632 .platform_data = &bfin_gpe_pdata,
1633 },
1634};
1635
1636static struct resource bfin_gpf_resources[] = {
1637 {
1638 .start = PORTF_FER,
1639 .end = PORTF_MUX + 3,
1640 .flags = IORESOURCE_MEM,
1641 },
1642 {
1643 .start = IRQ_PF0,
1644 .end = IRQ_PF0,
1645 .flags = IORESOURCE_IRQ,
1646 },
1647};
1648
1649static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
1650 .port_pin_base = GPIO_PF0,
1651 .port_width = GPIO_BANKSIZE,
1652 .pint_id = 4,
1653 .pint_assign = false,
1654 .pint_map = 1,
1655};
1656
1657static struct platform_device bfin_gpf_device = {
1658 .name = ADI_GPIO_DEVNAME,
1659 .id = 5,
1660 .num_resources = ARRAY_SIZE(bfin_gpf_resources),
1661 .resource = bfin_gpf_resources,
1662 .dev = {
1663 .platform_data = &bfin_gpf_pdata,
1664 },
1665};
1666
1667static struct resource bfin_gpg_resources[] = {
1668 {
1669 .start = PORTG_FER,
1670 .end = PORTG_MUX + 3,
1671 .flags = IORESOURCE_MEM,
1672 },
1673 {
1674 .start = IRQ_PG0,
1675 .end = IRQ_PG0,
1676 .flags = IORESOURCE_IRQ,
1677 },
1678};
1679
1680static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
1681 .port_pin_base = GPIO_PG0,
1682 .port_width = GPIO_BANKSIZE,
1683 .pint_id = 5,
1684 .pint_assign = false,
1685 .pint_map = 1,
1686};
1687
1688static struct platform_device bfin_gpg_device = {
1689 .name = ADI_GPIO_DEVNAME,
1690 .id = 6,
1691 .num_resources = ARRAY_SIZE(bfin_gpg_resources),
1692 .resource = bfin_gpg_resources,
1693 .dev = {
1694 .platform_data = &bfin_gpg_pdata,
1695 },
1696};
1697
1698#endif
1699
1700#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
1701#include <linux/input.h>
1702#include <linux/gpio_keys.h>
1703
1704static struct gpio_keys_button bfin_gpio_keys_table[] = {
1705 {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"},
1706 {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"},
1707};
1708
1709static struct gpio_keys_platform_data bfin_gpio_keys_data = {
1710 .buttons = bfin_gpio_keys_table,
1711 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
1712};
1713
1714static struct platform_device bfin_device_gpiokeys = {
1715 .name = "gpio-keys",
1716 .dev = {
1717 .platform_data = &bfin_gpio_keys_data,
1718 },
1719};
1720#endif
1721
1722static struct spi_board_info bfin_spi_board_info[] __initdata = {
1723#if IS_ENABLED(CONFIG_MTD_M25P80)
1724 {
1725
1726 .modalias = "m25p80",
1727 .max_speed_hz = 25000000,
1728 .bus_num = 0,
1729 .chip_select = MAX_CTRL_CS + GPIO_PD11,
1730 .platform_data = &bfin_spi_flash_data,
1731 .controller_data = &spi_flash_chip_info,
1732 .mode = SPI_MODE_3,
1733 },
1734#endif
1735#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
1736 {
1737 .modalias = "ad7877",
1738 .platform_data = &bfin_ad7877_ts_info,
1739 .irq = IRQ_PD9,
1740 .max_speed_hz = 12500000,
1741 .bus_num = 0,
1742 .chip_select = MAX_CTRL_CS + GPIO_PC15,
1743 },
1744#endif
1745#if IS_ENABLED(CONFIG_SPI_SPIDEV)
1746 {
1747 .modalias = "spidev",
1748 .max_speed_hz = 3125000,
1749 .bus_num = 0,
1750 .chip_select = MAX_CTRL_CS + GPIO_PD11,
1751 .controller_data = &spidev_chip_info,
1752 },
1753#endif
1754#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
1755 {
1756 .modalias = "adxl34x",
1757 .platform_data = &adxl34x_info,
1758 .irq = IRQ_PC5,
1759 .max_speed_hz = 5000000,
1760 .bus_num = 1,
1761 .chip_select = 2,
1762 .mode = SPI_MODE_3,
1763 },
1764#endif
1765};
1766#if IS_ENABLED(CONFIG_SPI_ADI_V3)
1767
1768static struct resource bfin_spi0_resource[] = {
1769 {
1770 .start = SPI0_REGBASE,
1771 .end = SPI0_REGBASE + 0xFF,
1772 .flags = IORESOURCE_MEM,
1773 },
1774 {
1775 .start = CH_SPI0_TX,
1776 .end = CH_SPI0_TX,
1777 .flags = IORESOURCE_DMA,
1778 },
1779 {
1780 .start = CH_SPI0_RX,
1781 .end = CH_SPI0_RX,
1782 .flags = IORESOURCE_DMA,
1783 },
1784};
1785
1786
1787static struct resource bfin_spi1_resource[] = {
1788 {
1789 .start = SPI1_REGBASE,
1790 .end = SPI1_REGBASE + 0xFF,
1791 .flags = IORESOURCE_MEM,
1792 },
1793 {
1794 .start = CH_SPI1_TX,
1795 .end = CH_SPI1_TX,
1796 .flags = IORESOURCE_DMA,
1797 },
1798 {
1799 .start = CH_SPI1_RX,
1800 .end = CH_SPI1_RX,
1801 .flags = IORESOURCE_DMA,
1802 },
1803
1804};
1805
1806
1807static struct adi_spi3_master bf60x_spi_master_info0 = {
1808 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1809 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1810};
1811
1812static struct platform_device bf60x_spi_master0 = {
1813 .name = "adi-spi3",
1814 .id = 0,
1815 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1816 .resource = bfin_spi0_resource,
1817 .dev = {
1818 .platform_data = &bf60x_spi_master_info0,
1819 },
1820};
1821
1822static struct adi_spi3_master bf60x_spi_master_info1 = {
1823 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1824 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1825};
1826
1827static struct platform_device bf60x_spi_master1 = {
1828 .name = "adi-spi3",
1829 .id = 1,
1830 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
1831 .resource = bfin_spi1_resource,
1832 .dev = {
1833 .platform_data = &bf60x_spi_master_info1,
1834 },
1835};
1836#endif
1837
1838#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
1839static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
1840
1841static struct resource bfin_twi0_resource[] = {
1842 [0] = {
1843 .start = TWI0_CLKDIV,
1844 .end = TWI0_CLKDIV + 0xFF,
1845 .flags = IORESOURCE_MEM,
1846 },
1847 [1] = {
1848 .start = IRQ_TWI0,
1849 .end = IRQ_TWI0,
1850 .flags = IORESOURCE_IRQ,
1851 },
1852};
1853
1854static struct platform_device i2c_bfin_twi0_device = {
1855 .name = "i2c-bfin-twi",
1856 .id = 0,
1857 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1858 .resource = bfin_twi0_resource,
1859 .dev = {
1860 .platform_data = &bfin_twi0_pins,
1861 },
1862};
1863
1864static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
1865
1866static struct resource bfin_twi1_resource[] = {
1867 [0] = {
1868 .start = TWI1_CLKDIV,
1869 .end = TWI1_CLKDIV + 0xFF,
1870 .flags = IORESOURCE_MEM,
1871 },
1872 [1] = {
1873 .start = IRQ_TWI1,
1874 .end = IRQ_TWI1,
1875 .flags = IORESOURCE_IRQ,
1876 },
1877};
1878
1879static struct platform_device i2c_bfin_twi1_device = {
1880 .name = "i2c-bfin-twi",
1881 .id = 1,
1882 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1883 .resource = bfin_twi1_resource,
1884 .dev = {
1885 .platform_data = &bfin_twi1_pins,
1886 },
1887};
1888#endif
1889
1890#if IS_ENABLED(CONFIG_GPIO_MCP23S08)
1891#include <linux/spi/mcp23s08.h>
1892static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch0 = {
1893 .base = 120,
1894};
1895static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch1 = {
1896 .base = 130,
1897};
1898static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch2 = {
1899 .base = 140,
1900};
1901# if IS_ENABLED(CONFIG_VIDEO_ADV7842)
1902static const struct mcp23s08_platform_data bfin_adv7842_soft_switch = {
1903 .base = 150,
1904};
1905# endif
1906# if IS_ENABLED(CONFIG_VIDEO_ADV7511) || IS_ENABLED(CONFIG_VIDEO_ADV7343)
1907static const struct mcp23s08_platform_data bfin_adv7511_soft_switch = {
1908 .base = 160,
1909};
1910# endif
1911#endif
1912
1913static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
1914#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
1915 {
1916 I2C_BOARD_INFO("adxl34x", 0x53),
1917 .irq = IRQ_PC5,
1918 .platform_data = (void *)&adxl34x_info,
1919 },
1920#endif
1921#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
1922 {
1923 I2C_BOARD_INFO("adau1761", 0x38),
1924 .platform_data = (void *)&adau1761_info
1925 },
1926#endif
1927#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
1928 {
1929 I2C_BOARD_INFO("ssm2602", 0x1b),
1930 },
1931#endif
1932#if IS_ENABLED(CONFIG_GPIO_MCP23S08)
1933 {
1934 I2C_BOARD_INFO("mcp23017", 0x21),
1935 .platform_data = (void *)&bfin_mcp23s08_soft_switch0
1936 },
1937 {
1938 I2C_BOARD_INFO("mcp23017", 0x22),
1939 .platform_data = (void *)&bfin_mcp23s08_soft_switch1
1940 },
1941 {
1942 I2C_BOARD_INFO("mcp23017", 0x23),
1943 .platform_data = (void *)&bfin_mcp23s08_soft_switch2
1944 },
1945# if IS_ENABLED(CONFIG_VIDEO_ADV7842)
1946 {
1947 I2C_BOARD_INFO("mcp23017", 0x26),
1948 .platform_data = (void *)&bfin_adv7842_soft_switch
1949 },
1950# endif
1951# if IS_ENABLED(CONFIG_VIDEO_ADV7511) || IS_ENABLED(CONFIG_VIDEO_ADV7343)
1952 {
1953 I2C_BOARD_INFO("mcp23017", 0x25),
1954 .platform_data = (void *)&bfin_adv7511_soft_switch
1955 },
1956# endif
1957#endif
1958};
1959
1960static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
1961};
1962
1963static const unsigned int cclk_vlev_datasheet[] =
1964{
1965
1966
1967
1968
1969 VRPAIR(VLEV_085, 150000000),
1970 VRPAIR(VLEV_090, 250000000),
1971 VRPAIR(VLEV_110, 276000000),
1972 VRPAIR(VLEV_115, 301000000),
1973 VRPAIR(VLEV_120, 525000000),
1974 VRPAIR(VLEV_125, 550000000),
1975 VRPAIR(VLEV_130, 600000000),
1976};
1977
1978static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1979 .tuple_tab = cclk_vlev_datasheet,
1980 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1981 .vr_settling_time = 25 ,
1982};
1983
1984static struct platform_device bfin_dpmc = {
1985 .name = "bfin dpmc",
1986 .dev = {
1987 .platform_data = &bfin_dmpc_vreg_data,
1988 },
1989};
1990
1991static struct platform_device *ezkit_devices[] __initdata = {
1992
1993 &bfin_dpmc,
1994#if defined(CONFIG_PINCTRL_ADI2)
1995 &bfin_pinctrl_device,
1996 &bfin_pint0_device,
1997 &bfin_pint1_device,
1998 &bfin_pint2_device,
1999 &bfin_pint3_device,
2000 &bfin_pint4_device,
2001 &bfin_pint5_device,
2002 &bfin_gpa_device,
2003 &bfin_gpb_device,
2004 &bfin_gpc_device,
2005 &bfin_gpd_device,
2006 &bfin_gpe_device,
2007 &bfin_gpf_device,
2008 &bfin_gpg_device,
2009#endif
2010
2011#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
2012 &rtc_device,
2013#endif
2014
2015#if IS_ENABLED(CONFIG_SERIAL_BFIN)
2016#ifdef CONFIG_SERIAL_BFIN_UART0
2017 &bfin_uart0_device,
2018#endif
2019#ifdef CONFIG_SERIAL_BFIN_UART1
2020 &bfin_uart1_device,
2021#endif
2022#endif
2023
2024#if IS_ENABLED(CONFIG_BFIN_SIR)
2025#ifdef CONFIG_BFIN_SIR0
2026 &bfin_sir0_device,
2027#endif
2028#ifdef CONFIG_BFIN_SIR1
2029 &bfin_sir1_device,
2030#endif
2031#endif
2032
2033#if IS_ENABLED(CONFIG_STMMAC_ETH)
2034 &bfin_eth_device,
2035#endif
2036
2037#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
2038 &musb_device,
2039#endif
2040
2041#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
2042 &bfin_isp1760_device,
2043#endif
2044
2045#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
2046#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
2047 &bfin_sport0_uart_device,
2048#endif
2049#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
2050 &bfin_sport1_uart_device,
2051#endif
2052#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
2053 &bfin_sport2_uart_device,
2054#endif
2055#endif
2056
2057#if IS_ENABLED(CONFIG_CAN_BFIN)
2058 &bfin_can0_device,
2059#endif
2060
2061#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
2062 &bfin_nand_device,
2063#endif
2064
2065#if IS_ENABLED(CONFIG_SDH_BFIN)
2066 &bfin_sdh_device,
2067#endif
2068
2069#if IS_ENABLED(CONFIG_SPI_ADI_V3)
2070 &bf60x_spi_master0,
2071 &bf60x_spi_master1,
2072#endif
2073
2074#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
2075 &bfin_rotary_device,
2076#endif
2077
2078#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
2079 &i2c_bfin_twi0_device,
2080#if !defined(CONFIG_BF542)
2081 &i2c_bfin_twi1_device,
2082#endif
2083#endif
2084
2085#if defined(CONFIG_BFIN_CRC)
2086 &bfin_crc0_device,
2087 &bfin_crc1_device,
2088#endif
2089#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
2090 &bfin_crypto_crc_device,
2091#endif
2092
2093#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
2094 &bfin_device_gpiokeys,
2095#endif
2096
2097#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
2098 &ezkit_flash_device,
2099#endif
2100#if IS_ENABLED(CONFIG_SND_BF6XX_PCM)
2101 &bfin_pcm,
2102#endif
2103#if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
2104 &bfin_i2s,
2105#endif
2106#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
2107 &bfin_ad1836_machine,
2108#endif
2109#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
2110 &adau1761_device,
2111#endif
2112#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
2113 &bfin_capture_device,
2114#endif
2115#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
2116 &bfin_display_device,
2117#endif
2118
2119};
2120
2121
2122static struct pinctrl_map __initdata bfin_pinmux_map[] = {
2123
2124 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
2125 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
2126 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
2127 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
2128 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
2129 PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"),
2130 PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.0", "pinctrl-adi2.0", NULL, "spi0"),
2131 PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.1", "pinctrl-adi2.0", NULL, "spi1"),
2132 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
2133 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
2134 PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
2135 PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
2136 PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0", "pinctrl-adi2.0", NULL, "smc0"),
2137 PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.0", "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
2138 PIN_MAP_MUX_GROUP("bfin_display.0", "8bit", "pinctrl-adi2.0", "ppi2_8bgrp", "ppi2"),
2139 PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0", "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
2140 PIN_MAP_MUX_GROUP("bfin_display.0", "16bit", "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
2141 PIN_MAP_MUX_GROUP("bfin_capture.0", "8bit", "pinctrl-adi2.0", "ppi0_8bgrp", "ppi0"),
2142 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", "ppi0_16bgrp", "ppi0"),
2143 PIN_MAP_MUX_GROUP("bfin_capture.0", "16bit", "pinctrl-adi2.0", "ppi0_16bgrp", "ppi0"),
2144 PIN_MAP_MUX_GROUP("bfin_capture.0", "24bit", "pinctrl-adi2.0", "ppi0_24bgrp", "ppi0"),
2145 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
2146 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
2147 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
2148 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
2149 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
2150 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
2151};
2152
2153static int __init ezkit_init(void)
2154{
2155 printk(KERN_INFO "%s(): registering device resources\n", __func__);
2156
2157
2158 pinctrl_register_mappings(bfin_pinmux_map,
2159 ARRAY_SIZE(bfin_pinmux_map));
2160
2161 i2c_register_board_info(0, bfin_i2c_board_info0,
2162 ARRAY_SIZE(bfin_i2c_board_info0));
2163 i2c_register_board_info(1, bfin_i2c_board_info1,
2164 ARRAY_SIZE(bfin_i2c_board_info1));
2165
2166 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
2167
2168 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
2169
2170 return 0;
2171}
2172
2173arch_initcall(ezkit_init);
2174
2175static struct platform_device *ezkit_early_devices[] __initdata = {
2176#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
2177#ifdef CONFIG_SERIAL_BFIN_UART0
2178 &bfin_uart0_device,
2179#endif
2180#ifdef CONFIG_SERIAL_BFIN_UART1
2181 &bfin_uart1_device,
2182#endif
2183#endif
2184};
2185
2186void __init native_machine_early_platform_add_devices(void)
2187{
2188 printk(KERN_INFO "register early platform devices\n");
2189 early_platform_add_devices(ezkit_early_devices,
2190 ARRAY_SIZE(ezkit_early_devices));
2191}
2192