LXR linux/arch/cris/arch-v32/mach-a3/dram

   1/*
   2 * DDR SDRAM initialization - alter with care
   3 * This file is intended to be included from other assembler files
   4 *
   5 * Note: This file may not modify r8 or r9 because they are used to
   6 * carry information from the decompressor to the kernel
   7 *
   8 * Copyright (C) 2005-2007 Axis Communications AB
   9 *
  10 * Authors:  Mikael Starvik <starvik@axis.com>
  11 */
  12
  13/* Just to be certain the config file is included, we include it here
  14 * explicitly instead of depending on it being included in the file that
  15 * uses this code.
  16 */
  17
  18#include <hwregs/asm/reg_map_asm.h>
  19#include <hwregs/asm/ddr2_defs_asm.h>
  20
  21        ;; WARNING! The registers r8 and r9 are used as parameters carrying
  22        ;; information from the decompressor (if the kernel was compressed).
  23        ;; They should not be used in the code below.
  24
  25        ;; Refer to ddr2 MDS for initialization sequence
  26
  27        ; 2. Wait 200us
  28        move.d   10000, $r2
  291:      bne      1b
  30        subq     1, $r2
  31
  32        ; Start clock
  33        move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_cfg), $r0
  34        move.d   REG_STATE(ddr2, rw_phy_cfg, en, yes), $r1
  35        move.d   $r1, [$r0]
  36
  37        ; 2. Wait 200us
  38        move.d   10000, $r2
  391:      bne      1b
  40        subq     1, $r2
  41
  42        ; Reset phy and start calibration
  43        move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_ctrl), $r0
  44        move.d   REG_STATE(ddr2, rw_phy_ctrl, rst, yes) | \
  45                 REG_STATE(ddr2, rw_phy_ctrl, cal_rst, yes), $r1
  46        move.d   $r1, [$r0]
  47        move.d   REG_STATE(ddr2, rw_phy_ctrl, cal_start, yes), $r1
  48        move.d   $r1, [$r0]
  49
  50        ; 2. Wait 200us
  51        move.d   10000, $r2
  521:      bne      1b
  53        subq     1, $r2
  54
  55        ; Issue commands
  56        move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_ctrl), $r0
  57        move.d   sdram_commands_start, $r2
  58command_loop:
  59        movu.b  [$r2+], $r1
  60        movu.w  [$r2+], $r3
  61do_cmd:
  62        lslq     16, $r1
  63        or.d     $r3, $r1
  64        move.d   $r1, [$r0]
  65        ; 2. Wait 200us
  66        move.d   10000, $r4
  671:      bne      1b
  68        subq     1, $r4
  69        cmp.d    sdram_commands_end, $r2
  70        blo      command_loop
  71        nop
  72
  73        ; Set timing
  74        move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing), $r0
  75        move.d   CONFIG_ETRAX_DDR2_TIMING, $r1
  76        move.d   $r1, [$r0]
  77
  78        ; Set latency
  79        move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency), $r0
  80        move.d   CONFIG_ETRAX_DDR2_LATENCY, $r1
  81        move.d   $r1, [$r0]
  82
  83        ; Set configuration
  84        move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg), $r0
  85        move.d   CONFIG_ETRAX_DDR2_CONFIG, $r1
  86        move.d   $r1, [$r0]
  87
  88        ba after_sdram_commands
  89        nop
  90
  91sdram_commands_start:
  92        .byte regk_ddr2_deselect
  93        .word 0
  94        .byte regk_ddr2_pre
  95        .word regk_ddr2_pre_all
  96        .byte regk_ddr2_emrs2
  97        .word 0
  98        .byte regk_ddr2_emrs3
  99        .word 0
 100        .byte regk_ddr2_emrs
 101        .word regk_ddr2_dll_en
 102        .byte regk_ddr2_mrs
 103        .word regk_ddr2_dll_rst
 104        .byte regk_ddr2_pre
 105        .word regk_ddr2_pre_all
 106        .byte regk_ddr2_ref
 107        .word 0
 108        .byte regk_ddr2_ref
 109        .word 0
 110        .byte regk_ddr2_mrs
 111        .word CONFIG_ETRAX_DDR2_MRS & 0xffff
 112        .byte regk_ddr2_emrs
 113        .word regk_ddr2_ocd_default | regk_ddr2_dll_en
 114        .byte regk_ddr2_emrs
 115        .word regk_ddr2_ocd_exit | regk_ddr2_dll_en | (CONFIG_ETRAX_DDR2_MRS >> 16)
 116sdram_commands_end:
 117        .align 1
 118after_sdram_commands:
 119