linux/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/timer_defs_asm.h
<<
>>
Prefs
   1#ifndef __timer_defs_asm_h
   2#define __timer_defs_asm_h
   3
   4/*
   5 * This file is autogenerated from
   6 *   file:           ../../inst/timer/rtl/timer_regs.r
   7 *     id:           timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp 
   8 *     last modfied: Mon Apr 11 16:09:53 2005
   9 * 
  10 *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r
  11 *      id: $Id: timer_defs_asm.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $
  12 * Any changes here will be lost.
  13 *
  14 * -*- buffer-read-only: t -*-
  15 */
  16
  17#ifndef REG_FIELD
  18#define REG_FIELD( scope, reg, field, value ) \
  19  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
  20#define REG_FIELD_X_( value, shift ) ((value) << shift)
  21#endif
  22
  23#ifndef REG_STATE
  24#define REG_STATE( scope, reg, field, symbolic_value ) \
  25  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
  26#define REG_STATE_X_( k, shift ) (k << shift)
  27#endif
  28
  29#ifndef REG_MASK
  30#define REG_MASK( scope, reg, field ) \
  31  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
  32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
  33#endif
  34
  35#ifndef REG_LSB
  36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
  37#endif
  38
  39#ifndef REG_BIT
  40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
  41#endif
  42
  43#ifndef REG_ADDR
  44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
  45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
  46#endif
  47
  48#ifndef REG_ADDR_VECT
  49#define REG_ADDR_VECT( scope, inst, reg, index ) \
  50         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
  51                         STRIDE_##scope##_##reg )
  52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
  53                          ((inst) + offs + (index) * stride)
  54#endif
  55
  56/* Register rw_tmr0_div, scope timer, type rw */
  57#define reg_timer_rw_tmr0_div_offset 0
  58
  59/* Register r_tmr0_data, scope timer, type r */
  60#define reg_timer_r_tmr0_data_offset 4
  61
  62/* Register rw_tmr0_ctrl, scope timer, type rw */
  63#define reg_timer_rw_tmr0_ctrl___op___lsb 0
  64#define reg_timer_rw_tmr0_ctrl___op___width 2
  65#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
  66#define reg_timer_rw_tmr0_ctrl___freq___width 3
  67#define reg_timer_rw_tmr0_ctrl_offset 8
  68
  69/* Register rw_tmr1_div, scope timer, type rw */
  70#define reg_timer_rw_tmr1_div_offset 16
  71
  72/* Register r_tmr1_data, scope timer, type r */
  73#define reg_timer_r_tmr1_data_offset 20
  74
  75/* Register rw_tmr1_ctrl, scope timer, type rw */
  76#define reg_timer_rw_tmr1_ctrl___op___lsb 0
  77#define reg_timer_rw_tmr1_ctrl___op___width 2
  78#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
  79#define reg_timer_rw_tmr1_ctrl___freq___width 3
  80#define reg_timer_rw_tmr1_ctrl_offset 24
  81
  82/* Register rs_cnt_data, scope timer, type rs */
  83#define reg_timer_rs_cnt_data___tmr___lsb 0
  84#define reg_timer_rs_cnt_data___tmr___width 24
  85#define reg_timer_rs_cnt_data___cnt___lsb 24
  86#define reg_timer_rs_cnt_data___cnt___width 8
  87#define reg_timer_rs_cnt_data_offset 32
  88
  89/* Register r_cnt_data, scope timer, type r */
  90#define reg_timer_r_cnt_data___tmr___lsb 0
  91#define reg_timer_r_cnt_data___tmr___width 24
  92#define reg_timer_r_cnt_data___cnt___lsb 24
  93#define reg_timer_r_cnt_data___cnt___width 8
  94#define reg_timer_r_cnt_data_offset 36
  95
  96/* Register rw_cnt_cfg, scope timer, type rw */
  97#define reg_timer_rw_cnt_cfg___clk___lsb 0
  98#define reg_timer_rw_cnt_cfg___clk___width 2
  99#define reg_timer_rw_cnt_cfg_offset 40
 100
 101/* Register rw_trig, scope timer, type rw */
 102#define reg_timer_rw_trig_offset 48
 103
 104/* Register rw_trig_cfg, scope timer, type rw */
 105#define reg_timer_rw_trig_cfg___tmr___lsb 0
 106#define reg_timer_rw_trig_cfg___tmr___width 2
 107#define reg_timer_rw_trig_cfg_offset 52
 108
 109/* Register r_time, scope timer, type r */
 110#define reg_timer_r_time_offset 56
 111
 112/* Register rw_out, scope timer, type rw */
 113#define reg_timer_rw_out___tmr___lsb 0
 114#define reg_timer_rw_out___tmr___width 2
 115#define reg_timer_rw_out_offset 60
 116
 117/* Register rw_wd_ctrl, scope timer, type rw */
 118#define reg_timer_rw_wd_ctrl___cnt___lsb 0
 119#define reg_timer_rw_wd_ctrl___cnt___width 8
 120#define reg_timer_rw_wd_ctrl___cmd___lsb 8
 121#define reg_timer_rw_wd_ctrl___cmd___width 1
 122#define reg_timer_rw_wd_ctrl___cmd___bit 8
 123#define reg_timer_rw_wd_ctrl___key___lsb 9
 124#define reg_timer_rw_wd_ctrl___key___width 7
 125#define reg_timer_rw_wd_ctrl_offset 64
 126
 127/* Register r_wd_stat, scope timer, type r */
 128#define reg_timer_r_wd_stat___cnt___lsb 0
 129#define reg_timer_r_wd_stat___cnt___width 8
 130#define reg_timer_r_wd_stat___cmd___lsb 8
 131#define reg_timer_r_wd_stat___cmd___width 1
 132#define reg_timer_r_wd_stat___cmd___bit 8
 133#define reg_timer_r_wd_stat_offset 68
 134
 135/* Register rw_intr_mask, scope timer, type rw */
 136#define reg_timer_rw_intr_mask___tmr0___lsb 0
 137#define reg_timer_rw_intr_mask___tmr0___width 1
 138#define reg_timer_rw_intr_mask___tmr0___bit 0
 139#define reg_timer_rw_intr_mask___tmr1___lsb 1
 140#define reg_timer_rw_intr_mask___tmr1___width 1
 141#define reg_timer_rw_intr_mask___tmr1___bit 1
 142#define reg_timer_rw_intr_mask___cnt___lsb 2
 143#define reg_timer_rw_intr_mask___cnt___width 1
 144#define reg_timer_rw_intr_mask___cnt___bit 2
 145#define reg_timer_rw_intr_mask___trig___lsb 3
 146#define reg_timer_rw_intr_mask___trig___width 1
 147#define reg_timer_rw_intr_mask___trig___bit 3
 148#define reg_timer_rw_intr_mask_offset 72
 149
 150/* Register rw_ack_intr, scope timer, type rw */
 151#define reg_timer_rw_ack_intr___tmr0___lsb 0
 152#define reg_timer_rw_ack_intr___tmr0___width 1
 153#define reg_timer_rw_ack_intr___tmr0___bit 0
 154#define reg_timer_rw_ack_intr___tmr1___lsb 1
 155#define reg_timer_rw_ack_intr___tmr1___width 1
 156#define reg_timer_rw_ack_intr___tmr1___bit 1
 157#define reg_timer_rw_ack_intr___cnt___lsb 2
 158#define reg_timer_rw_ack_intr___cnt___width 1
 159#define reg_timer_rw_ack_intr___cnt___bit 2
 160#define reg_timer_rw_ack_intr___trig___lsb 3
 161#define reg_timer_rw_ack_intr___trig___width 1
 162#define reg_timer_rw_ack_intr___trig___bit 3
 163#define reg_timer_rw_ack_intr_offset 76
 164
 165/* Register r_intr, scope timer, type r */
 166#define reg_timer_r_intr___tmr0___lsb 0
 167#define reg_timer_r_intr___tmr0___width 1
 168#define reg_timer_r_intr___tmr0___bit 0
 169#define reg_timer_r_intr___tmr1___lsb 1
 170#define reg_timer_r_intr___tmr1___width 1
 171#define reg_timer_r_intr___tmr1___bit 1
 172#define reg_timer_r_intr___cnt___lsb 2
 173#define reg_timer_r_intr___cnt___width 1
 174#define reg_timer_r_intr___cnt___bit 2
 175#define reg_timer_r_intr___trig___lsb 3
 176#define reg_timer_r_intr___trig___width 1
 177#define reg_timer_r_intr___trig___bit 3
 178#define reg_timer_r_intr_offset 80
 179
 180/* Register r_masked_intr, scope timer, type r */
 181#define reg_timer_r_masked_intr___tmr0___lsb 0
 182#define reg_timer_r_masked_intr___tmr0___width 1
 183#define reg_timer_r_masked_intr___tmr0___bit 0
 184#define reg_timer_r_masked_intr___tmr1___lsb 1
 185#define reg_timer_r_masked_intr___tmr1___width 1
 186#define reg_timer_r_masked_intr___tmr1___bit 1
 187#define reg_timer_r_masked_intr___cnt___lsb 2
 188#define reg_timer_r_masked_intr___cnt___width 1
 189#define reg_timer_r_masked_intr___cnt___bit 2
 190#define reg_timer_r_masked_intr___trig___lsb 3
 191#define reg_timer_r_masked_intr___trig___width 1
 192#define reg_timer_r_masked_intr___trig___bit 3
 193#define reg_timer_r_masked_intr_offset 84
 194
 195/* Register rw_test, scope timer, type rw */
 196#define reg_timer_rw_test___dis___lsb 0
 197#define reg_timer_rw_test___dis___width 1
 198#define reg_timer_rw_test___dis___bit 0
 199#define reg_timer_rw_test___en___lsb 1
 200#define reg_timer_rw_test___en___width 1
 201#define reg_timer_rw_test___en___bit 1
 202#define reg_timer_rw_test_offset 88
 203
 204
 205/* Constants */
 206#define regk_timer_ext                            0x00000001
 207#define regk_timer_f100                           0x00000007
 208#define regk_timer_f29_493                        0x00000004
 209#define regk_timer_f32                            0x00000005
 210#define regk_timer_f32_768                        0x00000006
 211#define regk_timer_hold                           0x00000001
 212#define regk_timer_ld                             0x00000000
 213#define regk_timer_no                             0x00000000
 214#define regk_timer_off                            0x00000000
 215#define regk_timer_run                            0x00000002
 216#define regk_timer_rw_cnt_cfg_default             0x00000000
 217#define regk_timer_rw_intr_mask_default           0x00000000
 218#define regk_timer_rw_out_default                 0x00000000
 219#define regk_timer_rw_test_default                0x00000000
 220#define regk_timer_rw_tmr0_ctrl_default           0x00000000
 221#define regk_timer_rw_tmr1_ctrl_default           0x00000000
 222#define regk_timer_rw_trig_cfg_default            0x00000000
 223#define regk_timer_start                          0x00000001
 224#define regk_timer_stop                           0x00000000
 225#define regk_timer_time                           0x00000001
 226#define regk_timer_tmr0                           0x00000002
 227#define regk_timer_tmr1                           0x00000003
 228#define regk_timer_yes                            0x00000001
 229#endif /* __timer_defs_asm_h */
 230