linux/arch/frv/kernel/setup.c
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   1/* setup.c: FRV specific setup
   2 *
   3 * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
   4 * Written by David Howells (dhowells@redhat.com)
   5 * - Derived from arch/m68k/kernel/setup.c
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License
   9 * as published by the Free Software Foundation; either version
  10 * 2 of the License, or (at your option) any later version.
  11 */
  12
  13#include <generated/utsrelease.h>
  14#include <linux/kernel.h>
  15#include <linux/sched.h>
  16#include <linux/delay.h>
  17#include <linux/interrupt.h>
  18#include <linux/fs.h>
  19#include <linux/mm.h>
  20#include <linux/fb.h>
  21#include <linux/console.h>
  22#include <linux/genhd.h>
  23#include <linux/errno.h>
  24#include <linux/string.h>
  25#include <linux/major.h>
  26#include <linux/bootmem.h>
  27#include <linux/highmem.h>
  28#include <linux/seq_file.h>
  29#include <linux/serial.h>
  30#include <linux/serial_core.h>
  31#include <linux/serial_reg.h>
  32#include <linux/serial_8250.h>
  33
  34#include <asm/setup.h>
  35#include <asm/irq.h>
  36#include <asm/sections.h>
  37#include <asm/pgalloc.h>
  38#include <asm/busctl-regs.h>
  39#include <asm/serial-regs.h>
  40#include <asm/timer-regs.h>
  41#include <asm/irc-regs.h>
  42#include <asm/spr-regs.h>
  43#include <asm/mb-regs.h>
  44#include <asm/mb93493-regs.h>
  45#include <asm/gdb-stub.h>
  46#include <asm/io.h>
  47
  48#ifdef CONFIG_BLK_DEV_INITRD
  49#include <asm/pgtable.h>
  50#endif
  51
  52#include "local.h"
  53
  54#ifdef CONFIG_MB93090_MB00
  55static void __init mb93090_display(void);
  56#endif
  57#ifdef CONFIG_MMU
  58static void __init setup_linux_memory(void);
  59#else
  60static void __init setup_uclinux_memory(void);
  61#endif
  62
  63#ifdef CONFIG_MB93090_MB00
  64static char __initdata mb93090_banner[] = "FJ/RH FR-V Linux";
  65static char __initdata mb93090_version[] = UTS_RELEASE;
  66
  67int __nongprelbss mb93090_mb00_detected;
  68#endif
  69
  70const char __frv_unknown_system[] = "unknown";
  71const char __frv_mb93091_cb10[] = "mb93091-cb10";
  72const char __frv_mb93091_cb11[] = "mb93091-cb11";
  73const char __frv_mb93091_cb30[] = "mb93091-cb30";
  74const char __frv_mb93091_cb41[] = "mb93091-cb41";
  75const char __frv_mb93091_cb60[] = "mb93091-cb60";
  76const char __frv_mb93091_cb70[] = "mb93091-cb70";
  77const char __frv_mb93091_cb451[] = "mb93091-cb451";
  78const char __frv_mb93090_mb00[] = "mb93090-mb00";
  79
  80const char __frv_mb93493[] = "mb93493";
  81
  82const char __frv_mb93093[] = "mb93093";
  83
  84static const char *__nongprelbss cpu_series;
  85static const char *__nongprelbss cpu_core;
  86static const char *__nongprelbss cpu_silicon;
  87static const char *__nongprelbss cpu_mmu;
  88static const char *__nongprelbss cpu_system;
  89static const char *__nongprelbss cpu_board1;
  90static const char *__nongprelbss cpu_board2;
  91
  92static unsigned long __nongprelbss cpu_psr_all;
  93static unsigned long __nongprelbss cpu_hsr0_all;
  94
  95unsigned long __nongprelbss pdm_suspend_mode;
  96
  97unsigned long __nongprelbss rom_length;
  98unsigned long __nongprelbss memory_start;
  99unsigned long __nongprelbss memory_end;
 100
 101unsigned long __nongprelbss dma_coherent_mem_start;
 102unsigned long __nongprelbss dma_coherent_mem_end;
 103
 104unsigned long __initdata __sdram_old_base;
 105unsigned long __initdata num_mappedpages;
 106
 107char __initdata command_line[COMMAND_LINE_SIZE];
 108char __initdata redboot_command_line[COMMAND_LINE_SIZE];
 109
 110#ifdef CONFIG_PM
 111#define __pminit
 112#define __pminitdata
 113#define __pminitconst
 114#else
 115#define __pminit __init
 116#define __pminitdata __initdata
 117#define __pminitconst __initconst
 118#endif
 119
 120struct clock_cmode {
 121        uint8_t xbus, sdram, corebus, core, dsu;
 122};
 123
 124#define _frac(N,D) ((N)<<4 | (D))
 125#define _x0_16  _frac(1,6)
 126#define _x0_25  _frac(1,4)
 127#define _x0_33  _frac(1,3)
 128#define _x0_375 _frac(3,8)
 129#define _x0_5   _frac(1,2)
 130#define _x0_66  _frac(2,3)
 131#define _x0_75  _frac(3,4)
 132#define _x1     _frac(1,1)
 133#define _x1_5   _frac(3,2)
 134#define _x2     _frac(2,1)
 135#define _x3     _frac(3,1)
 136#define _x4     _frac(4,1)
 137#define _x4_5   _frac(9,2)
 138#define _x6     _frac(6,1)
 139#define _x8     _frac(8,1)
 140#define _x9     _frac(9,1)
 141
 142int __nongprelbss clock_p0_current;
 143int __nongprelbss clock_cm_current;
 144int __nongprelbss clock_cmode_current;
 145#ifdef CONFIG_PM
 146int __nongprelbss clock_cmodes_permitted;
 147unsigned long __nongprelbss clock_bits_settable;
 148#endif
 149
 150static struct clock_cmode __pminitdata undef_clock_cmode = { _x1, _x1, _x1, _x1, _x1 };
 151
 152static struct clock_cmode __pminitdata clock_cmodes_fr401_fr403[16] = {
 153        [4]     = {     _x1,    _x1,    _x2,    _x2,    _x0_25  },
 154        [5]     = {     _x1,    _x2,    _x4,    _x4,    _x0_5   },
 155        [8]     = {     _x1,    _x1,    _x1,    _x2,    _x0_25  },
 156        [9]     = {     _x1,    _x2,    _x2,    _x4,    _x0_5   },
 157        [11]    = {     _x1,    _x4,    _x4,    _x8,    _x1     },
 158        [12]    = {     _x1,    _x1,    _x2,    _x4,    _x0_5   },
 159        [13]    = {     _x1,    _x2,    _x4,    _x8,    _x1     },
 160};
 161
 162static struct clock_cmode __pminitdata clock_cmodes_fr405[16] = {
 163        [0]     = {     _x1,    _x1,    _x1,    _x1,    _x0_5   },
 164        [1]     = {     _x1,    _x1,    _x1,    _x3,    _x0_25  },
 165        [2]     = {     _x1,    _x1,    _x2,    _x6,    _x0_5   },
 166        [3]     = {     _x1,    _x2,    _x2,    _x6,    _x0_5   },
 167        [4]     = {     _x1,    _x1,    _x2,    _x2,    _x0_16  },
 168        [8]     = {     _x1,    _x1,    _x1,    _x2,    _x0_16  },
 169        [9]     = {     _x1,    _x2,    _x2,    _x4,    _x0_33  },
 170        [12]    = {     _x1,    _x1,    _x2,    _x4,    _x0_33  },
 171        [14]    = {     _x1,    _x3,    _x3,    _x9,    _x0_75  },
 172        [15]    = {     _x1,    _x1_5,  _x1_5,  _x4_5,  _x0_375 },
 173
 174#define CLOCK_CMODES_PERMITTED_FR405 0xd31f
 175};
 176
 177static struct clock_cmode __pminitdata clock_cmodes_fr555[16] = {
 178        [0]     = {     _x1,    _x2,    _x2,    _x4,    _x0_33  },
 179        [1]     = {     _x1,    _x3,    _x3,    _x6,    _x0_5   },
 180        [2]     = {     _x1,    _x2,    _x4,    _x8,    _x0_66  },
 181        [3]     = {     _x1,    _x1_5,  _x3,    _x6,    _x0_5   },
 182        [4]     = {     _x1,    _x3,    _x3,    _x9,    _x0_75  },
 183        [5]     = {     _x1,    _x2,    _x2,    _x6,    _x0_5   },
 184        [6]     = {     _x1,    _x1_5,  _x1_5,  _x4_5,  _x0_375 },
 185};
 186
 187static const struct clock_cmode __pminitconst *clock_cmodes;
 188static int __pminitdata clock_doubled;
 189
 190static struct uart_port __pminitdata __frv_uart0 = {
 191        .uartclk                = 0,
 192        .membase                = (char *) UART0_BASE,
 193        .irq                    = IRQ_CPU_UART0,
 194        .regshift               = 3,
 195        .iotype                 = UPIO_MEM,
 196        .flags                  = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 197};
 198
 199static struct uart_port __pminitdata __frv_uart1 = {
 200        .uartclk                = 0,
 201        .membase                = (char *) UART1_BASE,
 202        .irq                    = IRQ_CPU_UART1,
 203        .regshift               = 3,
 204        .iotype                 = UPIO_MEM,
 205        .flags                  = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 206};
 207
 208#if 0
 209static void __init printk_xampr(unsigned long ampr, unsigned long amlr, char i_d, int n)
 210{
 211        unsigned long phys, virt, cxn, size;
 212
 213#ifdef CONFIG_MMU
 214        virt = amlr & 0xffffc000;
 215        cxn = amlr & 0x3fff;
 216#else
 217        virt = ampr & 0xffffc000;
 218        cxn = 0;
 219#endif
 220        phys = ampr & xAMPRx_PPFN;
 221        size = 1 << (((ampr & xAMPRx_SS) >> 4) + 17);
 222
 223        printk("%cAMPR%d: va %08lx-%08lx [pa %08lx] %c%c%c%c [cxn:%04lx]\n",
 224               i_d, n,
 225               virt, virt + size - 1,
 226               phys,
 227               ampr & xAMPRx_S  ? 'S' : '-',
 228               ampr & xAMPRx_C  ? 'C' : '-',
 229               ampr & DAMPRx_WP ? 'W' : '-',
 230               ampr & xAMPRx_V  ? 'V' : '-',
 231               cxn
 232               );
 233}
 234#endif
 235
 236/*****************************************************************************/
 237/*
 238 * dump the memory map
 239 */
 240static void __init dump_memory_map(void)
 241{
 242
 243#if 0
 244        /* dump the protection map */
 245        printk_xampr(__get_IAMPR(0),  __get_IAMLR(0),  'I', 0);
 246        printk_xampr(__get_IAMPR(1),  __get_IAMLR(1),  'I', 1);
 247        printk_xampr(__get_IAMPR(2),  __get_IAMLR(2),  'I', 2);
 248        printk_xampr(__get_IAMPR(3),  __get_IAMLR(3),  'I', 3);
 249        printk_xampr(__get_IAMPR(4),  __get_IAMLR(4),  'I', 4);
 250        printk_xampr(__get_IAMPR(5),  __get_IAMLR(5),  'I', 5);
 251        printk_xampr(__get_IAMPR(6),  __get_IAMLR(6),  'I', 6);
 252        printk_xampr(__get_IAMPR(7),  __get_IAMLR(7),  'I', 7);
 253        printk_xampr(__get_IAMPR(8),  __get_IAMLR(8),  'I', 8);
 254        printk_xampr(__get_IAMPR(9),  __get_IAMLR(9),  'i', 9);
 255        printk_xampr(__get_IAMPR(10), __get_IAMLR(10), 'I', 10);
 256        printk_xampr(__get_IAMPR(11), __get_IAMLR(11), 'I', 11);
 257        printk_xampr(__get_IAMPR(12), __get_IAMLR(12), 'I', 12);
 258        printk_xampr(__get_IAMPR(13), __get_IAMLR(13), 'I', 13);
 259        printk_xampr(__get_IAMPR(14), __get_IAMLR(14), 'I', 14);
 260        printk_xampr(__get_IAMPR(15), __get_IAMLR(15), 'I', 15);
 261
 262        printk_xampr(__get_DAMPR(0),  __get_DAMLR(0),  'D', 0);
 263        printk_xampr(__get_DAMPR(1),  __get_DAMLR(1),  'D', 1);
 264        printk_xampr(__get_DAMPR(2),  __get_DAMLR(2),  'D', 2);
 265        printk_xampr(__get_DAMPR(3),  __get_DAMLR(3),  'D', 3);
 266        printk_xampr(__get_DAMPR(4),  __get_DAMLR(4),  'D', 4);
 267        printk_xampr(__get_DAMPR(5),  __get_DAMLR(5),  'D', 5);
 268        printk_xampr(__get_DAMPR(6),  __get_DAMLR(6),  'D', 6);
 269        printk_xampr(__get_DAMPR(7),  __get_DAMLR(7),  'D', 7);
 270        printk_xampr(__get_DAMPR(8),  __get_DAMLR(8),  'D', 8);
 271        printk_xampr(__get_DAMPR(9),  __get_DAMLR(9),  'D', 9);
 272        printk_xampr(__get_DAMPR(10), __get_DAMLR(10), 'D', 10);
 273        printk_xampr(__get_DAMPR(11), __get_DAMLR(11), 'D', 11);
 274        printk_xampr(__get_DAMPR(12), __get_DAMLR(12), 'D', 12);
 275        printk_xampr(__get_DAMPR(13), __get_DAMLR(13), 'D', 13);
 276        printk_xampr(__get_DAMPR(14), __get_DAMLR(14), 'D', 14);
 277        printk_xampr(__get_DAMPR(15), __get_DAMLR(15), 'D', 15);
 278#endif
 279
 280#if 0
 281        /* dump the bus controller registers */
 282        printk("LGCR: %08lx\n", __get_LGCR());
 283        printk("Master: %08lx-%08lx CR=%08lx\n",
 284               __get_LEMBR(), __get_LEMBR() + __get_LEMAM(),
 285               __get_LMAICR());
 286
 287        int loop;
 288        for (loop = 1; loop <= 7; loop++) {
 289                unsigned long lcr = __get_LCR(loop), lsbr = __get_LSBR(loop);
 290                printk("CS#%d: %08lx-%08lx %c%c%c%c%c%c%c%c%c\n",
 291                       loop,
 292                       lsbr, lsbr + __get_LSAM(loop),
 293                       lcr & 0x80000000 ? 'r' : '-',
 294                       lcr & 0x40000000 ? 'w' : '-',
 295                       lcr & 0x08000000 ? 'b' : '-',
 296                       lcr & 0x04000000 ? 'B' : '-',
 297                       lcr & 0x02000000 ? 'C' : '-',
 298                       lcr & 0x01000000 ? 'D' : '-',
 299                       lcr & 0x00800000 ? 'W' : '-',
 300                       lcr & 0x00400000 ? 'R' : '-',
 301                       (lcr & 0x00030000) == 0x00000000 ? '4' :
 302                       (lcr & 0x00030000) == 0x00010000 ? '2' :
 303                       (lcr & 0x00030000) == 0x00020000 ? '1' :
 304                       '-'
 305                       );
 306        }
 307#endif
 308
 309#if 0
 310        printk("\n");
 311#endif
 312} /* end dump_memory_map() */
 313
 314/*****************************************************************************/
 315/*
 316 * attempt to detect a VDK motherboard and DAV daughter board on an MB93091 system
 317 */
 318#ifdef CONFIG_MB93091_VDK
 319static void __init detect_mb93091(void)
 320{
 321#ifdef CONFIG_MB93090_MB00
 322        /* Detect CB70 without motherboard */
 323        if (!(cpu_system == __frv_mb93091_cb70 && ((*(unsigned short *)0xffc00030) & 0x100))) {
 324                cpu_board1 = __frv_mb93090_mb00;
 325                mb93090_mb00_detected = 1;
 326        }
 327#endif
 328
 329#ifdef CONFIG_FUJITSU_MB93493
 330        cpu_board2 = __frv_mb93493;
 331#endif
 332
 333} /* end detect_mb93091() */
 334#endif
 335
 336/*****************************************************************************/
 337/*
 338 * determine the CPU type and set appropriate parameters
 339 *
 340 * Family     Series      CPU Core    Silicon    Imple  Vers
 341 * ----------------------------------------------------------
 342 * FR-V --+-> FR400 --+-> FR401 --+-> MB93401     02     00 [1]
 343 *        |           |           |
 344 *        |           |           +-> MB93401/A   02     01
 345 *        |           |           |
 346 *        |           |           +-> MB93403     02     02
 347 *        |           |
 348 *        |           +-> FR405 ----> MB93405     04     00
 349 *        |
 350 *        +-> FR450 ----> FR451 ----> MB93451     05     00
 351 *        |
 352 *        +-> FR500 ----> FR501 --+-> MB93501     01     01 [2]
 353 *        |                       |
 354 *        |                       +-> MB93501/A   01     02
 355 *        |
 356 *        +-> FR550 --+-> FR551 ----> MB93555     03     01
 357 *
 358 *  [1] The MB93401 is an obsolete CPU replaced by the MB93401A
 359 *  [2] The MB93501 is an obsolete CPU replaced by the MB93501A
 360 *
 361 * Imple is PSR(Processor Status Register)[31:28].
 362 * Vers is PSR(Processor Status Register)[27:24].
 363 *
 364 * A "Silicon" consists of CPU core and some on-chip peripherals.
 365 */
 366static void __init determine_cpu(void)
 367{
 368        unsigned long hsr0 = __get_HSR(0);
 369        unsigned long psr = __get_PSR();
 370
 371        /* work out what selectable services the CPU supports */
 372        __set_PSR(psr | PSR_EM | PSR_EF | PSR_CM | PSR_NEM);
 373        cpu_psr_all = __get_PSR();
 374        __set_PSR(psr);
 375
 376        __set_HSR(0, hsr0 | HSR0_GRLE | HSR0_GRHE | HSR0_FRLE | HSR0_FRHE);
 377        cpu_hsr0_all = __get_HSR(0);
 378        __set_HSR(0, hsr0);
 379
 380        /* derive other service specs from the CPU type */
 381        cpu_series              = "unknown";
 382        cpu_core                = "unknown";
 383        cpu_silicon             = "unknown";
 384        cpu_mmu                 = "Prot";
 385        cpu_system              = __frv_unknown_system;
 386        clock_cmodes            = NULL;
 387        clock_doubled           = 0;
 388#ifdef CONFIG_PM
 389        clock_bits_settable     = CLOCK_BIT_CM_H | CLOCK_BIT_CM_M | CLOCK_BIT_P0;
 390#endif
 391
 392        switch (PSR_IMPLE(psr)) {
 393        case PSR_IMPLE_FR401:
 394                cpu_series      = "fr400";
 395                cpu_core        = "fr401";
 396                pdm_suspend_mode = HSR0_PDM_PLL_RUN;
 397
 398                switch (PSR_VERSION(psr)) {
 399                case PSR_VERSION_FR401_MB93401:
 400                        cpu_silicon     = "mb93401";
 401                        cpu_system      = __frv_mb93091_cb10;
 402                        clock_cmodes    = clock_cmodes_fr401_fr403;
 403                        clock_doubled   = 1;
 404                        break;
 405                case PSR_VERSION_FR401_MB93401A:
 406                        cpu_silicon     = "mb93401/A";
 407                        cpu_system      = __frv_mb93091_cb11;
 408                        clock_cmodes    = clock_cmodes_fr401_fr403;
 409                        break;
 410                case PSR_VERSION_FR401_MB93403:
 411                        cpu_silicon     = "mb93403";
 412#ifndef CONFIG_MB93093_PDK
 413                        cpu_system      = __frv_mb93091_cb30;
 414#else
 415                        cpu_system      = __frv_mb93093;
 416#endif
 417                        clock_cmodes    = clock_cmodes_fr401_fr403;
 418                        break;
 419                default:
 420                        break;
 421                }
 422                break;
 423
 424        case PSR_IMPLE_FR405:
 425                cpu_series      = "fr400";
 426                cpu_core        = "fr405";
 427                pdm_suspend_mode = HSR0_PDM_PLL_STOP;
 428
 429                switch (PSR_VERSION(psr)) {
 430                case PSR_VERSION_FR405_MB93405:
 431                        cpu_silicon     = "mb93405";
 432                        cpu_system      = __frv_mb93091_cb60;
 433                        clock_cmodes    = clock_cmodes_fr405;
 434#ifdef CONFIG_PM
 435                        clock_bits_settable |= CLOCK_BIT_CMODE;
 436                        clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
 437#endif
 438
 439                        /* the FPGA on the CB70 has extra registers
 440                         * - it has 0x0046 in the VDK_ID FPGA register at 0x1a0, which is
 441                         *   how we tell the difference between it and a CB60
 442                         */
 443                        if (*(volatile unsigned short *) 0xffc001a0 == 0x0046)
 444                                cpu_system = __frv_mb93091_cb70;
 445                        break;
 446                default:
 447                        break;
 448                }
 449                break;
 450
 451        case PSR_IMPLE_FR451:
 452                cpu_series      = "fr450";
 453                cpu_core        = "fr451";
 454                pdm_suspend_mode = HSR0_PDM_PLL_STOP;
 455#ifdef CONFIG_PM
 456                clock_bits_settable |= CLOCK_BIT_CMODE;
 457                clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
 458#endif
 459                switch (PSR_VERSION(psr)) {
 460                case PSR_VERSION_FR451_MB93451:
 461                        cpu_silicon     = "mb93451";
 462                        cpu_mmu         = "Prot, SAT, xSAT, DAT";
 463                        cpu_system      = __frv_mb93091_cb451;
 464                        clock_cmodes    = clock_cmodes_fr405;
 465                        break;
 466                default:
 467                        break;
 468                }
 469                break;
 470
 471        case PSR_IMPLE_FR501:
 472                cpu_series      = "fr500";
 473                cpu_core        = "fr501";
 474                pdm_suspend_mode = HSR0_PDM_PLL_STOP;
 475
 476                switch (PSR_VERSION(psr)) {
 477                case PSR_VERSION_FR501_MB93501:  cpu_silicon = "mb93501";   break;
 478                case PSR_VERSION_FR501_MB93501A: cpu_silicon = "mb93501/A"; break;
 479                default:
 480                        break;
 481                }
 482                break;
 483
 484        case PSR_IMPLE_FR551:
 485                cpu_series      = "fr550";
 486                cpu_core        = "fr551";
 487                pdm_suspend_mode = HSR0_PDM_PLL_RUN;
 488
 489                switch (PSR_VERSION(psr)) {
 490                case PSR_VERSION_FR551_MB93555:
 491                        cpu_silicon     = "mb93555";
 492                        cpu_mmu         = "Prot, SAT";
 493                        cpu_system      = __frv_mb93091_cb41;
 494                        clock_cmodes    = clock_cmodes_fr555;
 495                        clock_doubled   = 1;
 496                        break;
 497                default:
 498                        break;
 499                }
 500                break;
 501
 502        default:
 503                break;
 504        }
 505
 506        printk("- Series:%s CPU:%s Silicon:%s\n",
 507               cpu_series, cpu_core, cpu_silicon);
 508
 509#ifdef CONFIG_MB93091_VDK
 510        detect_mb93091();
 511#endif
 512
 513#if defined(CONFIG_MB93093_PDK) && defined(CONFIG_FUJITSU_MB93493)
 514        cpu_board2 = __frv_mb93493;
 515#endif
 516
 517} /* end determine_cpu() */
 518
 519/*****************************************************************************/
 520/*
 521 * calculate the bus clock speed
 522 */
 523void __pminit determine_clocks(int verbose)
 524{
 525        const struct clock_cmode *mode, *tmode;
 526        unsigned long clkc, psr, quot;
 527
 528        clkc = __get_CLKC();
 529        psr = __get_PSR();
 530
 531        clock_p0_current = !!(clkc & CLKC_P0);
 532        clock_cm_current = clkc & CLKC_CM;
 533        clock_cmode_current = (clkc & CLKC_CMODE) >> CLKC_CMODE_s;
 534
 535        if (verbose)
 536                printk("psr=%08lx hsr0=%08lx clkc=%08lx\n", psr, __get_HSR(0), clkc);
 537
 538        /* the CB70 has some alternative ways of setting the clock speed through switches accessed
 539         * through the FPGA.  */
 540        if (cpu_system == __frv_mb93091_cb70) {
 541                unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
 542
 543                if (clkswr & 0x1000)
 544                        __clkin_clock_speed_HZ = 60000000UL;
 545                else
 546                        __clkin_clock_speed_HZ =
 547                                ((clkswr >> 8) & 0xf) * 10000000 +
 548                                ((clkswr >> 4) & 0xf) * 1000000 +
 549                                ((clkswr     ) & 0xf) * 100000;
 550        }
 551        /* the FR451 is currently fixed at 24MHz */
 552        else if (cpu_system == __frv_mb93091_cb451) {
 553                //__clkin_clock_speed_HZ = 24000000UL; // CB451-FPGA
 554                unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
 555
 556                if (clkswr & 0x1000)
 557                        __clkin_clock_speed_HZ = 60000000UL;
 558                else
 559                        __clkin_clock_speed_HZ =
 560                                ((clkswr >> 8) & 0xf) * 10000000 +
 561                                ((clkswr >> 4) & 0xf) * 1000000 +
 562                                ((clkswr     ) & 0xf) * 100000;
 563        }
 564        /* otherwise determine the clockspeed from VDK or other registers */
 565        else {
 566                __clkin_clock_speed_HZ = __get_CLKIN();
 567        }
 568
 569        /* look up the appropriate clock relationships table entry */
 570        mode = &undef_clock_cmode;
 571        if (clock_cmodes) {
 572                tmode = &clock_cmodes[(clkc & CLKC_CMODE) >> CLKC_CMODE_s];
 573                if (tmode->xbus)
 574                        mode = tmode;
 575        }
 576
 577#define CLOCK(SRC,RATIO) ((SRC) * (((RATIO) >> 4) & 0x0f) / ((RATIO) & 0x0f))
 578
 579        if (clock_doubled)
 580                __clkin_clock_speed_HZ <<= 1;
 581
 582        __ext_bus_clock_speed_HZ        = CLOCK(__clkin_clock_speed_HZ, mode->xbus);
 583        __sdram_clock_speed_HZ          = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
 584        __dsu_clock_speed_HZ            = CLOCK(__clkin_clock_speed_HZ, mode->dsu);
 585
 586        switch (clkc & CLKC_CM) {
 587        case 0: /* High */
 588                __core_bus_clock_speed_HZ       = CLOCK(__clkin_clock_speed_HZ, mode->corebus);
 589                __core_clock_speed_HZ           = CLOCK(__clkin_clock_speed_HZ, mode->core);
 590                break;
 591        case 1: /* Medium */
 592                __core_bus_clock_speed_HZ       = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
 593                __core_clock_speed_HZ           = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
 594                break;
 595        case 2: /* Low; not supported */
 596        case 3: /* UNDEF */
 597                printk("Unsupported CLKC CM %ld\n", clkc & CLKC_CM);
 598                panic("Bye");
 599        }
 600
 601        __res_bus_clock_speed_HZ = __ext_bus_clock_speed_HZ;
 602        if (clkc & CLKC_P0)
 603                __res_bus_clock_speed_HZ >>= 1;
 604
 605        if (verbose) {
 606                printk("CLKIN: %lu.%3.3luMHz\n",
 607                       __clkin_clock_speed_HZ / 1000000,
 608                       (__clkin_clock_speed_HZ / 1000) % 1000);
 609
 610                printk("CLKS:"
 611                       " ext=%luMHz res=%luMHz sdram=%luMHz cbus=%luMHz core=%luMHz dsu=%luMHz\n",
 612                       __ext_bus_clock_speed_HZ / 1000000,
 613                       __res_bus_clock_speed_HZ / 1000000,
 614                       __sdram_clock_speed_HZ / 1000000,
 615                       __core_bus_clock_speed_HZ / 1000000,
 616                       __core_clock_speed_HZ / 1000000,
 617                       __dsu_clock_speed_HZ / 1000000
 618                       );
 619        }
 620
 621        /* calculate the number of __delay() loop iterations per sec (2 insn loop) */
 622        __delay_loops_MHz = __core_clock_speed_HZ / (1000000 * 2);
 623
 624        /* set the serial prescaler */
 625        __serial_clock_speed_HZ = __res_bus_clock_speed_HZ;
 626        quot = 1;
 627        while (__serial_clock_speed_HZ / quot / 16 / 65536 > 3000)
 628                quot += 1;
 629
 630        /* double the divisor if P0 is clear, so that if/when P0 is set, it's still achievable
 631         * - we have to be careful - dividing too much can mean we can't get 115200 baud
 632         */
 633        if (__serial_clock_speed_HZ > 32000000 && !(clkc & CLKC_P0))
 634                quot <<= 1;
 635
 636        __serial_clock_speed_HZ /= quot;
 637        __frv_uart0.uartclk = __serial_clock_speed_HZ;
 638        __frv_uart1.uartclk = __serial_clock_speed_HZ;
 639
 640        if (verbose)
 641                printk("      uart=%luMHz\n", __serial_clock_speed_HZ / 1000000 * quot);
 642
 643        while (!(__get_UART0_LSR() & UART_LSR_TEMT))
 644                continue;
 645
 646        while (!(__get_UART1_LSR() & UART_LSR_TEMT))
 647                continue;
 648
 649        __set_UCPVR(quot);
 650        __set_UCPSR(0);
 651} /* end determine_clocks() */
 652
 653/*****************************************************************************/
 654/*
 655 * reserve some DMA consistent memory
 656 */
 657#ifdef CONFIG_RESERVE_DMA_COHERENT
 658static void __init reserve_dma_coherent(void)
 659{
 660        unsigned long ampr;
 661
 662        /* find the first non-kernel memory tile and steal it */
 663#define __steal_AMPR(r)                                         \
 664        if (__get_DAMPR(r) & xAMPRx_V) {                        \
 665                ampr = __get_DAMPR(r);                          \
 666                __set_DAMPR(r, ampr | xAMPRx_S | xAMPRx_C);     \
 667                __set_IAMPR(r, 0);                              \
 668                goto found;                                     \
 669        }
 670
 671        __steal_AMPR(1);
 672        __steal_AMPR(2);
 673        __steal_AMPR(3);
 674        __steal_AMPR(4);
 675        __steal_AMPR(5);
 676        __steal_AMPR(6);
 677
 678        if (PSR_IMPLE(__get_PSR()) == PSR_IMPLE_FR551) {
 679                __steal_AMPR(7);
 680                __steal_AMPR(8);
 681                __steal_AMPR(9);
 682                __steal_AMPR(10);
 683                __steal_AMPR(11);
 684                __steal_AMPR(12);
 685                __steal_AMPR(13);
 686                __steal_AMPR(14);
 687        }
 688
 689        /* unable to grant any DMA consistent memory */
 690        printk("No DMA consistent memory reserved\n");
 691        return;
 692
 693 found:
 694        dma_coherent_mem_start = ampr & xAMPRx_PPFN;
 695        ampr &= xAMPRx_SS;
 696        ampr >>= 4;
 697        ampr = 1 << (ampr - 3 + 20);
 698        dma_coherent_mem_end = dma_coherent_mem_start + ampr;
 699
 700        printk("DMA consistent memory reserved %lx-%lx\n",
 701               dma_coherent_mem_start, dma_coherent_mem_end);
 702
 703} /* end reserve_dma_coherent() */
 704#endif
 705
 706/*****************************************************************************/
 707/*
 708 * calibrate the delay loop
 709 */
 710void calibrate_delay(void)
 711{
 712        loops_per_jiffy = __delay_loops_MHz * (1000000 / HZ);
 713
 714        printk("Calibrating delay loop... %lu.%02lu BogoMIPS\n",
 715               loops_per_jiffy / (500000 / HZ),
 716               (loops_per_jiffy / (5000 / HZ)) % 100);
 717
 718} /* end calibrate_delay() */
 719
 720/*****************************************************************************/
 721/*
 722 * look through the command line for some things we need to know immediately
 723 */
 724static void __init parse_cmdline_early(char *cmdline)
 725{
 726        if (!cmdline)
 727                return;
 728
 729        while (*cmdline) {
 730                if (*cmdline == ' ')
 731                        cmdline++;
 732
 733                /* "mem=XXX[kKmM]" sets SDRAM size to <mem>, overriding the value we worked
 734                 * out from the SDRAM controller mask register
 735                 */
 736                if (!strncmp(cmdline, "mem=", 4)) {
 737                        unsigned long long mem_size;
 738
 739                        mem_size = memparse(cmdline + 4, &cmdline);
 740                        memory_end = memory_start + mem_size;
 741                }
 742
 743                while (*cmdline && *cmdline != ' ')
 744                        cmdline++;
 745        }
 746
 747} /* end parse_cmdline_early() */
 748
 749/*****************************************************************************/
 750/*
 751 *
 752 */
 753void __init setup_arch(char **cmdline_p)
 754{
 755#ifdef CONFIG_MMU
 756        printk("Linux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
 757#else
 758        printk("uClinux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
 759#endif
 760
 761        memcpy(boot_command_line, redboot_command_line, COMMAND_LINE_SIZE);
 762
 763        determine_cpu();
 764        determine_clocks(1);
 765
 766        /* For printk-directly-beats-on-serial-hardware hack */
 767        console_set_baud(115200);
 768#ifdef CONFIG_GDBSTUB
 769        gdbstub_set_baud(115200);
 770#endif
 771
 772#ifdef CONFIG_RESERVE_DMA_COHERENT
 773        reserve_dma_coherent();
 774#endif
 775        dump_memory_map();
 776
 777#ifdef CONFIG_MB93090_MB00
 778        if (mb93090_mb00_detected)
 779                mb93090_display();
 780#endif
 781
 782        /* register those serial ports that are available */
 783#ifdef CONFIG_FRV_ONCPU_SERIAL
 784#ifndef CONFIG_GDBSTUB_UART0
 785        __reg(UART0_BASE + UART_IER * 8) = 0;
 786        early_serial_setup(&__frv_uart0);
 787#endif
 788#ifndef CONFIG_GDBSTUB_UART1
 789        __reg(UART1_BASE + UART_IER * 8) = 0;
 790        early_serial_setup(&__frv_uart1);
 791#endif
 792#endif
 793
 794        /* deal with the command line - RedBoot may have passed one to the kernel */
 795        memcpy(command_line, boot_command_line, sizeof(command_line));
 796        *cmdline_p = &command_line[0];
 797        parse_cmdline_early(command_line);
 798
 799        /* set up the memory description
 800         * - by now the stack is part of the init task */
 801        printk("Memory %08lx-%08lx\n", memory_start, memory_end);
 802
 803        BUG_ON(memory_start == memory_end);
 804
 805        init_mm.start_code = (unsigned long) _stext;
 806        init_mm.end_code = (unsigned long) _etext;
 807        init_mm.end_data = (unsigned long) _edata;
 808#if 0 /* DAVIDM - don't set brk just incase someone decides to use it */
 809        init_mm.brk = (unsigned long) &_end;
 810#else
 811        init_mm.brk = (unsigned long) 0;
 812#endif
 813
 814#ifdef DEBUG
 815        printk("KERNEL -> TEXT=0x%p-0x%p DATA=0x%p-0x%p BSS=0x%p-0x%p\n",
 816               _stext, _etext, _sdata, _edata, __bss_start, __bss_stop);
 817#endif
 818
 819#ifdef CONFIG_VT
 820#if defined(CONFIG_VGA_CONSOLE)
 821        conswitchp = &vga_con;
 822#elif defined(CONFIG_DUMMY_CONSOLE)
 823        conswitchp = &dummy_con;
 824#endif
 825#endif
 826
 827#ifdef CONFIG_MMU
 828        setup_linux_memory();
 829#else
 830        setup_uclinux_memory();
 831#endif
 832
 833        /* get kmalloc into gear */
 834        paging_init();
 835
 836        /* init DMA */
 837        frv_dma_init();
 838#ifdef DEBUG
 839        printk("Done setup_arch\n");
 840#endif
 841
 842        /* start the decrement timer running */
 843//      asm volatile("movgs %0,timerd" :: "r"(10000000));
 844//      __set_HSR(0, __get_HSR(0) | HSR0_ETMD);
 845
 846} /* end setup_arch() */
 847
 848#if 0
 849/*****************************************************************************/
 850/*
 851 *
 852 */
 853static int setup_arch_serial(void)
 854{
 855        /* register those serial ports that are available */
 856#ifndef CONFIG_GDBSTUB_UART0
 857        early_serial_setup(&__frv_uart0);
 858#endif
 859#ifndef CONFIG_GDBSTUB_UART1
 860        early_serial_setup(&__frv_uart1);
 861#endif
 862
 863        return 0;
 864} /* end setup_arch_serial() */
 865
 866late_initcall(setup_arch_serial);
 867#endif
 868
 869/*****************************************************************************/
 870/*
 871 * set up the memory map for normal MMU linux
 872 */
 873#ifdef CONFIG_MMU
 874static void __init setup_linux_memory(void)
 875{
 876        unsigned long bootmap_size, low_top_pfn, kstart, kend, high_mem;
 877        unsigned long physpages;
 878
 879        kstart  = (unsigned long) &__kernel_image_start - PAGE_OFFSET;
 880        kend    = (unsigned long) &__kernel_image_end - PAGE_OFFSET;
 881
 882        kstart = kstart & PAGE_MASK;
 883        kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
 884
 885        /* give all the memory to the bootmap allocator,  tell it to put the
 886         * boot mem_map immediately following the kernel image
 887         */
 888        bootmap_size = init_bootmem_node(NODE_DATA(0),
 889                                         kend >> PAGE_SHIFT,            /* map addr */
 890                                         memory_start >> PAGE_SHIFT,    /* start of RAM */
 891                                         memory_end >> PAGE_SHIFT       /* end of RAM */
 892                                         );
 893
 894        /* pass the memory that the kernel can immediately use over to the bootmem allocator */
 895        max_mapnr = physpages = (memory_end - memory_start) >> PAGE_SHIFT;
 896        low_top_pfn = (KERNEL_LOWMEM_END - KERNEL_LOWMEM_START) >> PAGE_SHIFT;
 897        high_mem = 0;
 898
 899        if (physpages > low_top_pfn) {
 900#ifdef CONFIG_HIGHMEM
 901                high_mem = physpages - low_top_pfn;
 902#else
 903                max_mapnr = physpages = low_top_pfn;
 904#endif
 905        }
 906        else {
 907                low_top_pfn = physpages;
 908        }
 909
 910        min_low_pfn = memory_start >> PAGE_SHIFT;
 911        max_low_pfn = low_top_pfn;
 912        max_pfn = memory_end >> PAGE_SHIFT;
 913
 914        num_mappedpages = low_top_pfn;
 915
 916        printk(KERN_NOTICE "%ldMB LOWMEM available.\n", low_top_pfn >> (20 - PAGE_SHIFT));
 917
 918        free_bootmem(memory_start, low_top_pfn << PAGE_SHIFT);
 919
 920#ifdef CONFIG_HIGHMEM
 921        if (high_mem)
 922                printk(KERN_NOTICE "%ldMB HIGHMEM available.\n", high_mem >> (20 - PAGE_SHIFT));
 923#endif
 924
 925        /* take back the memory occupied by the kernel image and the bootmem alloc map */
 926        reserve_bootmem(kstart, kend - kstart + bootmap_size,
 927                        BOOTMEM_DEFAULT);
 928
 929        /* reserve the memory occupied by the initial ramdisk */
 930#ifdef CONFIG_BLK_DEV_INITRD
 931        if (LOADER_TYPE && INITRD_START) {
 932                if (INITRD_START + INITRD_SIZE <= (low_top_pfn << PAGE_SHIFT)) {
 933                        reserve_bootmem(INITRD_START, INITRD_SIZE,
 934                                        BOOTMEM_DEFAULT);
 935                        initrd_start = INITRD_START + PAGE_OFFSET;
 936                        initrd_end = initrd_start + INITRD_SIZE;
 937                }
 938                else {
 939                        printk(KERN_ERR
 940                               "initrd extends beyond end of memory (0x%08lx > 0x%08lx)\n"
 941                               "disabling initrd\n",
 942                               INITRD_START + INITRD_SIZE,
 943                               low_top_pfn << PAGE_SHIFT);
 944                        initrd_start = 0;
 945                }
 946        }
 947#endif
 948
 949} /* end setup_linux_memory() */
 950#endif
 951
 952/*****************************************************************************/
 953/*
 954 * set up the memory map for uClinux
 955 */
 956#ifndef CONFIG_MMU
 957static void __init setup_uclinux_memory(void)
 958{
 959#ifdef CONFIG_PROTECT_KERNEL
 960        unsigned long dampr;
 961#endif
 962        unsigned long kend;
 963        int bootmap_size;
 964
 965        kend = (unsigned long) &__kernel_image_end;
 966        kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
 967
 968        /* give all the memory to the bootmap allocator,  tell it to put the
 969         * boot mem_map immediately following the kernel image
 970         */
 971        bootmap_size = init_bootmem_node(NODE_DATA(0),
 972                                         kend >> PAGE_SHIFT,            /* map addr */
 973                                         memory_start >> PAGE_SHIFT,    /* start of RAM */
 974                                         memory_end >> PAGE_SHIFT       /* end of RAM */
 975                                         );
 976
 977        /* free all the usable memory */
 978        free_bootmem(memory_start, memory_end - memory_start);
 979
 980        high_memory = (void *) (memory_end & PAGE_MASK);
 981        max_mapnr = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
 982
 983        min_low_pfn = memory_start >> PAGE_SHIFT;
 984        max_low_pfn = memory_end >> PAGE_SHIFT;
 985        max_pfn = max_low_pfn;
 986
 987        /* now take back the bits the core kernel is occupying */
 988#ifndef CONFIG_PROTECT_KERNEL
 989        reserve_bootmem(kend, bootmap_size, BOOTMEM_DEFAULT);
 990        reserve_bootmem((unsigned long) &__kernel_image_start,
 991                        kend - (unsigned long) &__kernel_image_start,
 992                        BOOTMEM_DEFAULT);
 993
 994#else
 995        dampr = __get_DAMPR(0);
 996        dampr &= xAMPRx_SS;
 997        dampr = (dampr >> 4) + 17;
 998        dampr = 1 << dampr;
 999
1000        reserve_bootmem(__get_DAMPR(0) & xAMPRx_PPFN, dampr, BOOTMEM_DEFAULT);
1001#endif
1002
1003        /* reserve some memory to do uncached DMA through if requested */
1004#ifdef CONFIG_RESERVE_DMA_COHERENT
1005        if (dma_coherent_mem_start)
1006                reserve_bootmem(dma_coherent_mem_start,
1007                                dma_coherent_mem_end - dma_coherent_mem_start,
1008                                BOOTMEM_DEFAULT);
1009#endif
1010
1011} /* end setup_uclinux_memory() */
1012#endif
1013
1014/*****************************************************************************/
1015/*
1016 * get CPU information for use by procfs
1017 */
1018static int show_cpuinfo(struct seq_file *m, void *v)
1019{
1020        const char *gr, *fr, *fm, *fp, *cm, *nem, *ble;
1021#ifdef CONFIG_PM
1022        const char *sep;
1023#endif
1024
1025        gr  = cpu_hsr0_all & HSR0_GRHE  ? "gr0-63"      : "gr0-31";
1026        fr  = cpu_hsr0_all & HSR0_FRHE  ? "fr0-63"      : "fr0-31";
1027        fm  = cpu_psr_all  & PSR_EM     ? ", Media"     : "";
1028        fp  = cpu_psr_all  & PSR_EF     ? ", FPU"       : "";
1029        cm  = cpu_psr_all  & PSR_CM     ? ", CCCR"      : "";
1030        nem = cpu_psr_all  & PSR_NEM    ? ", NE"        : "";
1031        ble = cpu_psr_all  & PSR_BE     ? "BE"          : "LE";
1032
1033        seq_printf(m,
1034                   "CPU-Series:\t%s\n"
1035                   "CPU-Core:\t%s, %s, %s%s%s\n"
1036                   "CPU:\t\t%s\n"
1037                   "MMU:\t\t%s\n"
1038                   "FP-Media:\t%s%s%s\n"
1039                   "System:\t\t%s",
1040                   cpu_series,
1041                   cpu_core, gr, ble, cm, nem,
1042                   cpu_silicon,
1043                   cpu_mmu,
1044                   fr, fm, fp,
1045                   cpu_system);
1046
1047        if (cpu_board1)
1048                seq_printf(m, ", %s", cpu_board1);
1049
1050        if (cpu_board2)
1051                seq_printf(m, ", %s", cpu_board2);
1052
1053        seq_printf(m, "\n");
1054
1055#ifdef CONFIG_PM
1056        seq_printf(m, "PM-Controls:");
1057        sep = "\t";
1058
1059        if (clock_bits_settable & CLOCK_BIT_CMODE) {
1060                seq_printf(m, "%scmode=0x%04hx", sep, clock_cmodes_permitted);
1061                sep = ", ";
1062        }
1063
1064        if (clock_bits_settable & CLOCK_BIT_CM) {
1065                seq_printf(m, "%scm=0x%lx", sep, clock_bits_settable & CLOCK_BIT_CM);
1066                sep = ", ";
1067        }
1068
1069        if (clock_bits_settable & CLOCK_BIT_P0) {
1070                seq_printf(m, "%sp0=0x3", sep);
1071                sep = ", ";
1072        }
1073
1074        seq_printf(m, "%ssuspend=0x22\n", sep);
1075#endif
1076
1077        seq_printf(m,
1078                   "PM-Status:\tcmode=%d, cm=%d, p0=%d\n",
1079                   clock_cmode_current, clock_cm_current, clock_p0_current);
1080
1081#define print_clk(TAG, VAR) \
1082        seq_printf(m, "Clock-" TAG ":\t%lu.%2.2lu MHz\n", VAR / 1000000, (VAR / 10000) % 100)
1083
1084        print_clk("In",    __clkin_clock_speed_HZ);
1085        print_clk("Core",  __core_clock_speed_HZ);
1086        print_clk("SDRAM", __sdram_clock_speed_HZ);
1087        print_clk("CBus",  __core_bus_clock_speed_HZ);
1088        print_clk("Res",   __res_bus_clock_speed_HZ);
1089        print_clk("Ext",   __ext_bus_clock_speed_HZ);
1090        print_clk("DSU",   __dsu_clock_speed_HZ);
1091
1092        seq_printf(m,
1093                   "BogoMips:\t%lu.%02lu\n",
1094                   (loops_per_jiffy * HZ) / 500000, ((loops_per_jiffy * HZ) / 5000) % 100);
1095
1096        return 0;
1097} /* end show_cpuinfo() */
1098
1099static void *c_start(struct seq_file *m, loff_t *pos)
1100{
1101        return *pos < NR_CPUS ? (void *) 0x12345678 : NULL;
1102}
1103
1104static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1105{
1106        ++*pos;
1107        return c_start(m, pos);
1108}
1109
1110static void c_stop(struct seq_file *m, void *v)
1111{
1112}
1113
1114const struct seq_operations cpuinfo_op = {
1115        .start  = c_start,
1116        .next   = c_next,
1117        .stop   = c_stop,
1118        .show   = show_cpuinfo,
1119};
1120
1121void arch_gettod(int *year, int *mon, int *day, int *hour,
1122                 int *min, int *sec)
1123{
1124        *year = *mon = *day = *hour = *min = *sec = 0;
1125}
1126
1127/*****************************************************************************/
1128/*
1129 *
1130 */
1131#ifdef CONFIG_MB93090_MB00
1132static void __init mb93090_sendlcdcmd(uint32_t cmd)
1133{
1134        unsigned long base = __addr_LCD();
1135        int loop;
1136
1137        /* request reading of the busy flag */
1138        __set_LCD(base, LCD_CMD_READ_BUSY);
1139        __set_LCD(base, LCD_CMD_READ_BUSY & ~LCD_E);
1140
1141        /* wait for the busy flag to become clear */
1142        for (loop = 10000; loop > 0; loop--)
1143                if (!(__get_LCD(base) & 0x80))
1144                        break;
1145
1146        /* send the command */
1147        __set_LCD(base, cmd);
1148        __set_LCD(base, cmd & ~LCD_E);
1149
1150} /* end mb93090_sendlcdcmd() */
1151
1152/*****************************************************************************/
1153/*
1154 * write to the MB93090 LEDs and LCD
1155 */
1156static void __init mb93090_display(void)
1157{
1158        const char *p;
1159
1160        __set_LEDS(0);
1161
1162        /* set up the LCD */
1163        mb93090_sendlcdcmd(LCD_CMD_CLEAR);
1164        mb93090_sendlcdcmd(LCD_CMD_FUNCSET(1,1,0));
1165        mb93090_sendlcdcmd(LCD_CMD_ON(0,0));
1166        mb93090_sendlcdcmd(LCD_CMD_HOME);
1167
1168        mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(0));
1169        for (p = mb93090_banner; *p; p++)
1170                mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
1171
1172        mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(64));
1173        for (p = mb93090_version; *p; p++)
1174                mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
1175
1176} /* end mb93090_display() */
1177
1178#endif // CONFIG_MB93090_MB00
1179