1/* 2 * asm/metag_mem.h 3 * 4 * Copyright (C) 2000-2007, 2012 Imagination Technologies. 5 * 6 * This program is free software; you can redistribute it and/or modify it under 7 * the terms of the GNU General Public License version 2 as published by the 8 * Free Software Foundation. 9 * 10 * Various defines for Meta (memory-mapped) registers. 11 */ 12 13#ifndef _ASM_METAG_MEM_H_ 14#define _ASM_METAG_MEM_H_ 15 16/***************************************************************************** 17 * META MEMORY MAP LINEAR ADDRESS VALUES 18 ****************************************************************************/ 19/* 20 * COMMON MEMORY MAP 21 * ----------------- 22 */ 23 24#define LINSYSTEM_BASE 0x00200000 25#define LINSYSTEM_LIMIT 0x07FFFFFF 26 27/* Linear cache flush now implemented via DCACHE instruction. These defines 28 related to a special region that used to exist for achieving cache flushes. 29 */ 30#define LINSYSLFLUSH_S 0 31 32#define LINSYSRES0_BASE 0x00200000 33#define LINSYSRES0_LIMIT 0x01FFFFFF 34 35#define LINSYSCUSTOM_BASE 0x02000000 36#define LINSYSCUSTOM_LIMIT 0x02FFFFFF 37 38#define LINSYSEXPAND_BASE 0x03000000 39#define LINSYSEXPAND_LIMIT 0x03FFFFFF 40 41#define LINSYSEVENT_BASE 0x04000000 42#define LINSYSEVENT_WR_ATOMIC_UNLOCK 0x04000000 43#define LINSYSEVENT_WR_ATOMIC_LOCK 0x04000040 44#define LINSYSEVENT_WR_CACHE_DISABLE 0x04000080 45#define LINSYSEVENT_WR_CACHE_ENABLE 0x040000C0 46#define LINSYSEVENT_WR_COMBINE_FLUSH 0x04000100 47#define LINSYSEVENT_WR_FENCE 0x04000140 48#define LINSYSEVENT_LIMIT 0x04000FFF 49 50#define LINSYSCFLUSH_BASE 0x04400000 51#define LINSYSCFLUSH_DCACHE_LINE 0x04400000 52#define LINSYSCFLUSH_ICACHE_LINE 0x04500000 53#define LINSYSCFLUSH_MMCU 0x04700000 54#ifndef METAC_1_2 55#define LINSYSCFLUSH_TxMMCU_BASE 0x04700020 56#define LINSYSCFLUSH_TxMMCU_STRIDE 0x00000008 57#endif 58#define LINSYSCFLUSH_ADDR_BITS 0x000FFFFF 59#define LINSYSCFLUSH_ADDR_S 0 60#define LINSYSCFLUSH_LIMIT 0x047FFFFF 61 62#define LINSYSCTRL_BASE 0x04800000 63#define LINSYSCTRL_LIMIT 0x04FFFFFF 64 65#define LINSYSMTABLE_BASE 0x05000000 66#define LINSYSMTABLE_LIMIT 0x05FFFFFF 67 68#define LINSYSDIRECT_BASE 0x06000000 69#define LINSYSDIRECT_LIMIT 0x07FFFFFF 70 71#define LINLOCAL_BASE 0x08000000 72#define LINLOCAL_LIMIT 0x7FFFFFFF 73 74#define LINCORE_BASE 0x80000000 75#define LINCORE_LIMIT 0x87FFFFFF 76 77#define LINCORE_CODE_BASE 0x80000000 78#define LINCORE_CODE_LIMIT 0x81FFFFFF 79 80#define LINCORE_DATA_BASE 0x82000000 81#define LINCORE_DATA_LIMIT 0x83FFFFFF 82 83 84/* The core can support locked icache lines in this region */ 85#define LINCORE_ICACHE_BASE 0x84000000 86#define LINCORE_ICACHE_LIMIT 0x85FFFFFF 87 88/* The core can support locked dcache lines in this region */ 89#define LINCORE_DCACHE_BASE 0x86000000 90#define LINCORE_DCACHE_LIMIT 0x87FFFFFF 91 92#define LINGLOBAL_BASE 0x88000000 93#define LINGLOBAL_LIMIT 0xFFFDFFFF 94 95/* 96 * CHIP Core Register Map 97 * ---------------------- 98 */ 99#define CORE_HWBASE 0x04800000 100#define PRIV_HWBASE 0x04810000 101#define TRIG_HWBASE 0x04820000 102#define SYSC_HWBASE 0x04830000 103 104/***************************************************************************** 105 * INTER-THREAD KICK REGISTERS FOR SOFTWARE EVENT GENERATION 106 ****************************************************************************/ 107/* 108 * These values define memory mapped registers that can be used to supply 109 * kicks to threads that service arbitrary software events. 110 */ 111 112#define T0KICK 0x04800800 /* Background kick 0 */ 113#define TXXKICK_MAX 0xFFFF /* Maximum kicks */ 114#define TnXKICK_STRIDE 0x00001000 /* Thread scale value */ 115#define TnXKICK_STRIDE_S 12 116#define T0KICKI 0x04800808 /* Interrupt kick 0 */ 117#define TXIKICK_OFFSET 0x00000008 /* Int level offset value */ 118#define T1KICK 0x04801800 /* Background kick 1 */ 119#define T1KICKI 0x04801808 /* Interrupt kick 1 */ 120#define T2KICK 0x04802800 /* Background kick 2 */ 121#define T2KICKI 0x04802808 /* Interrupt kick 2 */ 122#define T3KICK 0x04803800 /* Background kick 3 */ 123#define T3KICKI 0x04803808 /* Interrupt kick 3 */ 124 125/***************************************************************************** 126 * GLOBAL REGISTER ACCESS RESOURCES 127 ****************************************************************************/ 128/* 129 * These values define memory mapped registers that allow access to the 130 * internal state of all threads in order to allow global set-up of thread 131 * state and external handling of thread events, errors, or debugging. 132 * 133 * The actual unit and register index values needed to access individul 134 * registers are chip specific see - METAC_TXUXX_VALUES in metac_x_y.h. 135 * However two C array initialisers TXUXX_MASKS and TGUXX_MASKS will always be 136 * defined to allow arbitrary loading, display, and saving of all valid 137 * register states without detailed knowledge of their purpose - TXUXX sets 138 * bits for all valid registers and TGUXX sets bits for the sub-set which are 139 * global. 140 */ 141 142#define T0UCTREG0 0x04800000 /* Access to all CT regs */ 143#define TnUCTRX_STRIDE 0x00001000 /* Thread scale value */ 144#define TXUCTREGn_STRIDE 0x00000008 /* Register scale value */ 145 146#define TXUXXRXDT 0x0480FFF0 /* Data to/from any threads reg */ 147#define TXUXXRXRQ 0x0480FFF8 148#define TXUXXRXRQ_DREADY_BIT 0x80000000 /* Poll for done */ 149#define TXUXXRXRQ_DSPEXT_BIT 0x00020000 /* Addr DSP Regs */ 150#define TXUXXRXRQ_RDnWR_BIT 0x00010000 /* Set for read */ 151#define TXUXXRXRQ_TX_BITS 0x00003000 /* Thread number */ 152#define TXUXXRXRQ_TX_S 12 153#define TXUXXRXRQ_RX_BITS 0x000001F0 /* Register num */ 154#define TXUXXRXRQ_RX_S 4 155#define TXUXXRXRQ_DSPRARD0 0 /* DSP RAM A Read Pointer 0 */ 156#define TXUXXRXRQ_DSPRARD1 1 /* DSP RAM A Read Pointer 1 */ 157#define TXUXXRXRQ_DSPRAWR0 2 /* DSP RAM A Write Pointer 0 */ 158#define TXUXXRXRQ_DSPRAWR2 3 /* DSP RAM A Write Pointer 1 */ 159#define TXUXXRXRQ_DSPRBRD0 4 /* DSP RAM B Read Pointer 0 */ 160#define TXUXXRXRQ_DSPRBRD1 5 /* DSP RAM B Read Pointer 1 */ 161#define TXUXXRXRQ_DSPRBWR0 6 /* DSP RAM B Write Pointer 0 */ 162#define TXUXXRXRQ_DSPRBWR1 7 /* DSP RAM B Write Pointer 1 */ 163#define TXUXXRXRQ_DSPRARINC0 8 /* DSP RAM A Read Increment 0 */ 164#define TXUXXRXRQ_DSPRARINC1 9 /* DSP RAM A Read Increment 1 */ 165#define TXUXXRXRQ_DSPRAWINC0 10 /* DSP RAM A Write Increment 0 */ 166#define TXUXXRXRQ_DSPRAWINC1 11 /* DSP RAM A Write Increment 1 */ 167#define TXUXXRXRQ_DSPRBRINC0 12 /* DSP RAM B Read Increment 0 */ 168#define TXUXXRXRQ_DSPRBRINC1 13 /* DSP RAM B Read Increment 1 */ 169#define TXUXXRXRQ_DSPRBWINC0 14 /* DSP RAM B Write Increment 0 */ 170#define TXUXXRXRQ_DSPRBWINC1 15 /* DSP RAM B Write Increment 1 */ 171 172#define TXUXXRXRQ_ACC0L0 16 /* Accumulator 0 bottom 32-bits */ 173#define TXUXXRXRQ_ACC1L0 17 /* Accumulator 1 bottom 32-bits */ 174#define TXUXXRXRQ_ACC2L0 18 /* Accumulator 2 bottom 32-bits */ 175#define TXUXXRXRQ_ACC3L0 19 /* Accumulator 3 bottom 32-bits */ 176#define TXUXXRXRQ_ACC0HI 20 /* Accumulator 0 top 8-bits */ 177#define TXUXXRXRQ_ACC1HI 21 /* Accumulator 1 top 8-bits */ 178#define TXUXXRXRQ_ACC2HI 22 /* Accumulator 2 top 8-bits */ 179#define TXUXXRXRQ_ACC3HI 23 /* Accumulator 3 top 8-bits */ 180#define TXUXXRXRQ_UXX_BITS 0x0000000F /* Unit number */ 181#define TXUXXRXRQ_UXX_S 0 182 183/***************************************************************************** 184 * PRIVILEGE CONTROL VALUES FOR MEMORY MAPPED RESOURCES 185 ****************************************************************************/ 186/* 187 * These values define memory mapped registers that give control over and 188 * the privilege required to access other memory mapped resources. These 189 * registers themselves always require privilege to update them. 190 */ 191 192#define TXPRIVREG_STRIDE 0x8 /* Delta between per-thread regs */ 193#define TXPRIVREG_STRIDE_S 3 194 195/* 196 * Each bit 0 to 15 defines privilege required to access internal register 197 * regions 0x04800000 to 0x048FFFFF in 64k chunks 198 */ 199#define T0PIOREG 0x04810100 200#define T1PIOREG 0x04810108 201#define T2PIOREG 0x04810110 202#define T3PIOREG 0x04810118 203 204/* 205 * Each bit 0 to 31 defines privilege required to use the pair of 206 * system events implemented as writee in the regions 0x04000000 to 207 * 0x04000FFF in 2*64 byte chunks. 208 */ 209#define T0PSYREG 0x04810180 210#define T1PSYREG 0x04810188 211#define T2PSYREG 0x04810190 212#define T3PSYREG 0x04810198 213 214/* 215 * CHIP PRIV CONTROLS 216 * ------------------ 217 */ 218 219/* The TXPIOREG register holds a bit mask directly mappable to 220 corresponding addresses in the range 0x04800000 to 049FFFFF */ 221#define TXPIOREG_ADDR_BITS 0x1F0000 /* Up to 32x64K bytes */ 222#define TXPIOREG_ADDR_S 16 223 224/* Hence based on the _HWBASE values ... */ 225#define TXPIOREG_CORE_BIT (1<<((0x04800000>>16)&0x1F)) 226#define TXPIOREG_PRIV_BIT (1<<((0x04810000>>16)&0x1F)) 227#define TXPIOREG_TRIG_BIT (1<<((0x04820000>>16)&0x1F)) 228#define TXPIOREG_SYSC_BIT (1<<((0x04830000>>16)&0x1F)) 229 230#define TXPIOREG_WRC_BIT 0x00080000 /* Wr combiner reg priv */ 231#define TXPIOREG_LOCALBUS_RW_BIT 0x00040000 /* Local bus rd/wr priv */ 232#define TXPIOREG_SYSREGBUS_RD_BIT 0x00020000 /* Sys reg bus write priv */ 233#define TXPIOREG_SYSREGBUS_WR_BIT 0x00010000 /* Sys reg bus read priv */ 234 235/* CORE region privilege controls */ 236#define T0PRIVCORE 0x04800828 237#define TXPRIVCORE_TXBKICK_BIT 0x001 /* Background kick priv */ 238#define TXPRIVCORE_TXIKICK_BIT 0x002 /* Interrupt kick priv */ 239#define TXPRIVCORE_TXAMAREGX_BIT 0x004 /* TXAMAREG4|5|6 priv */ 240#define TnPRIVCORE_STRIDE 0x00001000 241 242#define T0PRIVSYSR 0x04810000 243#define TnPRIVSYSR_STRIDE 0x00000008 244#define TnPRIVSYSR_STRIDE_S 3 245#define TXPRIVSYSR_CFLUSH_BIT 0x01 246#define TXPRIVSYSR_MTABLE_BIT 0x02 247#define TXPRIVSYSR_DIRECT_BIT 0x04 248#ifdef METAC_1_2 249#define TXPRIVSYSR_ALL_BITS 0x07 250#else 251#define TXPRIVSYSR_CORE_BIT 0x08 252#define TXPRIVSYSR_CORECODE_BIT 0x10 253#define TXPRIVSYSR_ALL_BITS 0x1F 254#endif 255#define T1PRIVSYSR 0x04810008 256#define T2PRIVSYSR 0x04810010 257#define T3PRIVSYSR 0x04810018 258 259/***************************************************************************** 260 * H/W TRIGGER STATE/LEVEL REGISTERS AND H/W TRIGGER VECTORS 261 ****************************************************************************/ 262/* 263 * These values define memory mapped registers that give control over and 264 * the state of hardware trigger sources both external to the META processor 265 * and internal to it. 266 */ 267 268#define HWSTATMETA 0x04820000 /* Hardware status/clear META trig */ 269#define HWSTATMETA_T0HALT_BITS 0xF 270#define HWSTATMETA_T0HALT_S 0 271#define HWSTATMETA_T0BHALT_BIT 0x1 /* Background HALT */ 272#define HWSTATMETA_T0IHALT_BIT 0x2 /* Interrupt HALT */ 273#define HWSTATMETA_T0PHALT_BIT 0x4 /* PF/RO Memory HALT */ 274#define HWSTATMETA_T0AMATR_BIT 0x8 /* AMA trigger */ 275#define HWSTATMETA_TnINT_S 4 /* Shift by (thread*4) */ 276#define HWSTATEXT 0x04820010 /* H/W status/clear external trigs 0-31 */ 277#define HWSTATEXT2 0x04820018 /* H/W status/clear external trigs 32-63 */ 278#define HWSTATEXT4 0x04820020 /* H/W status/clear external trigs 64-95 */ 279#define HWSTATEXT6 0x04820028 /* H/W status/clear external trigs 96-128 */ 280#define HWLEVELEXT 0x04820030 /* Edge/Level type of external trigs 0-31 */ 281#define HWLEVELEXT2 0x04820038 /* Edge/Level type of external trigs 32-63 */ 282#define HWLEVELEXT4 0x04820040 /* Edge/Level type of external trigs 64-95 */ 283#define HWLEVELEXT6 0x04820048 /* Edge/Level type of external trigs 96-128 */ 284#define HWLEVELEXT_XXX_LEVEL 1 /* Level sense logic in HWSTATEXTn */ 285#define HWLEVELEXT_XXX_EDGE 0 286#define HWMASKEXT 0x04820050 /* Enable/disable of external trigs 0-31 */ 287#define HWMASKEXT2 0x04820058 /* Enable/disable of external trigs 32-63 */ 288#define HWMASKEXT4 0x04820060 /* Enable/disable of external trigs 64-95 */ 289#define HWMASKEXT6 0x04820068 /* Enable/disable of external trigs 96-128 */ 290#define T0VECINT_BHALT 0x04820500 /* Background HALT trigger vector */ 291#define TXVECXXX_BITS 0xF /* Per-trigger vector vals 0,1,4-15 */ 292#define TXVECXXX_S 0 293#define T0VECINT_IHALT 0x04820508 /* Interrupt HALT */ 294#define T0VECINT_PHALT 0x04820510 /* PF/RO memory fault */ 295#define T0VECINT_AMATR 0x04820518 /* AMA trigger */ 296#define TnVECINT_STRIDE 0x00000020 /* Per thread stride */ 297#define HWVEC0EXT 0x04820700 /* Vectors for external triggers 0-31 */ 298#define HWVEC20EXT 0x04821700 /* Vectors for external triggers 32-63 */ 299#define HWVEC40EXT 0x04822700 /* Vectors for external triggers 64-95 */ 300#define HWVEC60EXT 0x04823700 /* Vectors for external triggers 96-127 */ 301#define HWVECnEXT_STRIDE 0x00000008 /* Per trigger stride */ 302#define HWVECnEXT_DEBUG 0x1 /* Redirect trigger to debug i/f */ 303 304/* 305 * CORE HWCODE-BREAKPOINT REGISTERS/VALUES 306 * --------------------------------------- 307 */ 308#define CODEB0ADDR 0x0480FF00 /* Address specifier */ 309#define CODEBXADDR_MATCHX_BITS 0xFFFFFFFC 310#define CODEBXADDR_MATCHX_S 2 311#define CODEB0CTRL 0x0480FF08 /* Control */ 312#define CODEBXCTRL_MATEN_BIT 0x80000000 /* Match 'Enable' */ 313#define CODEBXCTRL_MATTXEN_BIT 0x10000000 /* Match threadn enable */ 314#define CODEBXCTRL_HITC_BITS 0x00FF0000 /* Hit counter */ 315#define CODEBXCTRL_HITC_S 16 316#define CODEBXHITC_NEXT 0xFF /* Next 'hit' will trigger */ 317#define CODEBXHITC_HIT1 0x00 /* No 'hits' after trigger */ 318#define CODEBXCTRL_MMASK_BITS 0x0000FFFC /* Mask ADDR_MATCH bits */ 319#define CODEBXCTRL_MMASK_S 2 320#define CODEBXCTRL_MATLTX_BITS 0x00000003 /* Match threadn LOCAL addr */ 321#define CODEBXCTRL_MATLTX_S 0 /* Match threadn LOCAL addr */ 322#define CODEBnXXXX_STRIDE 0x00000010 /* Stride between CODEB reg sets */ 323#define CODEBnXXXX_STRIDE_S 4 324#define CODEBnXXXX_LIMIT 3 /* Sets 0-3 */ 325 326/* 327 * CORE DATA-WATCHPOINT REGISTERS/VALUES 328 * ------------------------------------- 329 */ 330#define DATAW0ADDR 0x0480FF40 /* Address specifier */ 331#define DATAWXADDR_MATCHR_BITS 0xFFFFFFF8 332#define DATAWXADDR_MATCHR_S 3 333#define DATAWXADDR_MATCHW_BITS 0xFFFFFFFF 334#define DATAWXADDR_MATCHW_S 0 335#define DATAW0CTRL 0x0480FF48 /* Control */ 336#define DATAWXCTRL_MATRD_BIT 0x80000000 /* Match 'Read' */ 337#ifndef METAC_1_2 338#define DATAWXCTRL_MATNOTTX_BIT 0x20000000 /* Invert threadn enable */ 339#endif 340#define DATAWXCTRL_MATWR_BIT 0x40000000 /* Match 'Write' */ 341#define DATAWXCTRL_MATTXEN_BIT 0x10000000 /* Match threadn enable */ 342#define DATAWXCTRL_WRSIZE_BITS 0x0F000000 /* Write Match Size */ 343#define DATAWXCTRL_WRSIZE_S 24 344#define DATAWWRSIZE_ANY 0 /* Any size transaction matches */ 345#define DATAWWRSIZE_8BIT 1 /* Specific sizes ... */ 346#define DATAWWRSIZE_16BIT 2 347#define DATAWWRSIZE_32BIT 3 348#define DATAWWRSIZE_64BIT 4 349#define DATAWXCTRL_HITC_BITS 0x00FF0000 /* Hit counter */ 350#define DATAWXCTRL_HITC_S 16 351#define DATAWXHITC_NEXT 0xFF /* Next 'hit' will trigger */ 352#define DATAWXHITC_HIT1 0x00 /* No 'hits' after trigger */ 353#define DATAWXCTRL_MMASK_BITS 0x0000FFF8 /* Mask ADDR_MATCH bits */ 354#define DATAWXCTRL_MMASK_S 3 355#define DATAWXCTRL_MATLTX_BITS 0x00000003 /* Match threadn LOCAL addr */ 356#define DATAWXCTRL_MATLTX_S 0 /* Match threadn LOCAL addr */ 357#define DATAW0DMATCH0 0x0480FF50 /* Write match data */ 358#define DATAW0DMATCH1 0x0480FF58 359#define DATAW0DMASK0 0x0480FF60 /* Write match data mask */ 360#define DATAW0DMASK1 0x0480FF68 361#define DATAWnXXXX_STRIDE 0x00000040 /* Stride between DATAW reg sets */ 362#define DATAWnXXXX_STRIDE_S 6 363#define DATAWnXXXX_LIMIT 1 /* Sets 0,1 */ 364 365/* 366 * CHIP Automatic Mips Allocation control registers 367 * ------------------------------------------------ 368 */ 369 370/* CORE memory mapped AMA registers */ 371#define T0AMAREG4 0x04800810 372#define TXAMAREG4_POOLSIZE_BITS 0x3FFFFF00 373#define TXAMAREG4_POOLSIZE_S 8 374#define TXAMAREG4_AVALUE_BITS 0x000000FF 375#define TXAMAREG4_AVALUE_S 0 376#define T0AMAREG5 0x04800818 377#define TXAMAREG5_POOLC_BITS 0x07FFFFFF 378#define TXAMAREG5_POOLC_S 0 379#define T0AMAREG6 0x04800820 380#define TXAMAREG6_DLINEDEF_BITS 0x00FFFFF0 381#define TXAMAREG6_DLINEDEF_S 0 382#define TnAMAREGX_STRIDE 0x00001000 383 384/* 385 * Memory Management Control Unit Table Entries 386 * -------------------------------------------- 387 */ 388#define MMCU_ENTRY_S 4 /* -> Entry size */ 389#define MMCU_ENTRY_ADDR_BITS 0xFFFFF000 /* Physical address */ 390#define MMCU_ENTRY_ADDR_S 12 /* -> Page size */ 391#define MMCU_ENTRY_CWIN_BITS 0x000000C0 /* Caching 'window' selection */ 392#define MMCU_ENTRY_CWIN_S 6 393#define MMCU_CWIN_UNCACHED 0 /* May not be memory etc. */ 394#define MMCU_CWIN_BURST 1 /* Cached but LRU unset */ 395#define MMCU_CWIN_C1SET 2 /* Cached in 1 set only */ 396#define MMCU_CWIN_CACHED 3 /* Fully cached */ 397#define MMCU_ENTRY_CACHE_BIT 0x00000080 /* Set for cached region */ 398#define MMCU_ECACHE1_FULL_BIT 0x00000040 /* Use all the sets */ 399#define MMCU_ECACHE0_BURST_BIT 0x00000040 /* Match bursts */ 400#define MMCU_ENTRY_SYS_BIT 0x00000010 /* Sys-coherent access required */ 401#define MMCU_ENTRY_WRC_BIT 0x00000008 /* Write combining allowed */ 402#define MMCU_ENTRY_PRIV_BIT 0x00000004 /* Privilege required */ 403#define MMCU_ENTRY_WR_BIT 0x00000002 /* Writes allowed */ 404#define MMCU_ENTRY_VAL_BIT 0x00000001 /* Entry is valid */ 405 406#ifdef METAC_2_1 407/* 408 * Extended first-level/top table entries have extra/larger fields in later 409 * cores as bits 11:0 previously had no effect in such table entries. 410 */ 411#define MMCU_E1ENT_ADDR_BITS 0xFFFFFFC0 /* Physical address */ 412#define MMCU_E1ENT_ADDR_S 6 /* -> resolution < page size */ 413#define MMCU_E1ENT_PGSZ_BITS 0x0000001E /* Page size for 2nd level */ 414#define MMCU_E1ENT_PGSZ_S 1 415#define MMCU_E1ENT_PGSZ0_POWER 12 /* PgSz 0 -> 4K */ 416#define MMCU_E1ENT_PGSZ_MAX 10 /* PgSz 10 -> 4M maximum */ 417#define MMCU_E1ENT_MINIM_BIT 0x00000020 418#endif /* METAC_2_1 */ 419 420/* MMCU control register in SYSC region */ 421#define MMCU_TABLE_PHYS_ADDR 0x04830010 422#define MMCU_TABLE_PHYS_ADDR_BITS 0xFFFFFFFC 423#ifdef METAC_2_1 424#define MMCU_TABLE_PHYS_EXTEND 0x00000001 /* See below */ 425#endif 426#define MMCU_DCACHE_CTRL_ADDR 0x04830018 427#define MMCU_xCACHE_CTRL_ENABLE_BIT 0x00000001 428#define MMCU_xCACHE_CTRL_PARTITION_BIT 0x00000000 /* See xCPART below */ 429#define MMCU_ICACHE_CTRL_ADDR 0x04830020 430 431#ifdef METAC_2_1 432 433/* 434 * Allow direct access to physical memory used to implement MMU table. 435 * 436 * Each is based on a corresponding MMCU_TnLOCAL_TABLE_PHYSn or similar 437 * MMCU_TnGLOBAL_TABLE_PHYSn register pair (see next). 438 */ 439#define LINSYSMEMT0L_BASE 0x05000000 440#define LINSYSMEMT0L_LIMIT 0x051FFFFF 441#define LINSYSMEMTnX_STRIDE 0x00200000 /* 2MB Local per thread */ 442#define LINSYSMEMTnX_STRIDE_S 21 443#define LINSYSMEMTXG_OFFSET 0x00800000 /* +2MB Global per thread */ 444#define LINSYSMEMTXG_OFFSET_S 23 445#define LINSYSMEMT1L_BASE 0x05200000 446#define LINSYSMEMT1L_LIMIT 0x053FFFFF 447#define LINSYSMEMT2L_BASE 0x05400000 448#define LINSYSMEMT2L_LIMIT 0x055FFFFF 449#define LINSYSMEMT3L_BASE 0x05600000 450#define LINSYSMEMT3L_LIMIT 0x057FFFFF 451#define LINSYSMEMT0G_BASE 0x05800000 452#define LINSYSMEMT0G_LIMIT 0x059FFFFF 453#define LINSYSMEMT1G_BASE 0x05A00000 454#define LINSYSMEMT1G_LIMIT 0x05BFFFFF 455#define LINSYSMEMT2G_BASE 0x05C00000 456#define LINSYSMEMT2G_LIMIT 0x05DFFFFF 457#define LINSYSMEMT3G_BASE 0x05E00000 458#define LINSYSMEMT3G_LIMIT 0x05FFFFFF 459 460/* 461 * Extended MMU table functionality allows a sparse or flat table to be 462 * described much more efficiently than before. 463 */ 464#define MMCU_T0LOCAL_TABLE_PHYS0 0x04830700 465#define MMCU_TnX_TABLE_PHYSX_STRIDE 0x20 /* Offset per thread */ 466#define MMCU_TnX_TABLE_PHYSX_STRIDE_S 5 467#define MMCU_TXG_TABLE_PHYSX_OFFSET 0x10 /* Global versus local */ 468#define MMCU_TXG_TABLE_PHYSX_OFFSET_S 4 469#define MMCU_TBLPHYS0_DCCTRL_BITS 0x000000DF /* DC controls */ 470#define MMCU_TBLPHYS0_ENTLB_BIT 0x00000020 /* Cache in TLB */ 471#define MMCU_TBLPHYS0_TBLSZ_BITS 0x00000F00 /* Area supported */ 472#define MMCU_TBLPHYS0_TBLSZ_S 8 473#define MMCU_TBLPHYS0_TBLSZ0_POWER 22 /* 0 -> 4M */ 474#define MMCU_TBLPHYS0_TBLSZ_MAX 9 /* 9 -> 2G */ 475#define MMCU_TBLPHYS0_LINBASE_BITS 0xFFC00000 /* Linear base */ 476#define MMCU_TBLPHYS0_LINBASE_S 22 477 478#define MMCU_T0LOCAL_TABLE_PHYS1 0x04830708 479#define MMCU_TBLPHYS1_ADDR_BITS 0xFFFFFFFC /* Physical base */ 480#define MMCU_TBLPHYS1_ADDR_S 2 481 482#define MMCU_T0GLOBAL_TABLE_PHYS0 0x04830710 483#define MMCU_T0GLOBAL_TABLE_PHYS1 0x04830718 484#define MMCU_T1LOCAL_TABLE_PHYS0 0x04830720 485#define MMCU_T1LOCAL_TABLE_PHYS1 0x04830728 486#define MMCU_T1GLOBAL_TABLE_PHYS0 0x04830730 487#define MMCU_T1GLOBAL_TABLE_PHYS1 0x04830738 488#define MMCU_T2LOCAL_TABLE_PHYS0 0x04830740 489#define MMCU_T2LOCAL_TABLE_PHYS1 0x04830748 490#define MMCU_T2GLOBAL_TABLE_PHYS0 0x04830750 491#define MMCU_T2GLOBAL_TABLE_PHYS1 0x04830758 492#define MMCU_T3LOCAL_TABLE_PHYS0 0x04830760 493#define MMCU_T3LOCAL_TABLE_PHYS1 0x04830768 494#define MMCU_T3GLOBAL_TABLE_PHYS0 0x04830770 495#define MMCU_T3GLOBAL_TABLE_PHYS1 0x04830778 496 497#define MMCU_T0EBWCCTRL 0x04830640 498#define MMCU_TnEBWCCTRL_BITS 0x00000007 499#define MMCU_TnEBWCCTRL_S 0 500#define MMCU_TnEBWCCCTRL_DISABLE_ALL 0 501#define MMCU_TnEBWCCCTRL_ABIT25 1 502#define MMCU_TnEBWCCCTRL_ABIT26 2 503#define MMCU_TnEBWCCCTRL_ABIT27 3 504#define MMCU_TnEBWCCCTRL_ABIT28 4 505#define MMCU_TnEBWCCCTRL_ABIT29 5 506#define MMCU_TnEBWCCCTRL_ABIT30 6 507#define MMCU_TnEBWCCCTRL_ENABLE_ALL 7 508#define MMCU_TnEBWCCTRL_STRIDE 8 509 510#endif /* METAC_2_1 */ 511 512 513/* Registers within the SYSC register region */ 514#define METAC_ID 0x04830000 515#define METAC_ID_MAJOR_BITS 0xFF000000 516#define METAC_ID_MAJOR_S 24 517#define METAC_ID_MINOR_BITS 0x00FF0000 518#define METAC_ID_MINOR_S 16 519#define METAC_ID_REV_BITS 0x0000FF00 520#define METAC_ID_REV_S 8 521#define METAC_ID_MAINT_BITS 0x000000FF 522#define METAC_ID_MAINT_S 0 523 524#ifdef METAC_2_1 525/* Use of this section is strongly deprecated */ 526#define METAC_ID2 0x04830008 527#define METAC_ID2_DESIGNER_BITS 0xFFFF0000 /* Modified by customer */ 528#define METAC_ID2_DESIGNER_S 16 529#define METAC_ID2_MINOR2_BITS 0x00000F00 /* 3rd digit of prod rev */ 530#define METAC_ID2_MINOR2_S 8 531#define METAC_ID2_CONFIG_BITS 0x000000FF /* Wrapper configuration */ 532#define METAC_ID2_CONFIG_S 0 533 534/* Primary core identification and configuration information */ 535#define METAC_CORE_ID 0x04831000 536#define METAC_COREID_GROUP_BITS 0xFF000000 537#define METAC_COREID_GROUP_S 24 538#define METAC_COREID_GROUP_METAG 0x14 539#define METAC_COREID_ID_BITS 0x00FF0000 540#define METAC_COREID_ID_S 16 541#define METAC_COREID_ID_W32 0x10 /* >= for 32-bit pipeline */ 542#define METAC_COREID_CONFIG_BITS 0x0000FFFF 543#define METAC_COREID_CONFIG_S 0 544#define METAC_COREID_CFGCACHE_BITS 0x0007 545#define METAC_COREID_CFGCACHE_S 0 546#define METAC_COREID_CFGCACHE_NOM 0 547#define METAC_COREID_CFGCACHE_TYPE0 1 548#define METAC_COREID_CFGCACHE_NOMMU 1 /* Alias for TYPE0 */ 549#define METAC_COREID_CFGCACHE_NOCACHE 2 550#define METAC_COREID_CFGCACHE_PRIVNOMMU 3 551#define METAC_COREID_CFGDSP_BITS 0x0038 552#define METAC_COREID_CFGDSP_S 3 553#define METAC_COREID_CFGDSP_NOM 0 554#define METAC_COREID_CFGDSP_MIN 1 555#define METAC_COREID_NOFPACC_BIT 0x0040 /* Set if no FPU accum */ 556#define METAC_COREID_CFGFPU_BITS 0x0180 557#define METAC_COREID_CFGFPU_S 7 558#define METAC_COREID_CFGFPU_NOM 0 559#define METAC_COREID_CFGFPU_SNGL 1 560#define METAC_COREID_CFGFPU_DBL 2 561#define METAC_COREID_NOAMA_BIT 0x0200 /* Set if no AMA present */ 562#define METAC_COREID_NOCOH_BIT 0x0400 /* Set if no Gbl coherency */ 563 564/* Core revision information */ 565#define METAC_CORE_REV 0x04831008 566#define METAC_COREREV_DESIGN_BITS 0xFF000000 567#define METAC_COREREV_DESIGN_S 24 568#define METAC_COREREV_MAJOR_BITS 0x00FF0000 569#define METAC_COREREV_MAJOR_S 16 570#define METAC_COREREV_MINOR_BITS 0x0000FF00 571#define METAC_COREREV_MINOR_S 8 572#define METAC_COREREV_MAINT_BITS 0x000000FF 573#define METAC_COREREV_MAINT_S 0 574 575/* Configuration information control outside the core */ 576#define METAC_CORE_DESIGNER1 0x04831010 /* Arbitrary value */ 577#define METAC_CORE_DESIGNER2 0x04831018 /* Arbitrary value */ 578 579/* Configuration information covering presence/number of various features */ 580#define METAC_CORE_CONFIG2 0x04831020 581#define METAC_CORECFG2_COREDBGTYPE_BITS 0x60000000 /* Core debug type */ 582#define METAC_CORECFG2_COREDBGTYPE_S 29 583#define METAC_CORECFG2_DCSMALL_BIT 0x04000000 /* Data cache small */ 584#define METAC_CORECFG2_ICSMALL_BIT 0x02000000 /* Inst cache small */ 585#define METAC_CORECFG2_DCSZNP_BITS 0x01C00000 /* Data cache size np */ 586#define METAC_CORECFG2_DCSZNP_S 22 587#define METAC_CORECFG2_ICSZNP_BITS 0x00380000 /* Inst cache size np */ 588#define METAC_CORECFG2_ICSZNP_S 19 589#define METAC_CORECFG2_DCSZ_BITS 0x00070000 /* Data cache size */ 590#define METAC_CORECFG2_DCSZ_S 16 591#define METAC_CORECFG2_xCSZ_4K 0 /* Allocated values */ 592#define METAC_CORECFG2_xCSZ_8K 1 593#define METAC_CORECFG2_xCSZ_16K 2 594#define METAC_CORECFG2_xCSZ_32K 3 595#define METAC_CORECFG2_xCSZ_64K 4 596#define METAC_CORE_C2ICSZ_BITS 0x0000E000 /* Inst cache size */ 597#define METAC_CORE_C2ICSZ_S 13 598#define METAC_CORE_GBLACC_BITS 0x00001800 /* Number of Global Acc */ 599#define METAC_CORE_GBLACC_S 11 600#define METAC_CORE_GBLDXR_BITS 0x00000700 /* 0 -> 0, R -> 2^(R-1) */ 601#define METAC_CORE_GBLDXR_S 8 602#define METAC_CORE_GBLAXR_BITS 0x000000E0 /* 0 -> 0, R -> 2^(R-1) */ 603#define METAC_CORE_GBLAXR_S 5 604#define METAC_CORE_RTTRACE_BIT 0x00000010 605#define METAC_CORE_WATCHN_BITS 0x0000000C /* 0 -> 0, N -> 2^N */ 606#define METAC_CORE_WATCHN_S 2 607#define METAC_CORE_BREAKN_BITS 0x00000003 /* 0 -> 0, N -> 2^N */ 608#define METAC_CORE_BREAKN_S 0 609 610/* Configuration information covering presence/number of various features */ 611#define METAC_CORE_CONFIG3 0x04831028 612#define METAC_CORECFG3_L2C_REV_ID_BITS 0x000F0000 /* Revision of L2 cache */ 613#define METAC_CORECFG3_L2C_REV_ID_S 16 614#define METAC_CORECFG3_L2C_LINE_SIZE_BITS 0x00003000 /* L2 line size */ 615#define METAC_CORECFG3_L2C_LINE_SIZE_S 12 616#define METAC_CORECFG3_L2C_LINE_SIZE_64B 0x0 /* 64 bytes */ 617#define METAC_CORECFG3_L2C_NUM_WAYS_BITS 0x00000F00 /* L2 number of ways (2^n) */ 618#define METAC_CORECFG3_L2C_NUM_WAYS_S 8 619#define METAC_CORECFG3_L2C_SIZE_BITS 0x000000F0 /* L2 size (2^n) */ 620#define METAC_CORECFG3_L2C_SIZE_S 4 621#define METAC_CORECFG3_L2C_UNIFIED_BIT 0x00000004 /* Unified cache: */ 622#define METAC_CORECFG3_L2C_UNIFIED_S 2 623#define METAC_CORECFG3_L2C_UNIFIED_UNIFIED 1 /* - Unified D/I cache */ 624#define METAC_CORECFG3_L2C_UNIFIED_SEPARATE 0 /* - Separate D/I cache */ 625#define METAC_CORECFG3_L2C_MODE_BIT 0x00000002 /* Cache Mode: */ 626#define METAC_CORECFG3_L2C_MODE_S 1 627#define METAC_CORECFG3_L2C_MODE_WRITE_BACK 1 /* - Write back */ 628#define METAC_CORECFG3_L2C_MODE_WRITE_THROUGH 0 /* - Write through */ 629#define METAC_CORECFG3_L2C_HAVE_L2C_BIT 0x00000001 /* Have L2C */ 630#define METAC_CORECFG3_L2C_HAVE_L2C_S 0 631 632#endif /* METAC_2_1 */ 633 634#define SYSC_CACHE_MMU_CONFIG 0x04830028 635#ifdef METAC_2_1 636#define SYSC_CMMUCFG_DCSKEWABLE_BIT 0x00000040 637#define SYSC_CMMUCFG_ICSKEWABLE_BIT 0x00000020 638#define SYSC_CMMUCFG_DCSKEWOFF_BIT 0x00000010 /* Skew association override */ 639#define SYSC_CMMUCFG_ICSKEWOFF_BIT 0x00000008 /* -> default 0 on if present */ 640#define SYSC_CMMUCFG_MODE_BITS 0x00000007 /* Access to old state */ 641#define SYSC_CMMUCFG_MODE_S 0 642#define SYSC_CMMUCFG_ON 0x7 643#define SYSC_CMMUCFG_EBYPASS 0x6 /* Enhanced by-pass mode */ 644#define SYSC_CMMUCFG_EBYPASSIC 0x4 /* EB just inst cache */ 645#define SYSC_CMMUCFG_EBYPASSDC 0x2 /* EB just data cache */ 646#endif /* METAC_2_1 */ 647/* Old definitions, Keep them for now */ 648#define SYSC_CMMUCFG_MMU_ON_BIT 0x1 649#define SYSC_CMMUCFG_DC_ON_BIT 0x2 650#define SYSC_CMMUCFG_IC_ON_BIT 0x4 651 652#define SYSC_JTAG_THREAD 0x04830030 653#define SYSC_JTAG_TX_BITS 0x00000003 /* Read only bits! */ 654#define SYSC_JTAG_TX_S 0 655#define SYSC_JTAG_PRIV_BIT 0x00000004 656#ifdef METAC_2_1 657#define SYSC_JTAG_SLAVETX_BITS 0x00000018 658#define SYSC_JTAG_SLAVETX_S 3 659#endif /* METAC_2_1 */ 660 661#define SYSC_DCACHE_FLUSH 0x04830038 662#define SYSC_ICACHE_FLUSH 0x04830040 663#define SYSC_xCACHE_FLUSH_INIT 0x1 664#define MMCU_DIRECTMAP0_ADDR 0x04830080 /* LINSYSDIRECT_BASE -> */ 665#define MMCU_DIRECTMAPn_STRIDE 0x00000010 /* 4 Region settings */ 666#define MMCU_DIRECTMAPn_S 4 667#define MMCU_DIRECTMAPn_ADDR_BITS 0xFF800000 668#define MMCU_DIRECTMAPn_ADDR_S 23 669#define MMCU_DIRECTMAPn_ADDR_SCALE 0x00800000 /* 8M Regions */ 670#ifdef METAC_2_1 671/* 672 * These fields in the above registers provide MMCU_ENTRY_* values 673 * for each direct mapped region to enable optimisation of these areas. 674 * (LSB similar to VALID must be set for enhancments to be active) 675 */ 676#define MMCU_DIRECTMAPn_ENHANCE_BIT 0x00000001 /* 0 = no optim */ 677#define MMCU_DIRECTMAPn_DCCTRL_BITS 0x000000DF /* Get DC Ctrl */ 678#define MMCU_DIRECTMAPn_DCCTRL_S 0 679#define MMCU_DIRECTMAPn_ICCTRL_BITS 0x0000C000 /* Get IC Ctrl */ 680#define MMCU_DIRECTMAPn_ICCTRL_S 8 681#define MMCU_DIRECTMAPn_ENTLB_BIT 0x00000020 /* Cache in TLB */ 682#define MMCU_DIRECTMAPn_ICCWIN_BITS 0x0000C000 /* Get IC Win Bits */ 683#define MMCU_DIRECTMAPn_ICCWIN_S 14 684#endif /* METAC_2_1 */ 685 686#define MMCU_DIRECTMAP1_ADDR 0x04830090 687#define MMCU_DIRECTMAP2_ADDR 0x048300a0 688#define MMCU_DIRECTMAP3_ADDR 0x048300b0 689 690/* 691 * These bits partion each threads use of data cache or instruction cache 692 * resource by modifying the top 4 bits of the address within the cache 693 * storage area. 694 */ 695#define SYSC_DCPART0 0x04830200 696#define SYSC_xCPARTn_STRIDE 0x00000008 697#define SYSC_xCPARTL_AND_BITS 0x0000000F /* Masks top 4 bits */ 698#define SYSC_xCPARTL_AND_S 0 699#define SYSC_xCPARTG_AND_BITS 0x00000F00 /* Masks top 4 bits */ 700#define SYSC_xCPARTG_AND_S 8 701#define SYSC_xCPARTL_OR_BITS 0x000F0000 /* Ors into top 4 bits */ 702#define SYSC_xCPARTL_OR_S 16 703#ifdef METAC_2_1 704#define SYSC_DCPART_GCON_BIT 0x00100000 /* Coherent shared local */ 705#endif /* METAC_2_1 */ 706#define SYSC_xCPARTG_OR_BITS 0x0F000000 /* Ors into top 4 bits */ 707#define SYSC_xCPARTG_OR_S 24 708#define SYSC_CWRMODE_BIT 0x80000000 /* Write cache mode bit */ 709 710#define SYSC_DCPART1 0x04830208 711#define SYSC_DCPART2 0x04830210 712#define SYSC_DCPART3 0x04830218 713#define SYSC_ICPART0 0x04830220 714#define SYSC_ICPART1 0x04830228 715#define SYSC_ICPART2 0x04830230 716#define SYSC_ICPART3 0x04830238 717 718/* 719 * META Core Memory and Cache Update registers 720 */ 721#define SYSC_MCMDATAX 0x04830300 /* 32-bit read/write data register */ 722#define SYSC_MCMDATAT 0x04830308 /* Read or write data triggers oper */ 723#define SYSC_MCMGCTRL 0x04830310 /* Control register */ 724#define SYSC_MCMGCTRL_READ_BIT 0x00000001 /* Set to issue 1st read */ 725#define SYSC_MCMGCTRL_AINC_BIT 0x00000002 /* Set for auto-increment */ 726#define SYSC_MCMGCTRL_ADDR_BITS 0x000FFFFC /* Address or index */ 727#define SYSC_MCMGCTRL_ADDR_S 2 728#define SYSC_MCMGCTRL_ID_BITS 0x0FF00000 /* Internal memory block Id */ 729#define SYSC_MCMGCTRL_ID_S 20 730#define SYSC_MCMGID_NODEV 0xFF /* No Device Selected */ 731#define SYSC_MCMGID_DSPRAM0A 0x04 /* DSP RAM D0 block A access */ 732#define SYSC_MCMGID_DSPRAM0B 0x05 /* DSP RAM D0 block B access */ 733#define SYSC_MCMGID_DSPRAM1A 0x06 /* DSP RAM D1 block A access */ 734#define SYSC_MCMGID_DSPRAM1B 0x07 /* DSP RAM D1 block B access */ 735#define SYSC_MCMGID_DCACHEL 0x08 /* DCACHE lines (64-bytes/line) */ 736#ifdef METAC_2_1 737#define SYSC_MCMGID_DCACHETLB 0x09 /* DCACHE TLB ( Read Only ) */ 738#endif /* METAC_2_1 */ 739#define SYSC_MCMGID_DCACHET 0x0A /* DCACHE tags (32-bits/line) */ 740#define SYSC_MCMGID_DCACHELRU 0x0B /* DCACHE LRU (8-bits/line) */ 741#define SYSC_MCMGID_ICACHEL 0x0C /* ICACHE lines (64-bytes/line */ 742#ifdef METAC_2_1 743#define SYSC_MCMGID_ICACHETLB 0x0D /* ICACHE TLB (Read Only ) */ 744#endif /* METAC_2_1 */ 745#define SYSC_MCMGID_ICACHET 0x0E /* ICACHE Tags (32-bits/line) */ 746#define SYSC_MCMGID_ICACHELRU 0x0F /* ICACHE LRU (8-bits/line ) */ 747#define SYSC_MCMGID_COREIRAM0 0x10 /* Core code mem id 0 */ 748#define SYSC_MCMGID_COREIRAMn 0x17 749#define SYSC_MCMGID_COREDRAM0 0x18 /* Core data mem id 0 */ 750#define SYSC_MCMGID_COREDRAMn 0x1F 751#ifdef METAC_2_1 752#define SYSC_MCMGID_DCACHEST 0x20 /* DCACHE ST ( Read Only ) */ 753#define SYSC_MCMGID_ICACHEST 0x21 /* ICACHE ST ( Read Only ) */ 754#define SYSC_MCMGID_DCACHETLBLRU 0x22 /* DCACHE TLB LRU ( Read Only )*/ 755#define SYSC_MCMGID_ICACHETLBLRU 0x23 /* ICACHE TLB LRU( Read Only ) */ 756#define SYSC_MCMGID_DCACHESTLRU 0x24 /* DCACHE ST LRU ( Read Only ) */ 757#define SYSC_MCMGID_ICACHESTLRU 0x25 /* ICACHE ST LRU ( Read Only ) */ 758#define SYSC_MCMGID_DEBUGTLB 0x26 /* DEBUG TLB ( Read Only ) */ 759#define SYSC_MCMGID_DEBUGST 0x27 /* DEBUG ST ( Read Only ) */ 760#define SYSC_MCMGID_L2CACHEL 0x30 /* L2 Cache Lines (64-bytes/line) */ 761#define SYSC_MCMGID_L2CACHET 0x31 /* L2 Cache Tags (32-bits/line) */ 762#define SYSC_MCMGID_COPROX0 0x70 /* Coprocessor port id 0 */ 763#define SYSC_MCMGID_COPROXn 0x77 764#endif /* METAC_2_1 */ 765#define SYSC_MCMGCTRL_TR31_BIT 0x80000000 /* Trigger 31 on completion */ 766#define SYSC_MCMSTATUS 0x04830318 /* Status read only */ 767#define SYSC_MCMSTATUS_IDLE_BIT 0x00000001 768 769/* META System Events */ 770#define SYSC_SYS_EVENT 0x04830400 771#define SYSC_SYSEVT_ATOMIC_BIT 0x00000001 772#define SYSC_SYSEVT_CACHEX_BIT 0x00000002 773#define SYSC_ATOMIC_LOCK 0x04830408 774#define SYSC_ATOMIC_STATE_TX_BITS 0x0000000F 775#define SYSC_ATOMIC_STATE_TX_S 0 776#ifdef METAC_1_2 777#define SYSC_ATOMIC_STATE_DX_BITS 0x000000F0 778#define SYSC_ATOMIC_STATE_DX_S 4 779#else /* METAC_1_2 */ 780#define SYSC_ATOMIC_SOURCE_BIT 0x00000010 781#endif /* !METAC_1_2 */ 782 783 784#ifdef METAC_2_1 785 786/* These definitions replace the EXPAND_TIMER_DIV register defines which are to 787 * be deprecated. 788 */ 789#define SYSC_TIMER_DIV 0x04830140 790#define SYSC_TIMDIV_BITS 0x000000FF 791#define SYSC_TIMDIV_S 0 792 793/* META Enhanced by-pass control for local and global region */ 794#define MMCU_LOCAL_EBCTRL 0x04830600 795#define MMCU_GLOBAL_EBCTRL 0x04830608 796#define MMCU_EBCTRL_SINGLE_BIT 0x00000020 /* TLB Uncached */ 797/* 798 * These fields in the above registers provide MMCU_ENTRY_* values 799 * for each direct mapped region to enable optimisation of these areas. 800 */ 801#define MMCU_EBCTRL_DCCTRL_BITS 0x000000C0 /* Get DC Ctrl */ 802#define MMCU_EBCTRL_DCCTRL_S 0 803#define MMCU_EBCTRL_ICCTRL_BITS 0x0000C000 /* Get DC Ctrl */ 804#define MMCU_EBCTRL_ICCTRL_S 8 805 806/* META Cached Core Mode Registers */ 807#define MMCU_T0CCM_ICCTRL 0x04830680 /* Core cached code control */ 808#define MMCU_TnCCM_xxCTRL_STRIDE 8 809#define MMCU_TnCCM_xxCTRL_STRIDE_S 3 810#define MMCU_T1CCM_ICCTRL 0x04830688 811#define MMCU_T2CCM_ICCTRL 0x04830690 812#define MMCU_T3CCM_ICCTRL 0x04830698 813#define MMCU_T0CCM_DCCTRL 0x048306C0 /* Core cached data control */ 814#define MMCU_T1CCM_DCCTRL 0x048306C8 815#define MMCU_T2CCM_DCCTRL 0x048306D0 816#define MMCU_T3CCM_DCCTRL 0x048306D8 817#define MMCU_TnCCM_ENABLE_BIT 0x00000001 818#define MMCU_TnCCM_WIN3_BIT 0x00000002 819#define MMCU_TnCCM_DCWRITE_BIT 0x00000004 /* In DCCTRL only */ 820#define MMCU_TnCCM_REGSZ_BITS 0x00000F00 821#define MMCU_TnCCM_REGSZ_S 8 822#define MMCU_TnCCM_REGSZ0_POWER 12 /* RegSz 0 -> 4K */ 823#define MMCU_TnCCM_REGSZ_MAXBYTES 0x00080000 /* 512K max */ 824#define MMCU_TnCCM_ADDR_BITS 0xFFFFF000 825#define MMCU_TnCCM_ADDR_S 12 826 827#endif /* METAC_2_1 */ 828 829/* 830 * Hardware performance counter registers 831 * -------------------------------------- 832 */ 833#ifdef METAC_2_1 834/* Two Performance Counter Internal Core Events Control registers */ 835#define PERF_ICORE0 0x0480FFD0 836#define PERF_ICORE1 0x0480FFD8 837#define PERFI_CTRL_BITS 0x0000000F 838#define PERFI_CTRL_S 0 839#define PERFI_CAH_DMISS 0x0 /* Dcache Misses in cache (TLB Hit) */ 840#define PERFI_CAH_IMISS 0x1 /* Icache Misses in cache (TLB Hit) */ 841#define PERFI_TLB_DMISS 0x2 /* Dcache Misses in per-thread TLB */ 842#define PERFI_TLB_IMISS 0x3 /* Icache Misses in per-thread TLB */ 843#define PERFI_TLB_DWRHITS 0x4 /* DC Write-Hits in per-thread TLB */ 844#define PERFI_TLB_DWRMISS 0x5 /* DC Write-Miss in per-thread TLB */ 845#define PERFI_CAH_DLFETCH 0x8 /* DC Read cache line fetch */ 846#define PERFI_CAH_ILFETCH 0x9 /* DC Read cache line fetch */ 847#define PERFI_CAH_DWFETCH 0xA /* DC Read cache word fetch */ 848#define PERFI_CAH_IWFETCH 0xB /* DC Read cache word fetch */ 849#endif /* METAC_2_1 */ 850 851/* Two memory-mapped hardware performance counter registers */ 852#define PERF_COUNT0 0x0480FFE0 853#define PERF_COUNT1 0x0480FFE8 854 855/* Fields in PERF_COUNTn registers */ 856#define PERF_COUNT_BITS 0x00ffffff /* Event count value */ 857 858#define PERF_THREAD_BITS 0x0f000000 /* Thread mask selects threads */ 859#define PERF_THREAD_S 24 860 861#define PERF_CTRL_BITS 0xf0000000 /* Event filter control */ 862#define PERF_CTRL_S 28 863 864#define PERFCTRL_SUPER 0 /* Superthread cycles */ 865#define PERFCTRL_REWIND 1 /* Rewinds due to Dcache Misses */ 866#ifdef METAC_2_1 867#define PERFCTRL_SUPREW 2 /* Rewinds of superthreaded cycles (no mask) */ 868 869#define PERFCTRL_CYCLES 3 /* Counts all cycles (no mask) */ 870 871#define PERFCTRL_PREDBC 4 /* Conditional branch predictions */ 872#define PERFCTRL_MISPBC 5 /* Conditional branch mispredictions */ 873#define PERFCTRL_PREDRT 6 /* Return predictions */ 874#define PERFCTRL_MISPRT 7 /* Return mispredictions */ 875#endif /* METAC_2_1 */ 876 877#define PERFCTRL_DHITS 8 /* Dcache Hits */ 878#define PERFCTRL_IHITS 9 /* Icache Hits */ 879#define PERFCTRL_IMISS 10 /* Icache Misses in cache or TLB */ 880#ifdef METAC_2_1 881#define PERFCTRL_DCSTALL 11 /* Dcache+TLB o/p delayed (per-thread) */ 882#define PERFCTRL_ICSTALL 12 /* Icache+TLB o/p delayed (per-thread) */ 883 884#define PERFCTRL_INT 13 /* Internal core detailed events (see next) */ 885#define PERFCTRL_EXT 15 /* External source in core periphery */ 886#endif /* METAC_2_1 */ 887 888#ifdef METAC_2_1 889/* These definitions replace the EXPAND_PERFCHANx register defines which are to 890 * be deprecated. 891 */ 892#define PERF_CHAN0 0x04830150 893#define PERF_CHAN1 0x04830158 894#define PERF_CHAN_BITS 0x0000000F 895#define PERF_CHAN_S 0 896#define PERFCHAN_WRC_WRBURST 0x0 /* Write combiner write burst */ 897#define PERFCHAN_WRC_WRITE 0x1 /* Write combiner write */ 898#define PERFCHAN_WRC_RDBURST 0x2 /* Write combiner read burst */ 899#define PERFCHAN_WRC_READ 0x3 /* Write combiner read */ 900#define PERFCHAN_PREARB_DELAY 0x4 /* Pre-arbiter delay cycle */ 901 /* Cross-bar hold-off cycle: */ 902#define PERFCHAN_XBAR_HOLDWRAP 0x5 /* wrapper register */ 903#define PERFCHAN_XBAR_HOLDSBUS 0x6 /* system bus (ATP only) */ 904#define PERFCHAN_XBAR_HOLDCREG 0x9 /* core registers */ 905#define PERFCHAN_L2C_MISS 0x6 /* L2 Cache miss */ 906#define PERFCHAN_L2C_HIT 0x7 /* L2 Cache hit */ 907#define PERFCHAN_L2C_WRITEBACK 0x8 /* L2 Cache writeback */ 908 /* Admission delay cycle: */ 909#define PERFCHAN_INPUT_CREG 0xB /* core registers */ 910#define PERFCHAN_INPUT_INTR 0xC /* internal ram */ 911#define PERFCHAN_INPUT_WRC 0xD /* write combiners(memory) */ 912 913/* Should following be removed as not in TRM anywhere? */ 914#define PERFCHAN_XBAR_HOLDINTR 0x8 /* internal ram */ 915#define PERFCHAN_INPUT_SBUS 0xA /* register port */ 916/* End of remove section. */ 917 918#define PERFCHAN_MAINARB_DELAY 0xF /* Main arbiter delay cycle */ 919 920#endif /* METAC_2_1 */ 921 922#ifdef METAC_2_1 923/* 924 * Write combiner registers 925 * ------------------------ 926 * 927 * These replace the EXPAND_T0WRCOMBINE register defines, which will be 928 * deprecated. 929 */ 930#define WRCOMB_CONFIG0 0x04830100 931#define WRCOMB_LFFEn_BIT 0x00004000 /* Enable auto line full flush */ 932#define WRCOMB_ENABLE_BIT 0x00002000 /* Enable write combiner */ 933#define WRCOMB_TIMEOUT_ENABLE_BIT 0x00001000 /* Timeout flush enable */ 934#define WRCOMB_TIMEOUT_COUNT_BITS 0x000003FF 935#define WRCOMB_TIMEOUT_COUNT_S 0 936#define WRCOMB_CONFIG4 0x04830180 937#define WRCOMB_PARTALLOC_BITS 0x000000C0 938#define WRCOMB_PARTALLOC_S 64 939#define WRCOMB_PARTSIZE_BITS 0x00000030 940#define WRCOMB_PARTSIZE_S 4 941#define WRCOMB_PARTOFFSET_BITS 0x0000000F 942#define WRCOMB_PARTOFFSET_S 0 943#define WRCOMB_CONFIG_STRIDE 8 944#endif /* METAC_2_1 */ 945 946#ifdef METAC_2_1 947/* 948 * Thread arbiter registers 949 * ------------------------ 950 * 951 * These replace the EXPAND_T0ARBITER register defines, which will be 952 * deprecated. 953 */ 954#define ARBITER_ARBCONFIG0 0x04830120 955#define ARBCFG_BPRIORITY_BIT 0x02000000 956#define ARBCFG_IPRIORITY_BIT 0x01000000 957#define ARBCFG_PAGE_BITS 0x00FF0000 958#define ARBCFG_PAGE_S 16 959#define ARBCFG_BBASE_BITS 0x0000FF00 960#define ARGCFG_BBASE_S 8 961#define ARBCFG_IBASE_BITS 0x000000FF 962#define ARBCFG_IBASE_S 0 963#define ARBITER_TTECONFIG0 0x04820160 964#define ARBTTE_IUPPER_BITS 0xFF000000 965#define ARBTTE_IUPPER_S 24 966#define ARBTTE_ILOWER_BITS 0x00FF0000 967#define ARBTTE_ILOWER_S 16 968#define ARBTTE_BUPPER_BITS 0x0000FF00 969#define ARBTTE_BUPPER_S 8 970#define ARBTTE_BLOWER_BITS 0x000000FF 971#define ARBTTE_BLOWER_S 0 972#define ARBITER_STRIDE 8 973#endif /* METAC_2_1 */ 974 975/* 976 * Expansion area registers 977 * -------------------------------------- 978 */ 979 980/* These defines are to be deprecated. See above instead. */ 981#define EXPAND_T0WRCOMBINE 0x03000000 982#ifdef METAC_2_1 983#define EXPWRC_LFFEn_BIT 0x00004000 /* Enable auto line full flush */ 984#endif /* METAC_2_1 */ 985#define EXPWRC_ENABLE_BIT 0x00002000 /* Enable write combiner */ 986#define EXPWRC_TIMEOUT_ENABLE_BIT 0x00001000 /* Timeout flush enable */ 987#define EXPWRC_TIMEOUT_COUNT_BITS 0x000003FF 988#define EXPWRC_TIMEOUT_COUNT_S 0 989#define EXPAND_TnWRCOMBINE_STRIDE 0x00000008 990 991/* These defines are to be deprecated. See above instead. */ 992#define EXPAND_T0ARBITER 0x03000020 993#define EXPARB_BPRIORITY_BIT 0x02000000 994#define EXPARB_IPRIORITY_BIT 0x01000000 995#define EXPARB_PAGE_BITS 0x00FF0000 996#define EXPARB_PAGE_S 16 997#define EXPARB_BBASE_BITS 0x0000FF00 998#define EXPARB_BBASE_S 8 999#define EXPARB_IBASE_BITS 0x000000FF 1000#define EXPARB_IBASE_S 0
1001#define EXPAND_TnARBITER_STRIDE 0x00000008 1002 1003/* These definitions are to be deprecated. See above instead. */ 1004#define EXPAND_TIMER_DIV 0x03000040 1005#define EXPTIM_DIV_BITS 0x000000FF 1006#define EXPTIM_DIV_S 0 1007 1008/* These definitions are to be deprecated. See above instead. */ 1009#define EXPAND_PERFCHAN0 0x03000050 1010#define EXPAND_PERFCHAN1 0x03000058 1011#define EXPPERF_CTRL_BITS 0x0000000F 1012#define EXPPERF_CTRL_S 0 1013#define EXPPERF_WRC_WRBURST 0x0 /* Write combiner write burst */ 1014#define EXPPERF_WRC_WRITE 0x1 /* Write combiner write */ 1015#define EXPPERF_WRC_RDBURST 0x2 /* Write combiner read burst */ 1016#define EXPPERF_WRC_READ 0x3 /* Write combiner read */ 1017#define EXPPERF_PREARB_DELAY 0x4 /* Pre-arbiter delay cycle */ 1018 /* Cross-bar hold-off cycle: */ 1019#define EXPPERF_XBAR_HOLDWRAP 0x5 /* wrapper register */ 1020#define EXPPERF_XBAR_HOLDSBUS 0x6 /* system bus */ 1021#ifdef METAC_1_2 1022#define EXPPERF_XBAR_HOLDLBUS 0x7 /* local bus */ 1023#else /* METAC_1_2 */ 1024#define EXPPERF_XBAR_HOLDINTR 0x8 /* internal ram */ 1025#define EXPPERF_XBAR_HOLDCREG 0x9 /* core registers */ 1026 /* Admission delay cycle: */ 1027#define EXPPERF_INPUT_SBUS 0xA /* register port */ 1028#define EXPPERF_INPUT_CREG 0xB /* core registers */ 1029#define EXPPERF_INPUT_INTR 0xC /* internal ram */ 1030#define EXPPERF_INPUT_WRC 0xD /* write combiners(memory) */ 1031#endif /* !METAC_1_2 */ 1032#define EXPPERF_MAINARB_DELAY 0xF /* Main arbiter delay cycle */ 1033 1034/* 1035 * Debug port registers 1036 * -------------------------------------- 1037 */ 1038 1039/* Data Exchange Register */ 1040#define DBGPORT_MDBGDATAX 0x0 1041 1042/* Data Transfer register */ 1043#define DBGPORT_MDBGDATAT 0x4 1044 1045/* Control Register 0 */ 1046#define DBGPORT_MDBGCTRL0 0x8 1047#define DBGPORT_MDBGCTRL0_ADDR_BITS 0xFFFFFFFC 1048#define DBGPORT_MDBGCTRL0_ADDR_S 2 1049#define DBGPORT_MDBGCTRL0_AUTOINCR_BIT 0x00000002 1050#define DBGPORT_MDBGCTRL0_RD_BIT 0x00000001 1051 1052/* Control Register 1 */ 1053#define DBGPORT_MDBGCTRL1 0xC 1054#ifdef METAC_2_1 1055#define DBGPORT_MDBGCTRL1_DEFERRTHREAD_BITS 0xC0000000 1056#define DBGPORT_MDBGCTRL1_DEFERRTHREAD_S 30 1057#endif /* METAC_2_1 */ 1058#define DBGPORT_MDBGCTRL1_LOCK2_INTERLOCK_BIT 0x20000000 1059#define DBGPORT_MDBGCTRL1_ATOMIC_INTERLOCK_BIT 0x10000000 1060#define DBGPORT_MDBGCTRL1_TRIGSTATUS_BIT 0x08000000 1061#define DBGPORT_MDBGCTRL1_GBLPORT_IDLE_BIT 0x04000000 1062#define DBGPORT_MDBGCTRL1_COREMEM_IDLE_BIT 0x02000000 1063#define DBGPORT_MDBGCTRL1_READY_BIT 0x01000000 1064#ifdef METAC_2_1 1065#define DBGPORT_MDBGCTRL1_DEFERRID_BITS 0x00E00000 1066#define DBGPORT_MDBGCTRL1_DEFERRID_S 21 1067#define DBGPORT_MDBGCTRL1_DEFERR_BIT 0x00100000 1068#endif /* METAC_2_1 */ 1069#define DBGPORT_MDBGCTRL1_WR_ACTIVE_BIT 0x00040000 1070#define DBGPORT_MDBGCTRL1_COND_LOCK2_BIT 0x00020000 1071#define DBGPORT_MDBGCTRL1_LOCK2_BIT 0x00010000 1072#define DBGPORT_MDBGCTRL1_DIAGNOSE_BIT 0x00008000 1073#define DBGPORT_MDBGCTRL1_FORCEDIAG_BIT 0x00004000 1074#define DBGPORT_MDBGCTRL1_MEMFAULT_BITS 0x00003000 1075#define DBGPORT_MDBGCTRL1_MEMFAULT_S 12 1076#define DBGPORT_MDBGCTRL1_TRIGGER_BIT 0x00000100 1077#ifdef METAC_2_1 1078#define DBGPORT_MDBGCTRL1_INTSPECIAL_BIT 0x00000080 1079#define DBGPORT_MDBGCTRL1_INTRUSIVE_BIT 0x00000040 1080#endif /* METAC_2_1 */ 1081#define DBGPORT_MDBGCTRL1_THREAD_BITS 0x00000030 /* Thread mask selects threads */ 1082#define DBGPORT_MDBGCTRL1_THREAD_S 4 1083#define DBGPORT_MDBGCTRL1_TRANS_SIZE_BITS 0x0000000C 1084#define DBGPORT_MDBGCTRL1_TRANS_SIZE_S 2 1085#define DBGPORT_MDBGCTRL1_TRANS_SIZE_32_BIT 0x00000000 1086#define DBGPORT_MDBGCTRL1_TRANS_SIZE_16_BIT 0x00000004 1087#define DBGPORT_MDBGCTRL1_TRANS_SIZE_8_BIT 0x00000008 1088#define DBGPORT_MDBGCTRL1_BYTE_ROUND_BITS 0x00000003 1089#define DBGPORT_MDBGCTRL1_BYTE_ROUND_S 0 1090#define DBGPORT_MDBGCTRL1_BYTE_ROUND_8_BIT 0x00000001 1091#define DBGPORT_MDBGCTRL1_BYTE_ROUND_16_BIT 0x00000002 1092 1093 1094/* L2 Cache registers */ 1095#define SYSC_L2C_INIT 0x048300C0 1096#define SYSC_L2C_INIT_INIT 1 1097#define SYSC_L2C_INIT_IN_PROGRESS 0 1098#define SYSC_L2C_INIT_COMPLETE 1 1099 1100#define SYSC_L2C_ENABLE 0x048300D0 1101#define SYSC_L2C_ENABLE_ENABLE_BIT 0x00000001 1102#define SYSC_L2C_ENABLE_PFENABLE_BIT 0x00000002 1103 1104#define SYSC_L2C_PURGE 0x048300C8 1105#define SYSC_L2C_PURGE_PURGE 1 1106#define SYSC_L2C_PURGE_IN_PROGRESS 0 1107#define SYSC_L2C_PURGE_COMPLETE 1 1108 1109#endif /* _ASM_METAG_MEM_H_ */ 1110