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19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/string.h>
22#include <linux/init.h>
23#include <linux/bootmem.h>
24#include <linux/mm.h>
25#include <linux/list.h>
26#include <linux/syscalls.h>
27#include <linux/irq.h>
28#include <linux/vmalloc.h>
29#include <linux/slab.h>
30#include <linux/of.h>
31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/of_pci.h>
34#include <linux/export.h>
35
36#include <asm/processor.h>
37#include <linux/io.h>
38#include <asm/pci-bridge.h>
39#include <asm/byteorder.h>
40
41static DEFINE_SPINLOCK(hose_spinlock);
42LIST_HEAD(hose_list);
43
44
45static int global_phb_number;
46
47
48resource_size_t isa_mem_base;
49
50unsigned long isa_io_base;
51EXPORT_SYMBOL(isa_io_base);
52
53static int pci_bus_count;
54
55struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
56{
57 struct pci_controller *phb;
58
59 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
60 if (!phb)
61 return NULL;
62 spin_lock(&hose_spinlock);
63 phb->global_number = global_phb_number++;
64 list_add_tail(&phb->list_node, &hose_list);
65 spin_unlock(&hose_spinlock);
66 phb->dn = dev;
67 phb->is_dynamic = mem_init_done;
68 return phb;
69}
70
71void pcibios_free_controller(struct pci_controller *phb)
72{
73 spin_lock(&hose_spinlock);
74 list_del(&phb->list_node);
75 spin_unlock(&hose_spinlock);
76
77 if (phb->is_dynamic)
78 kfree(phb);
79}
80
81static resource_size_t pcibios_io_size(const struct pci_controller *hose)
82{
83 return resource_size(&hose->io_resource);
84}
85
86int pcibios_vaddr_is_ioport(void __iomem *address)
87{
88 int ret = 0;
89 struct pci_controller *hose;
90 resource_size_t size;
91
92 spin_lock(&hose_spinlock);
93 list_for_each_entry(hose, &hose_list, list_node) {
94 size = pcibios_io_size(hose);
95 if (address >= hose->io_base_virt &&
96 address < (hose->io_base_virt + size)) {
97 ret = 1;
98 break;
99 }
100 }
101 spin_unlock(&hose_spinlock);
102 return ret;
103}
104
105unsigned long pci_address_to_pio(phys_addr_t address)
106{
107 struct pci_controller *hose;
108 resource_size_t size;
109 unsigned long ret = ~0;
110
111 spin_lock(&hose_spinlock);
112 list_for_each_entry(hose, &hose_list, list_node) {
113 size = pcibios_io_size(hose);
114 if (address >= hose->io_base_phys &&
115 address < (hose->io_base_phys + size)) {
116 unsigned long base =
117 (unsigned long)hose->io_base_virt - _IO_BASE;
118 ret = base + (address - hose->io_base_phys);
119 break;
120 }
121 }
122 spin_unlock(&hose_spinlock);
123
124 return ret;
125}
126EXPORT_SYMBOL_GPL(pci_address_to_pio);
127
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132
133
134
135struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
136{
137 while (node) {
138 struct pci_controller *hose, *tmp;
139 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
140 if (hose->dn == node)
141 return hose;
142 node = node->parent;
143 }
144 return NULL;
145}
146
147void __weak pcibios_set_master(struct pci_dev *dev)
148{
149
150}
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168
169static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
170 resource_size_t *offset,
171 enum pci_mmap_state mmap_state)
172{
173 struct pci_controller *hose = pci_bus_to_host(dev->bus);
174 unsigned long io_offset = 0;
175 int i, res_bit;
176
177 if (!hose)
178 return NULL;
179
180
181 if (mmap_state == pci_mmap_mem) {
182#if 0
183 *offset += hose->pci_mem_offset;
184#endif
185 res_bit = IORESOURCE_MEM;
186 } else {
187 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
188 *offset += io_offset;
189 res_bit = IORESOURCE_IO;
190 }
191
192
193
194
195
196 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
197 struct resource *rp = &dev->resource[i];
198 int flags = rp->flags;
199
200
201 if (i == PCI_ROM_RESOURCE)
202 flags |= IORESOURCE_MEM;
203
204
205 if ((flags & res_bit) == 0)
206 continue;
207
208
209 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
210 continue;
211
212
213 if (mmap_state == pci_mmap_io)
214 *offset += hose->io_base_phys - io_offset;
215 return rp;
216 }
217
218 return NULL;
219}
220
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224
225
226pgprot_t pci_phys_mem_access_prot(struct file *file,
227 unsigned long pfn,
228 unsigned long size,
229 pgprot_t prot)
230{
231 struct pci_dev *pdev = NULL;
232 struct resource *found = NULL;
233 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
234 int i;
235
236 if (page_is_ram(pfn))
237 return prot;
238
239 prot = pgprot_noncached(prot);
240 for_each_pci_dev(pdev) {
241 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
242 struct resource *rp = &pdev->resource[i];
243 int flags = rp->flags;
244
245
246 if ((flags & IORESOURCE_MEM) == 0)
247 continue;
248
249 if (offset < (rp->start & PAGE_MASK) ||
250 offset > rp->end)
251 continue;
252 found = rp;
253 break;
254 }
255 if (found)
256 break;
257 }
258 if (found) {
259 if (found->flags & IORESOURCE_PREFETCH)
260 prot = pgprot_noncached_wc(prot);
261 pci_dev_put(pdev);
262 }
263
264 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
265 (unsigned long long)offset, pgprot_val(prot));
266
267 return prot;
268}
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279
280int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
281 enum pci_mmap_state mmap_state, int write_combine)
282{
283 resource_size_t offset =
284 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
285 struct resource *rp;
286 int ret;
287
288 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
289 if (rp == NULL)
290 return -EINVAL;
291
292 vma->vm_pgoff = offset >> PAGE_SHIFT;
293 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
294
295 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
296 vma->vm_end - vma->vm_start, vma->vm_page_prot);
297
298 return ret;
299}
300
301
302int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
303{
304 unsigned long offset;
305 struct pci_controller *hose = pci_bus_to_host(bus);
306 struct resource *rp = &hose->io_resource;
307 void __iomem *addr;
308
309
310
311
312
313
314 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
315 offset += port;
316
317 if (!(rp->flags & IORESOURCE_IO))
318 return -ENXIO;
319 if (offset < rp->start || (offset + size) > rp->end)
320 return -ENXIO;
321 addr = hose->io_base_virt + port;
322
323 switch (size) {
324 case 1:
325 *((u8 *)val) = in_8(addr);
326 return 1;
327 case 2:
328 if (port & 1)
329 return -EINVAL;
330 *((u16 *)val) = in_le16(addr);
331 return 2;
332 case 4:
333 if (port & 3)
334 return -EINVAL;
335 *((u32 *)val) = in_le32(addr);
336 return 4;
337 }
338 return -EINVAL;
339}
340
341
342int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
343{
344 unsigned long offset;
345 struct pci_controller *hose = pci_bus_to_host(bus);
346 struct resource *rp = &hose->io_resource;
347 void __iomem *addr;
348
349
350
351
352
353
354 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
355 offset += port;
356
357 if (!(rp->flags & IORESOURCE_IO))
358 return -ENXIO;
359 if (offset < rp->start || (offset + size) > rp->end)
360 return -ENXIO;
361 addr = hose->io_base_virt + port;
362
363
364
365
366
367
368 switch (size) {
369 case 1:
370 out_8(addr, val >> 24);
371 return 1;
372 case 2:
373 if (port & 1)
374 return -EINVAL;
375 out_le16(addr, val >> 16);
376 return 2;
377 case 4:
378 if (port & 3)
379 return -EINVAL;
380 out_le32(addr, val);
381 return 4;
382 }
383 return -EINVAL;
384}
385
386
387int pci_mmap_legacy_page_range(struct pci_bus *bus,
388 struct vm_area_struct *vma,
389 enum pci_mmap_state mmap_state)
390{
391 struct pci_controller *hose = pci_bus_to_host(bus);
392 resource_size_t offset =
393 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
394 resource_size_t size = vma->vm_end - vma->vm_start;
395 struct resource *rp;
396
397 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
398 pci_domain_nr(bus), bus->number,
399 mmap_state == pci_mmap_mem ? "MEM" : "IO",
400 (unsigned long long)offset,
401 (unsigned long long)(offset + size - 1));
402
403 if (mmap_state == pci_mmap_mem) {
404
405
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410
411 if ((offset + size) > hose->isa_mem_size) {
412#ifdef CONFIG_MMU
413 pr_debug("Process %s (pid:%d) mapped non-existing PCI",
414 current->comm, current->pid);
415 pr_debug("legacy memory for 0%04x:%02x\n",
416 pci_domain_nr(bus), bus->number);
417#endif
418 if (vma->vm_flags & VM_SHARED)
419 return shmem_zero_setup(vma);
420 return 0;
421 }
422 offset += hose->isa_mem_phys;
423 } else {
424 unsigned long io_offset = (unsigned long)hose->io_base_virt -
425 _IO_BASE;
426 unsigned long roffset = offset + io_offset;
427 rp = &hose->io_resource;
428 if (!(rp->flags & IORESOURCE_IO))
429 return -ENXIO;
430 if (roffset < rp->start || (roffset + size) > rp->end)
431 return -ENXIO;
432 offset += hose->io_base_phys;
433 }
434 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
435
436 vma->vm_pgoff = offset >> PAGE_SHIFT;
437 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
438 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
439 vma->vm_end - vma->vm_start,
440 vma->vm_page_prot);
441}
442
443void pci_resource_to_user(const struct pci_dev *dev, int bar,
444 const struct resource *rsrc,
445 resource_size_t *start, resource_size_t *end)
446{
447 struct pci_bus_region region;
448
449 if (rsrc->flags & IORESOURCE_IO) {
450 pcibios_resource_to_bus(dev->bus, ®ion,
451 (struct resource *) rsrc);
452 *start = region.start;
453 *end = region.end;
454 return;
455 }
456
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460
461
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463
464 *start = rsrc->start;
465 *end = rsrc->end;
466}
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501void pci_process_bridge_OF_ranges(struct pci_controller *hose,
502 struct device_node *dev, int primary)
503{
504 int memno = 0, isa_hole = -1;
505 unsigned long long isa_mb = 0;
506 struct resource *res;
507 struct of_pci_range range;
508 struct of_pci_range_parser parser;
509
510 pr_info("PCI host bridge %s %s ranges:\n",
511 dev->full_name, primary ? "(primary)" : "");
512
513
514 if (of_pci_range_parser_init(&parser, dev))
515 return;
516
517 pr_debug("Parsing ranges property...\n");
518 for_each_of_pci_range(&parser, &range) {
519
520 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ",
521 range.pci_space, range.pci_addr);
522 pr_debug("cpu_addr:0x%016llx size:0x%016llx\n",
523 range.cpu_addr, range.size);
524
525
526
527
528
529
530 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
531 continue;
532
533
534 res = NULL;
535 switch (range.flags & IORESOURCE_TYPE_BITS) {
536 case IORESOURCE_IO:
537 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
538 range.cpu_addr, range.cpu_addr + range.size - 1,
539 range.pci_addr);
540
541
542 if (hose->pci_io_size) {
543 pr_info(" \\--> Skipped (too many) !\n");
544 continue;
545 }
546
547 if (range.size > 0x01000000)
548 range.size = 0x01000000;
549
550
551 hose->io_base_virt = ioremap(range.cpu_addr,
552 range.size);
553
554
555 if (primary)
556 isa_io_base =
557 (unsigned long)hose->io_base_virt;
558
559
560
561 hose->pci_io_size = range.pci_addr + range.size;
562 hose->io_base_phys = range.cpu_addr - range.pci_addr;
563
564
565 res = &hose->io_resource;
566 range.cpu_addr = range.pci_addr;
567
568 break;
569 case IORESOURCE_MEM:
570 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
571 range.cpu_addr, range.cpu_addr + range.size - 1,
572 range.pci_addr,
573 (range.pci_space & 0x40000000) ?
574 "Prefetch" : "");
575
576
577 if (memno >= 3) {
578 pr_info(" \\--> Skipped (too many) !\n");
579 continue;
580 }
581
582 if (range.pci_addr == 0) {
583 isa_mb = range.cpu_addr;
584 isa_hole = memno;
585 if (primary || isa_mem_base == 0)
586 isa_mem_base = range.cpu_addr;
587 hose->isa_mem_phys = range.cpu_addr;
588 hose->isa_mem_size = range.size;
589 }
590
591
592
593
594
595 if (memno == 0 ||
596 (isa_hole >= 0 && range.pci_addr != 0 &&
597 hose->pci_mem_offset == isa_mb))
598 hose->pci_mem_offset = range.cpu_addr -
599 range.pci_addr;
600 else if (range.pci_addr != 0 &&
601 hose->pci_mem_offset != range.cpu_addr -
602 range.pci_addr) {
603 pr_info(" \\--> Skipped (offset mismatch) !\n");
604 continue;
605 }
606
607
608 res = &hose->mem_resources[memno++];
609 break;
610 }
611 if (res != NULL) {
612 res->name = dev->full_name;
613 res->flags = range.flags;
614 res->start = range.cpu_addr;
615 res->end = range.cpu_addr + range.size - 1;
616 res->parent = res->child = res->sibling = NULL;
617 }
618 }
619
620
621
622
623
624 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
625 unsigned int next = isa_hole + 1;
626 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
627 if (next < memno)
628 memmove(&hose->mem_resources[isa_hole],
629 &hose->mem_resources[next],
630 sizeof(struct resource) * (memno - next));
631 hose->mem_resources[--memno].flags = 0;
632 }
633}
634
635
636int pci_proc_domain(struct pci_bus *bus)
637{
638 return pci_domain_nr(bus);
639}
640
641
642
643
644static void pcibios_fixup_resources(struct pci_dev *dev)
645{
646
647}
648DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
649
650
651
652
653
654
655static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
656 struct resource *res)
657{
658 struct pci_controller *hose = pci_bus_to_host(bus);
659 struct pci_dev *dev = bus->self;
660 resource_size_t offset;
661 u16 command;
662 int i;
663
664
665 if (res->flags & IORESOURCE_MEM) {
666
667
668
669 if (res->start != hose->pci_mem_offset)
670 return 0;
671
672
673
674
675 pci_read_config_word(dev, PCI_COMMAND, &command);
676 if ((command & PCI_COMMAND_MEMORY) == 0)
677 return 1;
678
679
680
681
682
683 for (i = 0; i < 3; i++) {
684 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
685 hose->mem_resources[i].start == hose->pci_mem_offset)
686 return 0;
687 }
688
689
690
691
692 return 1;
693 } else {
694
695 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
696 if (((res->start - offset) & 0xfffffffful) != 0)
697 return 0;
698
699
700
701
702
703
704
705 pci_read_config_word(dev, PCI_COMMAND, &command);
706 if (command & PCI_COMMAND_IO)
707 return 0;
708
709
710
711
712 return 1;
713 }
714}
715
716
717static void pcibios_fixup_bridge(struct pci_bus *bus)
718{
719 struct resource *res;
720 int i;
721
722 struct pci_dev *dev = bus->self;
723
724 pci_bus_for_each_resource(bus, res, i) {
725 if (!res)
726 continue;
727 if (!res->flags)
728 continue;
729 if (i >= 3 && bus->self->transparent)
730 continue;
731
732 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
733 pci_name(dev), i,
734 (unsigned long long)res->start,
735 (unsigned long long)res->end,
736 (unsigned int)res->flags);
737
738
739
740
741 if (pcibios_uninitialized_bridge_resource(bus, res)) {
742 res->flags = 0;
743 pr_debug("PCI:%s (unassigned)\n",
744 pci_name(dev));
745 } else {
746 pr_debug("PCI:%s %016llx-%016llx\n",
747 pci_name(dev),
748 (unsigned long long)res->start,
749 (unsigned long long)res->end);
750 }
751 }
752}
753
754void pcibios_setup_bus_self(struct pci_bus *bus)
755{
756
757 if (bus->self != NULL)
758 pcibios_fixup_bridge(bus);
759}
760
761void pcibios_setup_bus_devices(struct pci_bus *bus)
762{
763 struct pci_dev *dev;
764
765 pr_debug("PCI: Fixup bus devices %d (%s)\n",
766 bus->number, bus->self ? pci_name(bus->self) : "PHB");
767
768 list_for_each_entry(dev, &bus->devices, bus_list) {
769
770 dev->dev.of_node = pci_device_to_OF_node(dev);
771
772
773
774
775 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
776
777
778 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
779 }
780}
781
782void pcibios_fixup_bus(struct pci_bus *bus)
783{
784
785}
786EXPORT_SYMBOL(pcibios_fixup_bus);
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800
801resource_size_t pcibios_align_resource(void *data, const struct resource *res,
802 resource_size_t size, resource_size_t align)
803{
804 return res->start;
805}
806EXPORT_SYMBOL(pcibios_align_resource);
807
808int pcibios_add_device(struct pci_dev *dev)
809{
810 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
811
812 return 0;
813}
814EXPORT_SYMBOL(pcibios_add_device);
815
816
817
818
819
820static int __init reparent_resources(struct resource *parent,
821 struct resource *res)
822{
823 struct resource *p, **pp;
824 struct resource **firstpp = NULL;
825
826 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
827 if (p->end < res->start)
828 continue;
829 if (res->end < p->start)
830 break;
831 if (p->start < res->start || p->end > res->end)
832 return -1;
833 if (firstpp == NULL)
834 firstpp = pp;
835 }
836 if (firstpp == NULL)
837 return -1;
838 res->parent = parent;
839 res->child = *firstpp;
840 res->sibling = *pp;
841 *firstpp = res;
842 *pp = NULL;
843 for (p = res->child; p != NULL; p = p->sibling) {
844 p->parent = res;
845 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
846 p->name,
847 (unsigned long long)p->start,
848 (unsigned long long)p->end, res->name);
849 }
850 return 0;
851}
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886static void pcibios_allocate_bus_resources(struct pci_bus *bus)
887{
888 struct pci_bus *b;
889 int i;
890 struct resource *res, *pr;
891
892 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
893 pci_domain_nr(bus), bus->number);
894
895 pci_bus_for_each_resource(bus, res, i) {
896 if (!res || !res->flags
897 || res->start > res->end || res->parent)
898 continue;
899 if (bus->parent == NULL)
900 pr = (res->flags & IORESOURCE_IO) ?
901 &ioport_resource : &iomem_resource;
902 else {
903
904
905
906
907
908
909 pr = pci_find_parent_resource(bus->self, res);
910 if (pr == res) {
911
912
913
914
915 continue;
916 }
917 }
918
919 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
920 bus->self ? pci_name(bus->self) : "PHB",
921 bus->number, i,
922 (unsigned long long)res->start,
923 (unsigned long long)res->end);
924 pr_debug("[0x%x], parent %p (%s)\n",
925 (unsigned int)res->flags,
926 pr, (pr && pr->name) ? pr->name : "nil");
927
928 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
929 struct pci_dev *dev = bus->self;
930
931 if (request_resource(pr, res) == 0)
932 continue;
933
934
935
936
937
938 if (reparent_resources(pr, res) == 0)
939 continue;
940
941 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
942 pci_claim_bridge_resource(dev,
943 i + PCI_BRIDGE_RESOURCES) == 0)
944 continue;
945
946 }
947 pr_warn("PCI: Cannot allocate resource region ");
948 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
949 res->start = res->end = 0;
950 res->flags = 0;
951 }
952
953 list_for_each_entry(b, &bus->children, node)
954 pcibios_allocate_bus_resources(b);
955}
956
957static inline void alloc_resource(struct pci_dev *dev, int idx)
958{
959 struct resource *pr, *r = &dev->resource[idx];
960
961 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
962 pci_name(dev), idx,
963 (unsigned long long)r->start,
964 (unsigned long long)r->end,
965 (unsigned int)r->flags);
966
967 pr = pci_find_parent_resource(dev, r);
968 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
969 request_resource(pr, r) < 0) {
970 pr_warn("PCI: Cannot allocate resource region %d ", idx);
971 pr_cont("of device %s, will remap\n", pci_name(dev));
972 if (pr)
973 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
974 pr,
975 (unsigned long long)pr->start,
976 (unsigned long long)pr->end,
977 (unsigned int)pr->flags);
978
979 r->flags |= IORESOURCE_UNSET;
980 r->end -= r->start;
981 r->start = 0;
982 }
983}
984
985static void __init pcibios_allocate_resources(int pass)
986{
987 struct pci_dev *dev = NULL;
988 int idx, disabled;
989 u16 command;
990 struct resource *r;
991
992 for_each_pci_dev(dev) {
993 pci_read_config_word(dev, PCI_COMMAND, &command);
994 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
995 r = &dev->resource[idx];
996 if (r->parent)
997 continue;
998 if (!r->flags || (r->flags & IORESOURCE_UNSET))
999 continue;
1000
1001
1002
1003 if (idx == PCI_ROM_RESOURCE)
1004 disabled = 1;
1005 if (r->flags & IORESOURCE_IO)
1006 disabled = !(command & PCI_COMMAND_IO);
1007 else
1008 disabled = !(command & PCI_COMMAND_MEMORY);
1009 if (pass == disabled)
1010 alloc_resource(dev, idx);
1011 }
1012 if (pass)
1013 continue;
1014 r = &dev->resource[PCI_ROM_RESOURCE];
1015 if (r->flags) {
1016
1017
1018
1019 u32 reg;
1020 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1021 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1022 pr_debug("PCI: Switching off ROM of %s\n",
1023 pci_name(dev));
1024 r->flags &= ~IORESOURCE_ROM_ENABLE;
1025 pci_write_config_dword(dev, dev->rom_base_reg,
1026 reg & ~PCI_ROM_ADDRESS_ENABLE);
1027 }
1028 }
1029 }
1030}
1031
1032static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1033{
1034 struct pci_controller *hose = pci_bus_to_host(bus);
1035 resource_size_t offset;
1036 struct resource *res, *pres;
1037 int i;
1038
1039 pr_debug("Reserving legacy ranges for domain %04x\n",
1040 pci_domain_nr(bus));
1041
1042
1043 if (!(hose->io_resource.flags & IORESOURCE_IO))
1044 goto no_io;
1045 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1046 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1047 BUG_ON(res == NULL);
1048 res->name = "Legacy IO";
1049 res->flags = IORESOURCE_IO;
1050 res->start = offset;
1051 res->end = (offset + 0xfff) & 0xfffffffful;
1052 pr_debug("Candidate legacy IO: %pR\n", res);
1053 if (request_resource(&hose->io_resource, res)) {
1054 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1055 pci_domain_nr(bus), bus->number, res);
1056 kfree(res);
1057 }
1058
1059 no_io:
1060
1061 offset = hose->pci_mem_offset;
1062 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1063 for (i = 0; i < 3; i++) {
1064 pres = &hose->mem_resources[i];
1065 if (!(pres->flags & IORESOURCE_MEM))
1066 continue;
1067 pr_debug("hose mem res: %pR\n", pres);
1068 if ((pres->start - offset) <= 0xa0000 &&
1069 (pres->end - offset) >= 0xbffff)
1070 break;
1071 }
1072 if (i >= 3)
1073 return;
1074 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1075 BUG_ON(res == NULL);
1076 res->name = "Legacy VGA memory";
1077 res->flags = IORESOURCE_MEM;
1078 res->start = 0xa0000 + offset;
1079 res->end = 0xbffff + offset;
1080 pr_debug("Candidate VGA memory: %pR\n", res);
1081 if (request_resource(pres, res)) {
1082 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1083 pci_domain_nr(bus), bus->number, res);
1084 kfree(res);
1085 }
1086}
1087
1088void __init pcibios_resource_survey(void)
1089{
1090 struct pci_bus *b;
1091
1092
1093
1094
1095 list_for_each_entry(b, &pci_root_buses, node)
1096 pcibios_allocate_bus_resources(b);
1097
1098 pcibios_allocate_resources(0);
1099 pcibios_allocate_resources(1);
1100
1101
1102
1103
1104
1105 list_for_each_entry(b, &pci_root_buses, node)
1106 pcibios_reserve_legacy_regions(b);
1107
1108
1109 pr_debug("PCI: Assigning unassigned resources...\n");
1110 pci_assign_unassigned_resources();
1111}
1112
1113
1114
1115
1116
1117
1118void pcibios_claim_one_bus(struct pci_bus *bus)
1119{
1120 struct pci_dev *dev;
1121 struct pci_bus *child_bus;
1122
1123 list_for_each_entry(dev, &bus->devices, bus_list) {
1124 int i;
1125
1126 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1127 struct resource *r = &dev->resource[i];
1128
1129 if (r->parent || !r->start || !r->flags)
1130 continue;
1131
1132 pr_debug("PCI: Claiming %s: ", pci_name(dev));
1133 pr_debug("Resource %d: %016llx..%016llx [%x]\n",
1134 i, (unsigned long long)r->start,
1135 (unsigned long long)r->end,
1136 (unsigned int)r->flags);
1137
1138 if (pci_claim_resource(dev, i) == 0)
1139 continue;
1140
1141 pci_claim_bridge_resource(dev, i);
1142 }
1143 }
1144
1145 list_for_each_entry(child_bus, &bus->children, node)
1146 pcibios_claim_one_bus(child_bus);
1147}
1148EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1149
1150
1151
1152
1153
1154
1155
1156
1157void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1158{
1159 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1160 pci_domain_nr(bus), bus->number);
1161
1162
1163 pcibios_allocate_bus_resources(bus);
1164 pcibios_claim_one_bus(bus);
1165
1166
1167 pci_bus_add_devices(bus);
1168
1169
1170
1171}
1172EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1173
1174static void pcibios_setup_phb_resources(struct pci_controller *hose,
1175 struct list_head *resources)
1176{
1177 unsigned long io_offset;
1178 struct resource *res;
1179 int i;
1180
1181
1182 res = &hose->io_resource;
1183
1184
1185 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1186 res->start = (res->start + io_offset) & 0xffffffffu;
1187 res->end = (res->end + io_offset) & 0xffffffffu;
1188
1189 if (!res->flags) {
1190 pr_warn("PCI: I/O resource not set for host ");
1191 pr_cont("bridge %s (domain %d)\n",
1192 hose->dn->full_name, hose->global_number);
1193
1194 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1195 res->end = res->start + IO_SPACE_LIMIT;
1196 res->flags = IORESOURCE_IO;
1197 }
1198 pci_add_resource_offset(resources, res,
1199 (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
1200
1201 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1202 (unsigned long long)res->start,
1203 (unsigned long long)res->end,
1204 (unsigned long)res->flags);
1205
1206
1207 for (i = 0; i < 3; ++i) {
1208 res = &hose->mem_resources[i];
1209 if (!res->flags) {
1210 if (i > 0)
1211 continue;
1212 pr_err("PCI: Memory resource 0 not set for ");
1213 pr_cont("host bridge %s (domain %d)\n",
1214 hose->dn->full_name, hose->global_number);
1215
1216
1217 res->start = hose->pci_mem_offset;
1218 res->end = (resource_size_t)-1LL;
1219 res->flags = IORESOURCE_MEM;
1220
1221 }
1222 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
1223
1224 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1225 i, (unsigned long long)res->start,
1226 (unsigned long long)res->end,
1227 (unsigned long)res->flags);
1228 }
1229
1230 pr_debug("PCI: PHB MEM offset = %016llx\n",
1231 (unsigned long long)hose->pci_mem_offset);
1232 pr_debug("PCI: PHB IO offset = %08lx\n",
1233 (unsigned long)hose->io_base_virt - _IO_BASE);
1234}
1235
1236static void pcibios_scan_phb(struct pci_controller *hose)
1237{
1238 LIST_HEAD(resources);
1239 struct pci_bus *bus;
1240 struct device_node *node = hose->dn;
1241
1242 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1243
1244 pcibios_setup_phb_resources(hose, &resources);
1245
1246 bus = pci_scan_root_bus(hose->parent, hose->first_busno,
1247 hose->ops, hose, &resources);
1248 if (bus == NULL) {
1249 pr_err("Failed to create bus for PCI domain %04x\n",
1250 hose->global_number);
1251 pci_free_resource_list(&resources);
1252 return;
1253 }
1254 bus->busn_res.start = hose->first_busno;
1255 hose->bus = bus;
1256
1257 hose->last_busno = bus->busn_res.end;
1258}
1259
1260static int __init pcibios_init(void)
1261{
1262 struct pci_controller *hose, *tmp;
1263 int next_busno = 0;
1264
1265 pr_info("PCI: Probing PCI hardware\n");
1266
1267
1268 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1269 hose->last_busno = 0xff;
1270 pcibios_scan_phb(hose);
1271 if (next_busno <= hose->last_busno)
1272 next_busno = hose->last_busno + 1;
1273 }
1274 pci_bus_count = next_busno;
1275
1276
1277 pcibios_resource_survey();
1278 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1279 if (hose->bus)
1280 pci_bus_add_devices(hose->bus);
1281 }
1282
1283 return 0;
1284}
1285
1286subsys_initcall(pcibios_init);
1287
1288static struct pci_controller *pci_bus_to_hose(int bus)
1289{
1290 struct pci_controller *hose, *tmp;
1291
1292 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1293 if (bus >= hose->first_busno && bus <= hose->last_busno)
1294 return hose;
1295 return NULL;
1296}
1297
1298
1299
1300
1301
1302
1303
1304long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1305{
1306 struct pci_controller *hose;
1307 long result = -EOPNOTSUPP;
1308
1309 hose = pci_bus_to_hose(bus);
1310 if (!hose)
1311 return -ENODEV;
1312
1313 switch (which) {
1314 case IOBASE_BRIDGE_NUMBER:
1315 return (long)hose->first_busno;
1316 case IOBASE_MEMORY:
1317 return (long)hose->pci_mem_offset;
1318 case IOBASE_IO:
1319 return (long)hose->io_base_phys;
1320 case IOBASE_ISA_IO:
1321 return (long)isa_io_base;
1322 case IOBASE_ISA_MEM:
1323 return (long)isa_mem_base;
1324 }
1325
1326 return result;
1327}
1328
1329
1330
1331
1332
1333#define NULL_PCI_OP(rw, size, type) \
1334static int \
1335null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1336{ \
1337 return PCIBIOS_DEVICE_NOT_FOUND; \
1338}
1339
1340static int
1341null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1342 int len, u32 *val)
1343{
1344 return PCIBIOS_DEVICE_NOT_FOUND;
1345}
1346
1347static int
1348null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1349 int len, u32 val)
1350{
1351 return PCIBIOS_DEVICE_NOT_FOUND;
1352}
1353
1354static struct pci_ops null_pci_ops = {
1355 .read = null_read_config,
1356 .write = null_write_config,
1357};
1358
1359
1360
1361
1362
1363static struct pci_bus *
1364fake_pci_bus(struct pci_controller *hose, int busnr)
1365{
1366 static struct pci_bus bus;
1367
1368 if (!hose)
1369 pr_err("Can't find hose for PCI bus %d!\n", busnr);
1370
1371 bus.number = busnr;
1372 bus.sysdata = hose;
1373 bus.ops = hose ? hose->ops : &null_pci_ops;
1374 return &bus;
1375}
1376
1377#define EARLY_PCI_OP(rw, size, type) \
1378int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1379 int devfn, int offset, type value) \
1380{ \
1381 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1382 devfn, offset, value); \
1383}
1384
1385EARLY_PCI_OP(read, byte, u8 *)
1386EARLY_PCI_OP(read, word, u16 *)
1387EARLY_PCI_OP(read, dword, u32 *)
1388EARLY_PCI_OP(write, byte, u8)
1389EARLY_PCI_OP(write, word, u16)
1390EARLY_PCI_OP(write, dword, u32)
1391
1392int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1393 int cap)
1394{
1395 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1396}
1397
1398