1/* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * Parts of this file are based on Ralink's 2.6.21 BSP 7 * 8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 10 * Copyright (C) 2013 John Crispin <john@phrozen.org> 11 */ 12 13#ifndef _MT7620_REGS_H_ 14#define _MT7620_REGS_H_ 15 16#define MT7620_SYSC_BASE 0x10000000 17 18#define SYSC_REG_CHIP_NAME0 0x00 19#define SYSC_REG_CHIP_NAME1 0x04 20#define SYSC_REG_EFUSE_CFG 0x08 21#define SYSC_REG_CHIP_REV 0x0c 22#define SYSC_REG_SYSTEM_CONFIG0 0x10 23#define SYSC_REG_SYSTEM_CONFIG1 0x14 24#define SYSC_REG_CLKCFG0 0x2c 25#define SYSC_REG_CPU_SYS_CLKCFG 0x3c 26#define SYSC_REG_CPLL_CONFIG0 0x54 27#define SYSC_REG_CPLL_CONFIG1 0x58 28 29#define MT7620_CHIP_NAME0 0x3637544d 30#define MT7620_CHIP_NAME1 0x20203032 31#define MT7628_CHIP_NAME1 0x20203832 32 33#define SYSCFG0_XTAL_FREQ_SEL BIT(6) 34 35#define CHIP_REV_PKG_MASK 0x1 36#define CHIP_REV_PKG_SHIFT 16 37#define CHIP_REV_VER_MASK 0xf 38#define CHIP_REV_VER_SHIFT 8 39#define CHIP_REV_ECO_MASK 0xf 40 41#define CLKCFG0_PERI_CLK_SEL BIT(4) 42 43#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16 44#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf 45#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */ 46#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */ 47#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */ 48#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */ 49#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */ 50#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */ 51#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */ 52#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */ 53#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */ 54#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8 55#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f 56#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0 57#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f 58 59#define CPLL_CFG0_SW_CFG BIT(31) 60#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16 61#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7 62#define CPLL_CFG0_LC_CURFCK BIT(15) 63#define CPLL_CFG0_BYPASS_REF_CLK BIT(14) 64#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10 65#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3 66 67#define CPLL_CFG1_CPU_AUX1 BIT(25) 68#define CPLL_CFG1_CPU_AUX0 BIT(24) 69 70#define SYSCFG0_DRAM_TYPE_MASK 0x3 71#define SYSCFG0_DRAM_TYPE_SHIFT 4 72#define SYSCFG0_DRAM_TYPE_SDRAM 0 73#define SYSCFG0_DRAM_TYPE_DDR1 1 74#define SYSCFG0_DRAM_TYPE_DDR2 2 75#define SYSCFG0_DRAM_TYPE_UNKNOWN 3 76 77#define SYSCFG0_DRAM_TYPE_DDR2_MT7628 0 78#define SYSCFG0_DRAM_TYPE_DDR1_MT7628 1 79 80#define MT7620_DRAM_BASE 0x0 81#define MT7620_SDRAM_SIZE_MIN 2 82#define MT7620_SDRAM_SIZE_MAX 64 83#define MT7620_DDR1_SIZE_MIN 32 84#define MT7620_DDR1_SIZE_MAX 128 85#define MT7620_DDR2_SIZE_MIN 32 86#define MT7620_DDR2_SIZE_MAX 256 87 88#define MT7620_GPIO_MODE_UART0_SHIFT 2 89#define MT7620_GPIO_MODE_UART0_MASK 0x7 90#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT) 91#define MT7620_GPIO_MODE_UARTF 0x0 92#define MT7620_GPIO_MODE_PCM_UARTF 0x1 93#define MT7620_GPIO_MODE_PCM_I2S 0x2 94#define MT7620_GPIO_MODE_I2S_UARTF 0x3 95#define MT7620_GPIO_MODE_PCM_GPIO 0x4 96#define MT7620_GPIO_MODE_GPIO_UARTF 0x5 97#define MT7620_GPIO_MODE_GPIO_I2S 0x6 98#define MT7620_GPIO_MODE_GPIO 0x7 99 100#define MT7620_GPIO_MODE_NAND 0 101#define MT7620_GPIO_MODE_SD 1 102#define MT7620_GPIO_MODE_ND_SD_GPIO 2 103#define MT7620_GPIO_MODE_ND_SD_MASK 0x3 104#define MT7620_GPIO_MODE_ND_SD_SHIFT 18 105 106#define MT7620_GPIO_MODE_PCIE_RST 0 107#define MT7620_GPIO_MODE_PCIE_REF 1 108#define MT7620_GPIO_MODE_PCIE_GPIO 2 109#define MT7620_GPIO_MODE_PCIE_MASK 0x3 110#define MT7620_GPIO_MODE_PCIE_SHIFT 16 111 112#define MT7620_GPIO_MODE_WDT_RST 0 113#define MT7620_GPIO_MODE_WDT_REF 1 114#define MT7620_GPIO_MODE_WDT_GPIO 2 115#define MT7620_GPIO_MODE_WDT_MASK 0x3 116#define MT7620_GPIO_MODE_WDT_SHIFT 21 117 118#define MT7620_GPIO_MODE_I2C 0 119#define MT7620_GPIO_MODE_UART1 5 120#define MT7620_GPIO_MODE_MDIO 8 121#define MT7620_GPIO_MODE_RGMII1 9 122#define MT7620_GPIO_MODE_RGMII2 10 123#define MT7620_GPIO_MODE_SPI 11 124#define MT7620_GPIO_MODE_SPI_REF_CLK 12 125#define MT7620_GPIO_MODE_WLED 13 126#define MT7620_GPIO_MODE_JTAG 15 127#define MT7620_GPIO_MODE_EPHY 15 128#define MT7620_GPIO_MODE_PA 20 129 130static inline int mt7620_get_eco(void) 131{ 132 return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK; 133} 134 135#endif 136