LXR linux/arch/x86/include/asm/intel-mid.h

   1/*
   2 * intel-mid.h: Intel MID specific setup code
   3 *
   4 * (C) Copyright 2009 Intel Corporation
   5 *
   6 * This program is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU General Public License
   8 * as published by the Free Software Foundation; version 2
   9 * of the License.
  10 */
  11#ifndef _ASM_X86_INTEL_MID_H
  12#define _ASM_X86_INTEL_MID_H
  13
  14#include <linux/sfi.h>
  15#include <linux/pci.h>
  16#include <linux/platform_device.h>
  17
  18extern int intel_mid_pci_init(void);
  19extern int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
  20extern pci_power_t intel_mid_pci_get_power_state(struct pci_dev *pdev);
  21
  22extern void intel_mid_pwr_power_off(void);
  23
  24#define INTEL_MID_PWR_LSS_OFFSET        4
  25#define INTEL_MID_PWR_LSS_TYPE          (1 << 7)
  26
  27extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev);
  28
  29extern int get_gpio_by_name(const char *name);
  30extern void intel_scu_device_register(struct platform_device *pdev);
  31extern int __init sfi_parse_mrtc(struct sfi_table_header *table);
  32extern int __init sfi_parse_mtmr(struct sfi_table_header *table);
  33extern int sfi_mrtc_num;
  34extern struct sfi_rtc_table_entry sfi_mrtc_array[];
  35
  36/*
  37 * Here defines the array of devices platform data that IAFW would export
  38 * through SFI "DEVS" table, we use name and type to match the device and
  39 * its platform data.
  40 */
  41struct devs_id {
  42        char name[SFI_NAME_LEN + 1];
  43        u8 type;
  44        u8 delay;
  45        void *(*get_platform_data)(void *info);
  46        /* Custom handler for devices */
  47        void (*device_handler)(struct sfi_device_table_entry *pentry,
  48                               struct devs_id *dev);
  49};
  50
  51#define sfi_device(i)                                                           \
  52        static const struct devs_id *const __intel_mid_sfi_##i##_dev __used     \
  53        __attribute__((__section__(".x86_intel_mid_dev.init"))) = &i
  54
  55/**
  56* struct mid_sd_board_info - template for SD device creation
  57* @name:                identifies the driver
  58* @bus_num:             board-specific identifier for a given SD controller
  59* @max_clk:             the maximum frequency device supports
  60* @platform_data:       the particular data stored there is driver-specific
  61*/
  62struct mid_sd_board_info {
  63        char            name[SFI_NAME_LEN];
  64        int             bus_num;
  65        unsigned short  addr;
  66        u32             max_clk;
  67        void            *platform_data;
  68};
  69
  70/*
  71 * Medfield is the follow-up of Moorestown, it combines two chip solution into
  72 * one. Other than that it also added always-on and constant tsc and lapic
  73 * timers. Medfield is the platform name, and the chip name is called Penwell
  74 * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
  75 * identified via MSRs.
  76 */
  77enum intel_mid_cpu_type {
  78        /* 1 was Moorestown */
  79        INTEL_MID_CPU_CHIP_PENWELL = 2,
  80        INTEL_MID_CPU_CHIP_CLOVERVIEW,
  81        INTEL_MID_CPU_CHIP_TANGIER,
  82};
  83
  84extern enum intel_mid_cpu_type __intel_mid_cpu_chip;
  85
  86/**
  87 * struct intel_mid_ops - Interface between intel-mid & sub archs
  88 * @arch_setup: arch_setup function to re-initialize platform
  89 *              structures (x86_init, x86_platform_init)
  90 *
  91 * This structure can be extended if any new interface is required
  92 * between intel-mid & its sub arch files.
  93 */
  94struct intel_mid_ops {
  95        void (*arch_setup)(void);
  96};
  97
  98/* Helper API's for INTEL_MID_OPS_INIT */
  99#define DECLARE_INTEL_MID_OPS_INIT(cpuname, cpuid)                              \
 100        [cpuid] = get_##cpuname##_ops
 101
 102/* Maximum number of CPU ops */
 103#define MAX_CPU_OPS(a)                  (sizeof(a)/sizeof(void *))
 104
 105/*
 106 * For every new cpu addition, a weak get_<cpuname>_ops() function needs be
 107 * declared in arch/x86/platform/intel_mid/intel_mid_weak_decls.h.
 108 */
 109#define INTEL_MID_OPS_INIT {                                                    \
 110        DECLARE_INTEL_MID_OPS_INIT(penwell, INTEL_MID_CPU_CHIP_PENWELL),        \
 111        DECLARE_INTEL_MID_OPS_INIT(cloverview, INTEL_MID_CPU_CHIP_CLOVERVIEW),  \
 112        DECLARE_INTEL_MID_OPS_INIT(tangier, INTEL_MID_CPU_CHIP_TANGIER)         \
 113};
 114
 115#ifdef CONFIG_X86_INTEL_MID
 116
 117static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void)
 118{
 119        return __intel_mid_cpu_chip;
 120}
 121
 122static inline bool intel_mid_has_msic(void)
 123{
 124        return (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL);
 125}
 126
 127#else /* !CONFIG_X86_INTEL_MID */
 128
 129#define intel_mid_identify_cpu()        0
 130#define intel_mid_has_msic()            0
 131
 132#endif /* !CONFIG_X86_INTEL_MID */
 133
 134enum intel_mid_timer_options {
 135        INTEL_MID_TIMER_DEFAULT,
 136        INTEL_MID_TIMER_APBT_ONLY,
 137        INTEL_MID_TIMER_LAPIC_APBT,
 138};
 139
 140extern enum intel_mid_timer_options intel_mid_timer_options;
 141
 142/*
 143 * Penwell uses spread spectrum clock, so the freq number is not exactly
 144 * the same as reported by MSR based on SDM.
 145 */
 146#define FSB_FREQ_83SKU                  83200
 147#define FSB_FREQ_100SKU                 99840
 148#define FSB_FREQ_133SKU                 133000
 149
 150#define FSB_FREQ_167SKU                 167000
 151#define FSB_FREQ_200SKU                 200000
 152#define FSB_FREQ_267SKU                 267000
 153#define FSB_FREQ_333SKU                 333000
 154#define FSB_FREQ_400SKU                 400000
 155
 156/* Bus Select SoC Fuse value */
 157#define BSEL_SOC_FUSE_MASK              0x7
 158/* FSB 133MHz */
 159#define BSEL_SOC_FUSE_001               0x1
 160/* FSB 100MHz */
 161#define BSEL_SOC_FUSE_101               0x5
 162/* FSB 83MHz */
 163#define BSEL_SOC_FUSE_111               0x7
 164
 165#define SFI_MTMR_MAX_NUM                8
 166#define SFI_MRTC_MAX                    8
 167
 168extern void intel_scu_devices_create(void);
 169extern void intel_scu_devices_destroy(void);
 170
 171/* VRTC timer */
 172#define MRST_VRTC_MAP_SZ                1024
 173/* #define MRST_VRTC_PGOFFSET           0xc00 */
 174
 175extern void intel_mid_rtc_init(void);
 176
 177/* The offset for the mapping of global gpio pin to irq */
 178#define INTEL_MID_IRQ_OFFSET            0x100
 179
 180#endif /* _ASM_X86_INTEL_MID_H */
 181