LXR linux/drivers/ata/ahci

   1/*
   2 * Copyright (C) 2015 Xilinx, Inc.
   3 * CEVA AHCI SATA platform driver
   4 *
   5 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
   6 *
   7 * This program is free software; you can redistribute it and/or modify it
   8 * under the terms and conditions of the GNU General Public License,
   9 * version 2, as published by the Free Software Foundation.
  10 *
  11 * This program is distributed in the hope it will be useful, but WITHOUT
  12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14 * more details.
  15 *
  16 * You should have received a copy of the GNU General Public License along with
  17 * this program. If not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#include <linux/ahci_platform.h>
  21#include <linux/kernel.h>
  22#include <linux/libata.h>
  23#include <linux/module.h>
  24#include <linux/of_device.h>
  25#include <linux/platform_device.h>
  26#include "ahci.h"
  27
  28/* Vendor Specific Register Offsets */
  29#define AHCI_VEND_PCFG  0xA4
  30#define AHCI_VEND_PPCFG 0xA8
  31#define AHCI_VEND_PP2C  0xAC
  32#define AHCI_VEND_PP3C  0xB0
  33#define AHCI_VEND_PP4C  0xB4
  34#define AHCI_VEND_PP5C  0xB8
  35#define AHCI_VEND_AXICC 0xBC
  36#define AHCI_VEND_PAXIC 0xC0
  37#define AHCI_VEND_PTC   0xC8
  38
  39/* Vendor Specific Register bit definitions */
  40#define PAXIC_ADBW_BW64 0x1
  41#define PAXIC_MAWIDD    (1 << 8)
  42#define PAXIC_MARIDD    (1 << 16)
  43#define PAXIC_OTL       (0x4 << 20)
  44
  45/* Register bit definitions for cache control */
  46#define AXICC_ARCA_VAL  (0xF << 0)
  47#define AXICC_ARCF_VAL  (0xF << 4)
  48#define AXICC_ARCH_VAL  (0xF << 8)
  49#define AXICC_ARCP_VAL  (0xF << 12)
  50#define AXICC_AWCFD_VAL (0xF << 16)
  51#define AXICC_AWCD_VAL  (0xF << 20)
  52#define AXICC_AWCF_VAL  (0xF << 24)
  53
  54#define PCFG_TPSS_VAL   (0x32 << 16)
  55#define PCFG_TPRS_VAL   (0x2 << 12)
  56#define PCFG_PAD_VAL    0x2
  57
  58#define PPCFG_TTA       0x1FFFE
  59#define PPCFG_PSSO_EN   (1 << 28)
  60#define PPCFG_PSS_EN    (1 << 29)
  61#define PPCFG_ESDF_EN   (1 << 31)
  62
  63#define PP5C_RIT        0x60216
  64#define PP5C_RCT        (0x7f0 << 20)
  65
  66#define PTC_RX_WM_VAL   0x40
  67#define PTC_RSVD        (1 << 27)
  68
  69#define PORT0_BASE      0x100
  70#define PORT1_BASE      0x180
  71
  72/* Port Control Register Bit Definitions */
  73#define PORT_SCTL_SPD_GEN3      (0x3 << 4)
  74#define PORT_SCTL_SPD_GEN2      (0x2 << 4)
  75#define PORT_SCTL_SPD_GEN1      (0x1 << 4)
  76#define PORT_SCTL_IPM           (0x3 << 8)
  77
  78#define PORT_BASE       0x100
  79#define PORT_OFFSET     0x80
  80#define NR_PORTS        2
  81#define DRV_NAME        "ahci-ceva"
  82#define CEVA_FLAG_BROKEN_GEN2   1
  83
  84static unsigned int rx_watermark = PTC_RX_WM_VAL;
  85module_param(rx_watermark, uint, 0);
  86MODULE_PARM_DESC(rx_watermark, "RxWaterMark value (0 - 0x80)");
  87
  88struct ceva_ahci_priv {
  89        struct platform_device *ahci_pdev;
  90        /* Port Phy2Cfg Register */
  91        u32 pp2c[NR_PORTS];
  92        u32 pp3c[NR_PORTS];
  93        u32 pp4c[NR_PORTS];
  94        u32 pp5c[NR_PORTS];
  95        /* Axi Cache Control Register */
  96        u32 axicc;
  97        bool is_cci_enabled;
  98        int flags;
  99};
 100
 101static unsigned int ceva_ahci_read_id(struct ata_device *dev,
 102                                        struct ata_taskfile *tf, u16 *id)
 103{
 104        u32 err_mask;
 105
 106        err_mask = ata_do_dev_read_id(dev, tf, id);
 107        if (err_mask)
 108                return err_mask;
 109        /*
 110         * Since CEVA controller does not support device sleep feature, we
 111         * need to clear DEVSLP (bit 8) in word78 of the IDENTIFY DEVICE data.
 112         */
 113        id[ATA_ID_FEATURE_SUPP] &= cpu_to_le16(~(1 << 8));
 114
 115        return 0;
 116}
 117
 118static struct ata_port_operations ahci_ceva_ops = {
 119        .inherits = &ahci_platform_ops,
 120        .read_id = ceva_ahci_read_id,
 121};
 122
 123static const struct ata_port_info ahci_ceva_port_info = {
 124        .flags          = AHCI_FLAG_COMMON,
 125        .pio_mask       = ATA_PIO4,
 126        .udma_mask      = ATA_UDMA6,
 127        .port_ops       = &ahci_ceva_ops,
 128};
 129
 130static void ahci_ceva_setup(struct ahci_host_priv *hpriv)
 131{
 132        void __iomem *mmio = hpriv->mmio;
 133        struct ceva_ahci_priv *cevapriv = hpriv->plat_data;
 134        u32 tmp;
 135        int i;
 136
 137        /* Set AHCI Enable */
 138        tmp = readl(mmio + HOST_CTL);
 139        tmp |= HOST_AHCI_EN;
 140        writel(tmp, mmio + HOST_CTL);
 141
 142        for (i = 0; i < NR_PORTS; i++) {
 143                /* TPSS TPRS scalars, CISE and Port Addr */
 144                tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
 145                writel(tmp, mmio + AHCI_VEND_PCFG);
 146
 147                /*
 148                 * AXI Data bus width to 64
 149                 * Set Mem Addr Read, Write ID for data transfers
 150                 * Transfer limit to 72 DWord
 151                 */
 152                tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
 153                writel(tmp, mmio + AHCI_VEND_PAXIC);
 154
 155                /* Set AXI cache control register if CCi is enabled */
 156                if (cevapriv->is_cci_enabled) {
 157                        tmp = readl(mmio + AHCI_VEND_AXICC);
 158                        tmp |= AXICC_ARCA_VAL | AXICC_ARCF_VAL |
 159                                AXICC_ARCH_VAL | AXICC_ARCP_VAL |
 160                                AXICC_AWCFD_VAL | AXICC_AWCD_VAL |
 161                                AXICC_AWCF_VAL;
 162                        writel(tmp, mmio + AHCI_VEND_AXICC);
 163                }
 164
 165                /* Port Phy Cfg register enables */
 166                tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
 167                writel(tmp, mmio + AHCI_VEND_PPCFG);
 168
 169                /* Phy Control OOB timing parameters COMINIT */
 170                writel(cevapriv->pp2c[i], mmio + AHCI_VEND_PP2C);
 171
 172                /* Phy Control OOB timing parameters COMWAKE */
 173                writel(cevapriv->pp3c[i], mmio + AHCI_VEND_PP3C);
 174
 175                /* Phy Control Burst timing setting */
 176                writel(cevapriv->pp4c[i], mmio + AHCI_VEND_PP4C);
 177
 178                /* Rate Change Timer and Retry Interval Timer setting */
 179                writel(cevapriv->pp5c[i], mmio + AHCI_VEND_PP5C);
 180
 181                /* Rx Watermark setting  */
 182                tmp = rx_watermark | PTC_RSVD;
 183                writel(tmp, mmio + AHCI_VEND_PTC);
 184
 185                /* Default to Gen 3 Speed and Gen 1 if Gen2 is broken */
 186                tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM;
 187                if (cevapriv->flags & CEVA_FLAG_BROKEN_GEN2)
 188                        tmp = PORT_SCTL_SPD_GEN1 | PORT_SCTL_IPM;
 189                writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
 190        }
 191}
 192
 193static struct scsi_host_template ahci_platform_sht = {
 194        AHCI_SHT(DRV_NAME),
 195};
 196
 197static int ceva_ahci_probe(struct platform_device *pdev)
 198{
 199        struct device_node *np = pdev->dev.of_node;
 200        struct device *dev = &pdev->dev;
 201        struct ahci_host_priv *hpriv;
 202        struct ceva_ahci_priv *cevapriv;
 203        enum dev_dma_attr attr;
 204        int rc;
 205
 206        cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL);
 207        if (!cevapriv)
 208                return -ENOMEM;
 209
 210        cevapriv->ahci_pdev = pdev;
 211
 212        hpriv = ahci_platform_get_resources(pdev);
 213        if (IS_ERR(hpriv))
 214                return PTR_ERR(hpriv);
 215
 216        rc = ahci_platform_enable_resources(hpriv);
 217        if (rc)
 218                return rc;
 219
 220        if (of_property_read_bool(np, "ceva,broken-gen2"))
 221                cevapriv->flags = CEVA_FLAG_BROKEN_GEN2;
 222
 223        /* Read OOB timing value for COMINIT from device-tree */
 224        if (of_property_read_u8_array(np, "ceva,p0-cominit-params",
 225                                        (u8 *)&cevapriv->pp2c[0], 4) < 0) {
 226                dev_warn(dev, "ceva,p0-cominit-params property not defined\n");
 227                return -EINVAL;
 228        }
 229
 230        if (of_property_read_u8_array(np, "ceva,p1-cominit-params",
 231                                        (u8 *)&cevapriv->pp2c[1], 4) < 0) {
 232                dev_warn(dev, "ceva,p1-cominit-params property not defined\n");
 233                return -EINVAL;
 234        }
 235
 236        /* Read OOB timing value for COMWAKE from device-tree*/
 237        if (of_property_read_u8_array(np, "ceva,p0-comwake-params",
 238                                        (u8 *)&cevapriv->pp3c[0], 4) < 0) {
 239                dev_warn(dev, "ceva,p0-comwake-params property not defined\n");
 240                return -EINVAL;
 241        }
 242
 243        if (of_property_read_u8_array(np, "ceva,p1-comwake-params",
 244                                        (u8 *)&cevapriv->pp3c[1], 4) < 0) {
 245                dev_warn(dev, "ceva,p1-comwake-params property not defined\n");
 246                return -EINVAL;
 247        }
 248
 249        /* Read phy BURST timing value from device-tree */
 250        if (of_property_read_u8_array(np, "ceva,p0-burst-params",
 251                                        (u8 *)&cevapriv->pp4c[0], 4) < 0) {
 252                dev_warn(dev, "ceva,p0-burst-params property not defined\n");
 253                return -EINVAL;
 254        }
 255
 256        if (of_property_read_u8_array(np, "ceva,p1-burst-params",
 257                                        (u8 *)&cevapriv->pp4c[1], 4) < 0) {
 258                dev_warn(dev, "ceva,p1-burst-params property not defined\n");
 259                return -EINVAL;
 260        }
 261
 262        /* Read phy RETRY interval timing value from device-tree */
 263        if (of_property_read_u16_array(np, "ceva,p0-retry-params",
 264                                        (u16 *)&cevapriv->pp5c[0], 2) < 0) {
 265                dev_warn(dev, "ceva,p0-retry-params property not defined\n");
 266                return -EINVAL;
 267        }
 268
 269        if (of_property_read_u16_array(np, "ceva,p1-retry-params",
 270                                        (u16 *)&cevapriv->pp5c[1], 2) < 0) {
 271                dev_warn(dev, "ceva,p1-retry-params property not defined\n");
 272                return -EINVAL;
 273        }
 274
 275        /*
 276         * Check if CCI is enabled for SATA. The DEV_DMA_COHERENT is returned
 277         * if CCI is enabled, so check for DEV_DMA_COHERENT.
 278         */
 279        attr = device_get_dma_attr(dev);
 280        cevapriv->is_cci_enabled = (attr == DEV_DMA_COHERENT);
 281
 282        hpriv->plat_data = cevapriv;
 283
 284        /* CEVA specific initialization */
 285        ahci_ceva_setup(hpriv);
 286
 287        rc = ahci_platform_init_host(pdev, hpriv, &ahci_ceva_port_info,
 288                                        &ahci_platform_sht);
 289        if (rc)
 290                goto disable_resources;
 291
 292        return 0;
 293
 294disable_resources:
 295        ahci_platform_disable_resources(hpriv);
 296        return rc;
 297}
 298
 299static int __maybe_unused ceva_ahci_suspend(struct device *dev)
 300{
 301        return ahci_platform_suspend_host(dev);
 302}
 303
 304static int __maybe_unused ceva_ahci_resume(struct device *dev)
 305{
 306        return ahci_platform_resume_host(dev);
 307}
 308
 309static SIMPLE_DEV_PM_OPS(ahci_ceva_pm_ops, ceva_ahci_suspend, ceva_ahci_resume);
 310
 311static const struct of_device_id ceva_ahci_of_match[] = {
 312        { .compatible = "ceva,ahci-1v84" },
 313        {},
 314};
 315MODULE_DEVICE_TABLE(of, ceva_ahci_of_match);
 316
 317static struct platform_driver ceva_ahci_driver = {
 318        .probe = ceva_ahci_probe,
 319        .remove = ata_platform_remove_one,
 320        .driver = {
 321                .name = DRV_NAME,
 322                .of_match_table = ceva_ahci_of_match,
 323                .pm = &ahci_ceva_pm_ops,
 324        },
 325};
 326module_platform_driver(ceva_ahci_driver);
 327
 328MODULE_DESCRIPTION("CEVA AHCI SATA platform driver");
 329MODULE_AUTHOR("Xilinx Inc.");
 330MODULE_LICENSE("GPL v2");
 331