1/* drivers/atm/midway.h - Efficient Networks Midway (SAR) description */ 2 3/* Written 1995-1999 by Werner Almesberger, EPFL LRC/ICA */ 4 5 6#ifndef DRIVERS_ATM_MIDWAY_H 7#define DRIVERS_ATM_MIDWAY_H 8 9 10#define NR_VCI 1024 /* number of VCIs */ 11#define NR_VCI_LD 10 /* log2(NR_VCI) */ 12#define NR_DMA_RX 512 /* RX DMA queue entries */ 13#define NR_DMA_TX 512 /* TX DMA queue entries */ 14#define NR_SERVICE NR_VCI /* service list size */ 15#define NR_CHAN 8 /* number of TX channels */ 16#define TS_CLOCK 25000000 /* traffic shaper clock (cell/sec) */ 17 18#define MAP_MAX_SIZE 0x00400000 /* memory window for max config */ 19#define EPROM_SIZE 0x00010000 20#define MEM_VALID 0xffc00000 /* mask base address with this */ 21#define PHY_BASE 0x00020000 /* offset of PHY register are */ 22#define REG_BASE 0x00040000 /* offset of Midway register area */ 23#define RAM_BASE 0x00200000 /* offset of RAM area */ 24#define RAM_INCREMENT 0x00020000 /* probe for RAM every 128kB */ 25 26#define MID_VCI_BASE RAM_BASE 27#define MID_DMA_RX_BASE (MID_VCI_BASE+NR_VCI*16) 28#define MID_DMA_TX_BASE (MID_DMA_RX_BASE+NR_DMA_RX*8) 29#define MID_SERVICE_BASE (MID_DMA_TX_BASE+NR_DMA_TX*8) 30#define MID_FREE_BASE (MID_SERVICE_BASE+NR_SERVICE*4) 31 32#define MAC_LEN 6 /* atm.h */ 33 34#define MID_MIN_BUF_SIZE (1024) /* 1 kB is minimum */ 35#define MID_MAX_BUF_SIZE (128*1024) /* 128 kB is maximum */ 36 37#define RX_DESCR_SIZE 1 /* RX PDU descr is 1 longword */ 38#define TX_DESCR_SIZE 2 /* TX PDU descr is 2 longwords */ 39#define AAL5_TRAILER (ATM_AAL5_TRAILER/4) /* AAL5 trailer is 2 longwords */ 40 41#define TX_GAP 8 /* TX buffer gap (words) */ 42 43/* 44 * Midway Reset/ID 45 * 46 * All values read-only. Writing to this register resets Midway chip. 47 */ 48 49#define MID_RES_ID_MCON 0x00 /* Midway Reset/ID */ 50 51#define MID_ID 0xf0000000 /* Midway version */ 52#define MID_SHIFT 24 53#define MID_MOTHER_ID 0x00000700 /* mother board id */ 54#define MID_MOTHER_SHIFT 8 55#define MID_CON_TI 0x00000080 /* 0: normal ctrl; 1: SABRE */ 56#define MID_CON_SUNI 0x00000040 /* 0: UTOPIA; 1: SUNI */ 57#define MID_CON_V6 0x00000020 /* 0: non-pipel UTOPIA (required iff 58 !CON_SUNI; 1: UTOPIA */ 59#define DAUGTHER_ID 0x0000001f /* daugther board id */ 60 61/* 62 * Interrupt Status Acknowledge, Interrupt Status & Interrupt Enable 63 */ 64 65#define MID_ISA 0x01 /* Interrupt Status Acknowledge */ 66#define MID_IS 0x02 /* Interrupt Status */ 67#define MID_IE 0x03 /* Interrupt Enable */ 68 69#define MID_TX_COMPLETE_7 0x00010000 /* channel N completed a PDU */ 70#define MID_TX_COMPLETE_6 0x00008000 /* transmission */ 71#define MID_TX_COMPLETE_5 0x00004000 72#define MID_TX_COMPLETE_4 0x00002000 73#define MID_TX_COMPLETE_3 0x00001000 74#define MID_TX_COMPLETE_2 0x00000800 75#define MID_TX_COMPLETE_1 0x00000400 76#define MID_TX_COMPLETE_0 0x00000200 77#define MID_TX_COMPLETE 0x0001fe00 /* any TX */ 78#define MID_TX_DMA_OVFL 0x00000100 /* DMA to adapter overflow */ 79#define MID_TX_IDENT_MISM 0x00000080 /* TX: ident mismatch => halted */ 80#define MID_DMA_LERR_ACK 0x00000040 /* LERR - SBus ? */ 81#define MID_DMA_ERR_ACK 0x00000020 /* DMA error */ 82#define MID_RX_DMA_COMPLETE 0x00000010 /* DMA to host done */ 83#define MID_TX_DMA_COMPLETE 0x00000008 /* DMA from host done */ 84#define MID_SERVICE 0x00000004 /* something in service list */ 85#define MID_SUNI_INT 0x00000002 /* interrupt from SUNI */ 86#define MID_STAT_OVFL 0x00000001 /* statistics overflow */ 87 88/* 89 * Master Control/Status 90 */ 91 92#define MID_MC_S 0x04 93 94#define MID_INT_SELECT 0x000001C0 /* Interrupt level (000: off) */ 95#define MID_INT_SEL_SHIFT 6 96#define MID_TX_LOCK_MODE 0x00000020 /* 0: streaming; 1: TX ovfl->lock */ 97#define MID_DMA_ENABLE 0x00000010 /* R: 0: disable; 1: enable 98 W: 0: no change; 1: enable */ 99#define MID_TX_ENABLE 0x00000008 /* R: 0: TX disabled; 1: enabled 100 W: 0: no change; 1: enable */ 101#define MID_RX_ENABLE 0x00000004 /* like TX */ 102#define MID_WAIT_1MS 0x00000002 /* R: 0: timer not running; 1: running 103 W: 0: no change; 1: no interrupts 104 for 1 ms */ 105#define MID_WAIT_500US 0x00000001 /* like WAIT_1MS, but 0.5 ms */ 106 107/* 108 * Statistics 109 * 110 * Cleared when reading. 111 */ 112 113#define MID_STAT 0x05 114 115#define MID_VCI_TRASH 0xFFFF0000 /* trashed cells because of VCI mode */ 116#define MID_VCI_TRASH_SHIFT 16 117#define MID_OVFL_TRASH 0x0000FFFF /* trashed cells because of overflow */ 118 119/* 120 * Address registers 121 */ 122 123#define MID_SERV_WRITE 0x06 /* free pos in service area (R, 10 bits) */ 124#define MID_DMA_ADDR 0x07 /* virtual DMA address (R, 32 bits) */ 125#define MID_DMA_WR_RX 0x08 /* (RW, 9 bits) */ 126#define MID_DMA_RD_RX 0x09 127#define MID_DMA_WR_TX 0x0A 128#define MID_DMA_RD_TX 0x0B 129 130/* 131 * Transmit Place Registers (0x10+4*channel) 132 */ 133 134#define MID_TX_PLACE(c) (0x10+4*(c)) 135 136#define MID_SIZE 0x00003800 /* size, N*256 x 32 bit */ 137#define MID_SIZE_SHIFT 11 138#define MID_LOCATION 0x000007FF /* location in adapter memory (word) */ 139 140#define MID_LOC_SKIP 8 /* 8 bits of location are always zero 141 (applies to all uses of location) */ 142 143/* 144 * Transmit ReadPtr Registers (0x11+4*channel) 145 */ 146 147#define MID_TX_RDPTR(c) (0x11+4*(c)) 148 149#define MID_READ_PTR 0x00007FFF /* next word for PHY */ 150 151/* 152 * Transmit DescrStart Registers (0x12+4*channel) 153 */ 154 155#define MID_TX_DESCRSTART(c) (0x12+4*(c)) 156 157#define MID_DESCR_START 0x00007FFF /* seg buffer being DMAed */ 158 159#define ENI155_MAGIC 0xa54b872d 160 161struct midway_eprom { 162 unsigned char mac[MAC_LEN],inv_mac[MAC_LEN]; 163 unsigned char pad[36]; 164 u32 serial,inv_serial; 165 u32 magic,inv_magic; 166}; 167 168 169/* 170 * VCI table entry 171 */ 172 173#define MID_VCI_IN_SERVICE 0x00000001 /* set if VCI is currently in 174 service list */ 175#define MID_VCI_SIZE 0x00038000 /* reassembly buffer size, 176 2*<size> kB */ 177#define MID_VCI_SIZE_SHIFT 15 178#define MID_VCI_LOCATION 0x1ffc0000 /* buffer location */ 179#define MID_VCI_LOCATION_SHIFT 18 180#define MID_VCI_PTI_MODE 0x20000000 /* 0: trash, 1: preserve */ 181#define MID_VCI_MODE 0xc0000000 182#define MID_VCI_MODE_SHIFT 30 183#define MID_VCI_READ 0x00007fff 184#define MID_VCI_READ_SHIFT 0 185#define MID_VCI_DESCR 0x7fff0000 186#define MID_VCI_DESCR_SHIFT 16 187#define MID_VCI_COUNT 0x000007ff 188#define MID_VCI_COUNT_SHIFT 0 189#define MID_VCI_STATE 0x0000c000 190#define MID_VCI_STATE_SHIFT 14 191#define MID_VCI_WRITE 0x7fff0000 192#define MID_VCI_WRITE_SHIFT 16 193 194#define MID_MODE_TRASH 0 195#define MID_MODE_RAW 1 196#define MID_MODE_AAL5 2 197 198/* 199 * Reassembly buffer descriptor 200 */ 201 202#define MID_RED_COUNT 0x000007ff 203#define MID_RED_CRC_ERR 0x00000800 204#define MID_RED_T 0x00001000 205#define MID_RED_CE 0x00010000 206#define MID_RED_CLP 0x01000000 207#define MID_RED_IDEN 0xfe000000 208#define MID_RED_SHIFT 25 209 210#define MID_RED_RX_ID 0x1b /* constant identifier */ 211 212/* 213 * Segmentation buffer descriptor 214 */ 215 216#define MID_SEG_COUNT MID_RED_COUNT 217#define MID_SEG_RATE 0x01f80000 218#define MID_SEG_RATE_SHIFT 19 219#define MID_SEG_PR 0x06000000 220#define MID_SEG_PR_SHIFT 25 221#define MID_SEG_AAL5 0x08000000 222#define MID_SEG_ID 0xf0000000 223#define MID_SEG_ID_SHIFT 28 224#define MID_SEG_MAX_RATE 63 225 226#define MID_SEG_CLP 0x00000001 227#define MID_SEG_PTI 0x0000000e 228#define MID_SEG_PTI_SHIFT 1 229#define MID_SEG_VCI 0x00003ff0 230#define MID_SEG_VCI_SHIFT 4 231 232#define MID_SEG_TX_ID 0xb /* constant identifier */ 233 234/* 235 * DMA entry 236 */ 237 238#define MID_DMA_COUNT 0xffff0000 239#define MID_DMA_COUNT_SHIFT 16 240#define MID_DMA_END 0x00000020 241#define MID_DMA_TYPE 0x0000000f 242 243#define MID_DT_JK 0x3 244#define MID_DT_WORD 0x0 245#define MID_DT_2W 0x7 246#define MID_DT_4W 0x4 247#define MID_DT_8W 0x5 248#define MID_DT_16W 0x6 249#define MID_DT_2WM 0xf 250#define MID_DT_4WM 0xc 251#define MID_DT_8WM 0xd 252#define MID_DT_16WM 0xe 253 254/* only for RX*/ 255#define MID_DMA_VCI 0x0000ffc0 256#define MID_DMA_VCI_SHIFT 6 257 258/* only for TX */ 259#define MID_DMA_CHAN 0x000001c0 260#define MID_DMA_CHAN_SHIFT 6 261 262#define MID_DT_BYTE 0x1 263#define MID_DT_HWORD 0x2 264 265#endif 266