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15#undef DEBUG
16
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/clk.h>
20#include <linux/clk-provider.h>
21#include <linux/io.h>
22#include <linux/clk/ti.h>
23
24#include <asm/div64.h>
25
26#include "clock.h"
27
28
29#define DPLL_MIN_MULTIPLIER 2
30#define DPLL_MIN_DIVIDER 1
31
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33#define DPLL_MULT_UNDERFLOW -1
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41#define DPLL_SCALE_FACTOR 64
42#define DPLL_SCALE_BASE 2
43#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
44 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
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49
50#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000
51#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000
52
53
54#define DPLL_FINT_UNDERFLOW -1
55#define DPLL_FINT_INVALID -2
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70static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)
71{
72 struct dpll_data *dd;
73 long fint, fint_min, fint_max;
74 int ret = 0;
75
76 dd = clk->dpll_data;
77
78
79 fint = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)) / n;
80
81 if (dd->flags & DPLL_J_TYPE) {
82 fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
83 fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
84 } else {
85 fint_min = ti_clk_get_features()->fint_min;
86 fint_max = ti_clk_get_features()->fint_max;
87 }
88
89 if (!fint_min || !fint_max) {
90 WARN(1, "No fint limits available!\n");
91 return DPLL_FINT_INVALID;
92 }
93
94 if (fint < ti_clk_get_features()->fint_min) {
95 pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
96 n);
97 dd->max_divider = n;
98 ret = DPLL_FINT_UNDERFLOW;
99 } else if (fint > ti_clk_get_features()->fint_max) {
100 pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
101 n);
102 dd->min_divider = n;
103 ret = DPLL_FINT_INVALID;
104 } else if (fint > ti_clk_get_features()->fint_band1_max &&
105 fint < ti_clk_get_features()->fint_band2_min) {
106 pr_debug("rejecting n=%d due to Fint failure\n", n);
107 ret = DPLL_FINT_INVALID;
108 }
109
110 return ret;
111}
112
113static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
114 unsigned int m, unsigned int n)
115{
116 unsigned long long num;
117
118 num = (unsigned long long)parent_rate * m;
119 do_div(num, n);
120 return num;
121}
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143static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
144 unsigned long target_rate,
145 unsigned long parent_rate)
146{
147 int r = 0, carry = 0;
148
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150 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
151 carry = 1;
152 *m = (*m / DPLL_SCALE_FACTOR) + carry;
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158 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
159 if (*new_rate > target_rate) {
160 (*m)--;
161 *new_rate = 0;
162 }
163
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165 if (*m < DPLL_MIN_MULTIPLIER) {
166 *m = DPLL_MIN_MULTIPLIER;
167 *new_rate = 0;
168 r = DPLL_MULT_UNDERFLOW;
169 }
170
171 if (*new_rate == 0)
172 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
173
174 return r;
175}
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184static int _omap2_dpll_is_in_bypass(u32 v)
185{
186 u8 mask, val;
187
188 mask = ti_clk_get_features()->dpll_bypass_vals;
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195 while (mask) {
196 val = __ffs(mask);
197 mask ^= (1 << val);
198 if (v == val)
199 return 1;
200 }
201
202 return 0;
203}
204
205
206u8 omap2_init_dpll_parent(struct clk_hw *hw)
207{
208 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
209 u32 v;
210 struct dpll_data *dd;
211
212 dd = clk->dpll_data;
213 if (!dd)
214 return -EINVAL;
215
216 v = ti_clk_ll_ops->clk_readl(dd->control_reg);
217 v &= dd->enable_mask;
218 v >>= __ffs(dd->enable_mask);
219
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221 if (_omap2_dpll_is_in_bypass(v))
222 return 1;
223
224 return 0;
225}
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241unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
242{
243 u64 dpll_clk;
244 u32 dpll_mult, dpll_div, v;
245 struct dpll_data *dd;
246
247 dd = clk->dpll_data;
248 if (!dd)
249 return 0;
250
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252 v = ti_clk_ll_ops->clk_readl(dd->control_reg);
253 v &= dd->enable_mask;
254 v >>= __ffs(dd->enable_mask);
255
256 if (_omap2_dpll_is_in_bypass(v))
257 return clk_hw_get_rate(dd->clk_bypass);
258
259 v = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg);
260 dpll_mult = v & dd->mult_mask;
261 dpll_mult >>= __ffs(dd->mult_mask);
262 dpll_div = v & dd->div1_mask;
263 dpll_div >>= __ffs(dd->div1_mask);
264
265 dpll_clk = (u64)clk_hw_get_rate(dd->clk_ref) * dpll_mult;
266 do_div(dpll_clk, dpll_div + 1);
267
268 return dpll_clk;
269}
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285long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
286 unsigned long *parent_rate)
287{
288 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
289 int m, n, r, scaled_max_m;
290 int min_delta_m = INT_MAX, min_delta_n = INT_MAX;
291 unsigned long scaled_rt_rp;
292 unsigned long new_rate = 0;
293 struct dpll_data *dd;
294 unsigned long ref_rate;
295 long delta;
296 long prev_min_delta = LONG_MAX;
297 const char *clk_name;
298
299 if (!clk || !clk->dpll_data)
300 return ~0;
301
302 dd = clk->dpll_data;
303
304 if (dd->max_rate && target_rate > dd->max_rate)
305 target_rate = dd->max_rate;
306
307 ref_rate = clk_hw_get_rate(dd->clk_ref);
308 clk_name = clk_hw_get_name(hw);
309 pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",
310 clk_name, target_rate);
311
312 scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
313 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
314
315 dd->last_rounded_rate = 0;
316
317 for (n = dd->min_divider; n <= dd->max_divider; n++) {
318
319 r = _dpll_test_fint(clk, n);
320 if (r == DPLL_FINT_UNDERFLOW)
321 break;
322 else if (r == DPLL_FINT_INVALID)
323 continue;
324
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326 m = scaled_rt_rp * n;
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334 if (m > scaled_max_m)
335 break;
336
337 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
338 ref_rate);
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341 if (r == DPLL_MULT_UNDERFLOW)
342 continue;
343
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345 delta = target_rate - new_rate;
346 if (delta < 0)
347 continue;
348
349 if (delta < prev_min_delta) {
350 prev_min_delta = delta;
351 min_delta_m = m;
352 min_delta_n = n;
353 }
354
355 pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n",
356 clk_name, m, n, new_rate);
357
358 if (delta == 0)
359 break;
360 }
361
362 if (prev_min_delta == LONG_MAX) {
363 pr_debug("clock: %s: cannot round to rate %lu\n",
364 clk_name, target_rate);
365 return ~0;
366 }
367
368 dd->last_rounded_m = min_delta_m;
369 dd->last_rounded_n = min_delta_n;
370 dd->last_rounded_rate = target_rate - prev_min_delta;
371
372 return dd->last_rounded_rate;
373}
374