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10#ifndef __ZTE_CLK_H
11#define __ZTE_CLK_H
12#include <linux/clk-provider.h>
13#include <linux/spinlock.h>
14
15#define PNAME(x) static const char *x[]
16
17#define CLK_HW_INIT(_name, _parent, _ops, _flags) \
18 &(struct clk_init_data) { \
19 .flags = _flags, \
20 .name = _name, \
21 .parent_names = (const char *[]) { _parent }, \
22 .num_parents = 1, \
23 .ops = _ops, \
24 }
25
26#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
27 &(struct clk_init_data) { \
28 .flags = _flags, \
29 .name = _name, \
30 .parent_names = _parents, \
31 .num_parents = ARRAY_SIZE(_parents), \
32 .ops = _ops, \
33 }
34
35struct zx_pll_config {
36 unsigned long rate;
37 u32 cfg0;
38 u32 cfg1;
39};
40
41struct clk_zx_pll {
42 struct clk_hw hw;
43 void __iomem *reg_base;
44 const struct zx_pll_config *lookup_table;
45 int count;
46 spinlock_t *lock;
47 u8 pd_bit;
48 u8 lock_bit;
49};
50
51#define PLL_RATE(_rate, _cfg0, _cfg1) \
52{ \
53 .rate = _rate, \
54 .cfg0 = _cfg0, \
55 .cfg1 = _cfg1, \
56}
57
58#define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \
59{ \
60 .reg_base = (void __iomem *) _reg, \
61 .lookup_table = _table, \
62 .count = ARRAY_SIZE(_table), \
63 .pd_bit = _pd, \
64 .lock_bit = _lock, \
65 .hw.init = CLK_HW_INIT(_name, _parent, &zx_pll_ops, \
66 CLK_GET_RATE_NOCACHE), \
67}
68
69#define ZX296718_PLL(_name, _parent, _reg, _table) \
70ZX_PLL(_name, _parent, _reg, _table, 0, 30)
71
72struct zx_clk_gate {
73 struct clk_gate gate;
74 u16 id;
75};
76
77#define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \
78{ \
79 .gate = { \
80 .reg = (void __iomem *) _reg, \
81 .bit_idx = (_bit), \
82 .flags = _gflags, \
83 .lock = &clk_lock, \
84 .hw.init = CLK_HW_INIT(_name, \
85 _parent, \
86 &clk_gate_ops, \
87 _flag | CLK_IGNORE_UNUSED), \
88 }, \
89 .id = _id, \
90}
91
92struct zx_clk_fixed_factor {
93 struct clk_fixed_factor factor;
94 u16 id;
95};
96
97#define FFACTOR(_id, _name, _parent, _mult, _div, _flag) \
98{ \
99 .factor = { \
100 .div = _div, \
101 .mult = _mult, \
102 .hw.init = CLK_HW_INIT(_name, \
103 _parent, \
104 &clk_fixed_factor_ops, \
105 _flag), \
106 }, \
107 .id = _id, \
108}
109
110struct zx_clk_mux {
111 struct clk_mux mux;
112 u16 id;
113};
114
115#define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \
116{ \
117 .mux = { \
118 .reg = (void __iomem *) _reg, \
119 .mask = BIT(_width) - 1, \
120 .shift = _shift, \
121 .flags = _mflag, \
122 .lock = &clk_lock, \
123 .hw.init = CLK_HW_INIT_PARENTS(_name, \
124 _parent, \
125 &clk_mux_ops, \
126 _flag), \
127 }, \
128 .id = _id, \
129}
130
131#define MUX(_id, _name, _parent, _reg, _shift, _width) \
132MUX_F(_id, _name, _parent, _reg, _shift, _width, 0, 0)
133
134struct zx_clk_div {
135 struct clk_divider div;
136 u16 id;
137};
138
139#define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table) \
140{ \
141 .div = { \
142 .reg = (void __iomem *) _reg, \
143 .shift = _shift, \
144 .width = _width, \
145 .flags = 0, \
146 .table = _table, \
147 .lock = &clk_lock, \
148 .hw.init = CLK_HW_INIT(_name, \
149 _parent, \
150 &clk_divider_ops, \
151 _flag), \
152 }, \
153 .id = _id, \
154}
155
156struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
157 unsigned long flags, void __iomem *reg_base,
158 const struct zx_pll_config *lookup_table, int count, spinlock_t *lock);
159
160struct clk_zx_audio {
161 struct clk_hw hw;
162 void __iomem *reg_base;
163};
164
165struct clk *clk_register_zx_audio(const char *name,
166 const char * const parent_name,
167 unsigned long flags, void __iomem *reg_base);
168
169extern const struct clk_ops zx_pll_ops;
170#endif
171
