1
2
3
4
5
6
7
8
9
10
11
12#include <linux/interrupt.h>
13#include <linux/dmaengine.h>
14
15#define DW_DMA_MAX_NR_CHANNELS 8
16#define DW_DMA_MAX_NR_REQUESTS 16
17
18
19enum dw_dma_fc {
20 DW_DMA_FC_D_M2M,
21 DW_DMA_FC_D_M2P,
22 DW_DMA_FC_D_P2M,
23 DW_DMA_FC_D_P2P,
24 DW_DMA_FC_P_P2M,
25 DW_DMA_FC_SP_P2P,
26 DW_DMA_FC_P_M2P,
27 DW_DMA_FC_DP_P2P,
28};
29
30
31
32
33
34#define DW_REG(name) u32 name; u32 __pad_##name
35
36
37struct dw_dma_chan_regs {
38 DW_REG(SAR);
39 DW_REG(DAR);
40 DW_REG(LLP);
41 u32 CTL_LO;
42 u32 CTL_HI;
43 DW_REG(SSTAT);
44 DW_REG(DSTAT);
45 DW_REG(SSTATAR);
46 DW_REG(DSTATAR);
47 u32 CFG_LO;
48 u32 CFG_HI;
49 DW_REG(SGR);
50 DW_REG(DSR);
51};
52
53struct dw_dma_irq_regs {
54 DW_REG(XFER);
55 DW_REG(BLOCK);
56 DW_REG(SRC_TRAN);
57 DW_REG(DST_TRAN);
58 DW_REG(ERROR);
59};
60
61struct dw_dma_regs {
62
63 struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS];
64
65
66 struct dw_dma_irq_regs RAW;
67 struct dw_dma_irq_regs STATUS;
68 struct dw_dma_irq_regs MASK;
69 struct dw_dma_irq_regs CLEAR;
70
71 DW_REG(STATUS_INT);
72
73
74 DW_REG(REQ_SRC);
75 DW_REG(REQ_DST);
76 DW_REG(SGL_REQ_SRC);
77 DW_REG(SGL_REQ_DST);
78 DW_REG(LAST_SRC);
79 DW_REG(LAST_DST);
80
81
82 DW_REG(CFG);
83 DW_REG(CH_EN);
84 DW_REG(ID);
85 DW_REG(TEST);
86
87
88 DW_REG(__reserved0);
89 DW_REG(__reserved1);
90
91
92 u32 __reserved;
93
94
95 u32 DWC_PARAMS[DW_DMA_MAX_NR_CHANNELS];
96 u32 MULTI_BLK_TYPE;
97 u32 MAX_BLK_SIZE;
98
99
100 u32 DW_PARAMS;
101};
102
103
104
105
106
107
108
109#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
110#define dma_readl_native ioread32be
111#define dma_writel_native iowrite32be
112#else
113#define dma_readl_native readl
114#define dma_writel_native writel
115#endif
116
117
118#define DW_PARAMS_NR_CHAN 8
119#define DW_PARAMS_NR_MASTER 11
120#define DW_PARAMS_DATA_WIDTH(n) (15 + 2 * (n))
121#define DW_PARAMS_DATA_WIDTH1 15
122#define DW_PARAMS_DATA_WIDTH2 17
123#define DW_PARAMS_DATA_WIDTH3 19
124#define DW_PARAMS_DATA_WIDTH4 21
125#define DW_PARAMS_EN 28
126
127
128#define DWC_PARAMS_MBLK_EN 11
129
130
131enum dw_dma_msize {
132 DW_DMA_MSIZE_1,
133 DW_DMA_MSIZE_4,
134 DW_DMA_MSIZE_8,
135 DW_DMA_MSIZE_16,
136 DW_DMA_MSIZE_32,
137 DW_DMA_MSIZE_64,
138 DW_DMA_MSIZE_128,
139 DW_DMA_MSIZE_256,
140};
141
142
143#define DWC_LLP_LMS(x) ((x) & 3)
144#define DWC_LLP_LOC(x) ((x) & ~3)
145
146
147#define DWC_CTLL_INT_EN (1 << 0)
148#define DWC_CTLL_DST_WIDTH(n) ((n)<<1)
149#define DWC_CTLL_SRC_WIDTH(n) ((n)<<4)
150#define DWC_CTLL_DST_INC (0<<7)
151#define DWC_CTLL_DST_DEC (1<<7)
152#define DWC_CTLL_DST_FIX (2<<7)
153#define DWC_CTLL_SRC_INC (0<<9)
154#define DWC_CTLL_SRC_DEC (1<<9)
155#define DWC_CTLL_SRC_FIX (2<<9)
156#define DWC_CTLL_DST_MSIZE(n) ((n)<<11)
157#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14)
158#define DWC_CTLL_S_GATH_EN (1 << 17)
159#define DWC_CTLL_D_SCAT_EN (1 << 18)
160#define DWC_CTLL_FC(n) ((n) << 20)
161#define DWC_CTLL_FC_M2M (0 << 20)
162#define DWC_CTLL_FC_M2P (1 << 20)
163#define DWC_CTLL_FC_P2M (2 << 20)
164#define DWC_CTLL_FC_P2P (3 << 20)
165
166#define DWC_CTLL_DMS(n) ((n)<<23)
167#define DWC_CTLL_SMS(n) ((n)<<25)
168#define DWC_CTLL_LLP_D_EN (1 << 27)
169#define DWC_CTLL_LLP_S_EN (1 << 28)
170
171
172#define DWC_CTLH_DONE 0x00001000
173#define DWC_CTLH_BLOCK_TS_MASK 0x00000fff
174
175
176#define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5)
177#define DWC_CFGL_CH_PRIOR(x) ((x) << 5)
178#define DWC_CFGL_CH_SUSP (1 << 8)
179#define DWC_CFGL_FIFO_EMPTY (1 << 9)
180#define DWC_CFGL_HS_DST (1 << 10)
181#define DWC_CFGL_HS_SRC (1 << 11)
182#define DWC_CFGL_LOCK_CH_XFER (0 << 12)
183#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
184#define DWC_CFGL_LOCK_CH_XACT (2 << 12)
185#define DWC_CFGL_LOCK_BUS_XFER (0 << 14)
186#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
187#define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
188#define DWC_CFGL_LOCK_CH (1 << 15)
189#define DWC_CFGL_LOCK_BUS (1 << 16)
190#define DWC_CFGL_HS_DST_POL (1 << 18)
191#define DWC_CFGL_HS_SRC_POL (1 << 19)
192#define DWC_CFGL_MAX_BURST(x) ((x) << 20)
193#define DWC_CFGL_RELOAD_SAR (1 << 30)
194#define DWC_CFGL_RELOAD_DAR (1 << 31)
195
196
197#define DWC_CFGH_FCMODE (1 << 0)
198#define DWC_CFGH_FIFO_MODE (1 << 1)
199#define DWC_CFGH_PROTCTL(x) ((x) << 2)
200#define DWC_CFGH_DS_UPD_EN (1 << 5)
201#define DWC_CFGH_SS_UPD_EN (1 << 6)
202#define DWC_CFGH_SRC_PER(x) ((x) << 7)
203#define DWC_CFGH_DST_PER(x) ((x) << 11)
204
205
206#define DWC_SGR_SGI(x) ((x) << 0)
207#define DWC_SGR_SGC(x) ((x) << 20)
208
209
210#define DWC_DSR_DSI(x) ((x) << 0)
211#define DWC_DSR_DSC(x) ((x) << 20)
212
213
214#define DW_CFG_DMA_EN (1 << 0)
215
216enum dw_dmac_flags {
217 DW_DMA_IS_CYCLIC = 0,
218 DW_DMA_IS_SOFT_LLP = 1,
219 DW_DMA_IS_PAUSED = 2,
220 DW_DMA_IS_INITIALIZED = 3,
221};
222
223struct dw_dma_chan {
224 struct dma_chan chan;
225 void __iomem *ch_regs;
226 u8 mask;
227 u8 priority;
228 enum dma_transfer_direction direction;
229
230
231 struct list_head *tx_node_active;
232
233 spinlock_t lock;
234
235
236 unsigned long flags;
237 struct list_head active_list;
238 struct list_head queue;
239 struct dw_cyclic_desc *cdesc;
240
241 unsigned int descs_allocated;
242
243
244 unsigned int block_size;
245 bool nollp;
246
247
248 struct dw_dma_slave dws;
249
250
251 struct dma_slave_config dma_sconfig;
252};
253
254static inline struct dw_dma_chan_regs __iomem *
255__dwc_regs(struct dw_dma_chan *dwc)
256{
257 return dwc->ch_regs;
258}
259
260#define channel_readl(dwc, name) \
261 dma_readl_native(&(__dwc_regs(dwc)->name))
262#define channel_writel(dwc, name, val) \
263 dma_writel_native((val), &(__dwc_regs(dwc)->name))
264
265static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
266{
267 return container_of(chan, struct dw_dma_chan, chan);
268}
269
270struct dw_dma {
271 struct dma_device dma;
272 void __iomem *regs;
273 struct dma_pool *desc_pool;
274 struct tasklet_struct tasklet;
275
276
277 struct dw_dma_chan *chan;
278 u8 all_chan_mask;
279 u8 in_use;
280
281
282 struct dw_dma_platform_data *pdata;
283};
284
285static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
286{
287 return dw->regs;
288}
289
290#define dma_readl(dw, name) \
291 dma_readl_native(&(__dw_regs(dw)->name))
292#define dma_writel(dw, name, val) \
293 dma_writel_native((val), &(__dw_regs(dw)->name))
294
295#define channel_set_bit(dw, reg, mask) \
296 dma_writel(dw, reg, ((mask) << 8) | (mask))
297#define channel_clear_bit(dw, reg, mask) \
298 dma_writel(dw, reg, ((mask) << 8) | 0)
299
300static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
301{
302 return container_of(ddev, struct dw_dma, dma);
303}
304
305#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
306typedef __be32 __dw32;
307#else
308typedef __le32 __dw32;
309#endif
310
311
312struct dw_lli {
313
314 __dw32 sar;
315 __dw32 dar;
316 __dw32 llp;
317 __dw32 ctllo;
318
319 __dw32 ctlhi;
320
321
322
323 __dw32 sstat;
324 __dw32 dstat;
325};
326
327struct dw_desc {
328
329 struct dw_lli lli;
330
331#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
332#define lli_set(d, reg, v) ((d)->lli.reg |= cpu_to_be32(v))
333#define lli_clear(d, reg, v) ((d)->lli.reg &= ~cpu_to_be32(v))
334#define lli_read(d, reg) be32_to_cpu((d)->lli.reg)
335#define lli_write(d, reg, v) ((d)->lli.reg = cpu_to_be32(v))
336#else
337#define lli_set(d, reg, v) ((d)->lli.reg |= cpu_to_le32(v))
338#define lli_clear(d, reg, v) ((d)->lli.reg &= ~cpu_to_le32(v))
339#define lli_read(d, reg) le32_to_cpu((d)->lli.reg)
340#define lli_write(d, reg, v) ((d)->lli.reg = cpu_to_le32(v))
341#endif
342
343
344 struct list_head desc_node;
345 struct list_head tx_list;
346 struct dma_async_tx_descriptor txd;
347 size_t len;
348 size_t total_len;
349 u32 residue;
350};
351
352#define to_dw_desc(h) list_entry(h, struct dw_desc, desc_node)
353
354static inline struct dw_desc *
355txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
356{
357 return container_of(txd, struct dw_desc, txd);
358}
359