1/* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * Freescale DCU drm device driver 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12#ifndef __FSL_DCU_DRM_DRV_H__ 13#define __FSL_DCU_DRM_DRV_H__ 14 15#include "fsl_dcu_drm_crtc.h" 16#include "fsl_dcu_drm_output.h" 17#include "fsl_dcu_drm_plane.h" 18 19#define DCU_DCU_MODE 0x0010 20#define DCU_MODE_BLEND_ITER(x) ((x) << 20) 21#define DCU_MODE_RASTER_EN BIT(14) 22#define DCU_MODE_DCU_MODE(x) (x) 23#define DCU_MODE_DCU_MODE_MASK 0x03 24#define DCU_MODE_OFF 0 25#define DCU_MODE_NORMAL 1 26#define DCU_MODE_TEST 2 27#define DCU_MODE_COLORBAR 3 28 29#define DCU_BGND 0x0014 30#define DCU_BGND_R(x) ((x) << 16) 31#define DCU_BGND_G(x) ((x) << 8) 32#define DCU_BGND_B(x) (x) 33 34#define DCU_DISP_SIZE 0x0018 35#define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16) 36/*Regisiter value 1/16 of horizontal resolution*/ 37#define DCU_DISP_SIZE_DELTA_X(x) ((x) >> 4) 38 39#define DCU_HSYN_PARA 0x001c 40#define DCU_HSYN_PARA_BP(x) ((x) << 22) 41#define DCU_HSYN_PARA_PW(x) ((x) << 11) 42#define DCU_HSYN_PARA_FP(x) (x) 43 44#define DCU_VSYN_PARA 0x0020 45#define DCU_VSYN_PARA_BP(x) ((x) << 22) 46#define DCU_VSYN_PARA_PW(x) ((x) << 11) 47#define DCU_VSYN_PARA_FP(x) (x) 48 49#define DCU_SYN_POL 0x0024 50#define DCU_SYN_POL_INV_PXCK BIT(6) 51#define DCU_SYN_POL_NEG BIT(5) 52#define DCU_SYN_POL_INV_VS_LOW BIT(1) 53#define DCU_SYN_POL_INV_HS_LOW BIT(0) 54 55#define DCU_THRESHOLD 0x0028 56#define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16) 57#define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8) 58#define DCU_THRESHOLD_OUT_BUF_LOW(x) (x) 59#define BF_VS_VAL 0x03 60#define BUF_MAX_VAL 0x78 61#define BUF_MIN_VAL 0x0a 62 63#define DCU_INT_STATUS 0x002C 64#define DCU_INT_STATUS_VSYNC BIT(0) 65#define DCU_INT_STATUS_UNDRUN BIT(1) 66#define DCU_INT_STATUS_LSBFVS BIT(2) 67#define DCU_INT_STATUS_VBLANK BIT(3) 68#define DCU_INT_STATUS_CRCREADY BIT(4) 69#define DCU_INT_STATUS_CRCOVERFLOW BIT(5) 70#define DCU_INT_STATUS_P1FIFOLO BIT(6) 71#define DCU_INT_STATUS_P1FIFOHI BIT(7) 72#define DCU_INT_STATUS_P2FIFOLO BIT(8) 73#define DCU_INT_STATUS_P2FIFOHI BIT(9) 74#define DCU_INT_STATUS_PROGEND BIT(10) 75#define DCU_INT_STATUS_IPMERROR BIT(11) 76#define DCU_INT_STATUS_LYRTRANS BIT(12) 77#define DCU_INT_STATUS_DMATRANS BIT(14) 78#define DCU_INT_STATUS_P3FIFOLO BIT(16) 79#define DCU_INT_STATUS_P3FIFOHI BIT(17) 80#define DCU_INT_STATUS_P4FIFOLO BIT(18) 81#define DCU_INT_STATUS_P4FIFOHI BIT(19) 82#define DCU_INT_STATUS_P1EMPTY BIT(26) 83#define DCU_INT_STATUS_P2EMPTY BIT(27) 84#define DCU_INT_STATUS_P3EMPTY BIT(28) 85#define DCU_INT_STATUS_P4EMPTY BIT(29) 86 87#define DCU_INT_MASK 0x0030 88#define DCU_INT_MASK_VSYNC BIT(0) 89#define DCU_INT_MASK_UNDRUN BIT(1) 90#define DCU_INT_MASK_LSBFVS BIT(2) 91#define DCU_INT_MASK_VBLANK BIT(3) 92#define DCU_INT_MASK_CRCREADY BIT(4) 93#define DCU_INT_MASK_CRCOVERFLOW BIT(5) 94#define DCU_INT_MASK_P1FIFOLO BIT(6) 95#define DCU_INT_MASK_P1FIFOHI BIT(7) 96#define DCU_INT_MASK_P2FIFOLO BIT(8) 97#define DCU_INT_MASK_P2FIFOHI BIT(9) 98#define DCU_INT_MASK_PROGEND BIT(10) 99#define DCU_INT_MASK_IPMERROR BIT(11) 100#define DCU_INT_MASK_LYRTRANS BIT(12) 101#define DCU_INT_MASK_DMATRANS BIT(14) 102#define DCU_INT_MASK_P3FIFOLO BIT(16) 103#define DCU_INT_MASK_P3FIFOHI BIT(17) 104#define DCU_INT_MASK_P4FIFOLO BIT(18) 105#define DCU_INT_MASK_P4FIFOHI BIT(19) 106#define DCU_INT_MASK_P1EMPTY BIT(26) 107#define DCU_INT_MASK_P2EMPTY BIT(27) 108#define DCU_INT_MASK_P3EMPTY BIT(28) 109#define DCU_INT_MASK_P4EMPTY BIT(29) 110 111#define DCU_DIV_RATIO 0x0054 112 113#define DCU_UPDATE_MODE 0x00cc 114#define DCU_UPDATE_MODE_MODE BIT(31) 115#define DCU_UPDATE_MODE_READREG BIT(30) 116 117#define DCU_DCFB_MAX 0x300 118 119#define DCU_CTRLDESCLN(layer, reg) (0x200 + (reg - 1) * 4 + (layer) * 0x40) 120 121#define DCU_LAYER_HEIGHT(x) ((x) << 16) 122#define DCU_LAYER_WIDTH(x) (x) 123 124#define DCU_LAYER_POSY(x) ((x) << 16) 125#define DCU_LAYER_POSX(x) (x) 126 127#define DCU_LAYER_EN BIT(31) 128#define DCU_LAYER_TILE_EN BIT(30) 129#define DCU_LAYER_DATA_SEL_CLUT BIT(29) 130#define DCU_LAYER_SAFETY_EN BIT(28) 131#define DCU_LAYER_TRANS(x) ((x) << 20) 132#define DCU_LAYER_BPP(x) ((x) << 16) 133#define DCU_LAYER_RLE_EN BIT(15) 134#define DCU_LAYER_LUOFFS(x) ((x) << 4) 135#define DCU_LAYER_BB_ON BIT(2) 136#define DCU_LAYER_AB_NONE 0 137#define DCU_LAYER_AB_CHROMA_KEYING 1 138#define DCU_LAYER_AB_WHOLE_FRAME 2 139 140#define DCU_LAYER_CKMAX_R(x) ((x) << 16) 141#define DCU_LAYER_CKMAX_G(x) ((x) << 8) 142#define DCU_LAYER_CKMAX_B(x) (x) 143 144#define DCU_LAYER_CKMIN_R(x) ((x) << 16) 145#define DCU_LAYER_CKMIN_G(x) ((x) << 8) 146#define DCU_LAYER_CKMIN_B(x) (x) 147 148#define DCU_LAYER_TILE_VER(x) ((x) << 16) 149#define DCU_LAYER_TILE_HOR(x) (x) 150 151#define DCU_LAYER_FG_FCOLOR(x) (x) 152 153#define DCU_LAYER_BG_BCOLOR(x) (x) 154 155#define DCU_LAYER_POST_SKIP(x) ((x) << 16) 156#define DCU_LAYER_PRE_SKIP(x) (x) 157 158#define FSL_DCU_RGB565 4 159#define FSL_DCU_RGB888 5 160#define FSL_DCU_ARGB8888 6 161#define FSL_DCU_ARGB1555 11 162#define FSL_DCU_ARGB4444 12 163#define FSL_DCU_YUV422 14 164 165#define VF610_LAYER_REG_NUM 9 166#define LS1021A_LAYER_REG_NUM 10 167 168struct clk; 169struct device; 170struct drm_device; 171 172struct fsl_dcu_soc_data { 173 const char *name; 174 /*total layer number*/ 175 unsigned int total_layer; 176 /*max layer number DCU supported*/ 177 unsigned int max_layer; 178 unsigned int layer_regs; 179}; 180 181struct fsl_dcu_drm_device { 182 struct device *dev; 183 struct device_node *np; 184 struct regmap *regmap; 185 int irq; 186 struct clk *clk; 187 struct clk *pix_clk; 188 struct fsl_tcon *tcon; 189 /*protects hardware register*/ 190 spinlock_t irq_lock; 191 struct drm_device *drm; 192 struct drm_fbdev_cma *fbdev; 193 struct drm_crtc crtc; 194 struct drm_encoder encoder; 195 struct fsl_dcu_drm_connector connector; 196 const struct fsl_dcu_soc_data *soc; 197 struct drm_atomic_state *state; 198}; 199 200void fsl_dcu_fbdev_init(struct drm_device *dev); 201int fsl_dcu_drm_modeset_init(struct fsl_dcu_drm_device *fsl_dev); 202 203#endif /* __FSL_DCU_DRM_DRV_H__ */ 204