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19#include "mdp5_kms.h"
20
21struct mdp5_plane {
22 struct drm_plane base;
23 const char *name;
24
25 enum mdp5_pipe pipe;
26
27 spinlock_t pipe_lock;
28 uint32_t reg_offset;
29 uint32_t caps;
30
31 uint32_t flush_mask;
32
33 uint32_t nformats;
34 uint32_t formats[32];
35};
36#define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
37
38static int mdp5_plane_mode_set(struct drm_plane *plane,
39 struct drm_crtc *crtc, struct drm_framebuffer *fb,
40 int crtc_x, int crtc_y,
41 unsigned int crtc_w, unsigned int crtc_h,
42 uint32_t src_x, uint32_t src_y,
43 uint32_t src_w, uint32_t src_h);
44
45static void set_scanout_locked(struct drm_plane *plane,
46 struct drm_framebuffer *fb);
47
48static struct mdp5_kms *get_kms(struct drm_plane *plane)
49{
50 struct msm_drm_private *priv = plane->dev->dev_private;
51 return to_mdp5_kms(to_mdp_kms(priv->kms));
52}
53
54static bool plane_enabled(struct drm_plane_state *state)
55{
56 return state->fb && state->crtc;
57}
58
59static void mdp5_plane_destroy(struct drm_plane *plane)
60{
61 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
62
63 drm_plane_helper_disable(plane);
64 drm_plane_cleanup(plane);
65
66 kfree(mdp5_plane);
67}
68
69static void mdp5_plane_install_rotation_property(struct drm_device *dev,
70 struct drm_plane *plane)
71{
72 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
73
74 if (!(mdp5_plane->caps & MDP_PIPE_CAP_HFLIP) &&
75 !(mdp5_plane->caps & MDP_PIPE_CAP_VFLIP))
76 return;
77
78 if (!dev->mode_config.rotation_property)
79 dev->mode_config.rotation_property =
80 drm_mode_create_rotation_property(dev,
81 DRM_ROTATE_0 | DRM_REFLECT_X | DRM_REFLECT_Y);
82
83 if (dev->mode_config.rotation_property)
84 drm_object_attach_property(&plane->base,
85 dev->mode_config.rotation_property,
86 DRM_ROTATE_0);
87}
88
89
90static void mdp5_plane_install_properties(struct drm_plane *plane,
91 struct drm_mode_object *obj)
92{
93 struct drm_device *dev = plane->dev;
94 struct msm_drm_private *dev_priv = dev->dev_private;
95 struct drm_property *prop;
96
97#define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
98 prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
99 if (!prop) { \
100 prop = drm_property_##fnc(dev, 0, #name, \
101 ##__VA_ARGS__); \
102 if (!prop) { \
103 dev_warn(dev->dev, \
104 "Create property %s failed\n", \
105 #name); \
106 return; \
107 } \
108 dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
109 } \
110 drm_object_attach_property(&plane->base, prop, init_val); \
111 } while (0)
112
113#define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
114 INSTALL_PROPERTY(name, NAME, init_val, \
115 create_range, min, max)
116
117#define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
118 INSTALL_PROPERTY(name, NAME, init_val, \
119 create_enum, name##_prop_enum_list, \
120 ARRAY_SIZE(name##_prop_enum_list))
121
122 INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
123
124 mdp5_plane_install_rotation_property(dev, plane);
125
126#undef INSTALL_RANGE_PROPERTY
127#undef INSTALL_ENUM_PROPERTY
128#undef INSTALL_PROPERTY
129}
130
131static int mdp5_plane_atomic_set_property(struct drm_plane *plane,
132 struct drm_plane_state *state, struct drm_property *property,
133 uint64_t val)
134{
135 struct drm_device *dev = plane->dev;
136 struct mdp5_plane_state *pstate;
137 struct msm_drm_private *dev_priv = dev->dev_private;
138 int ret = 0;
139
140 pstate = to_mdp5_plane_state(state);
141
142#define SET_PROPERTY(name, NAME, type) do { \
143 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
144 pstate->name = (type)val; \
145 DBG("Set property %s %d", #name, (type)val); \
146 goto done; \
147 } \
148 } while (0)
149
150 SET_PROPERTY(zpos, ZPOS, uint8_t);
151
152 dev_err(dev->dev, "Invalid property\n");
153 ret = -EINVAL;
154done:
155 return ret;
156#undef SET_PROPERTY
157}
158
159static int mdp5_plane_atomic_get_property(struct drm_plane *plane,
160 const struct drm_plane_state *state,
161 struct drm_property *property, uint64_t *val)
162{
163 struct drm_device *dev = plane->dev;
164 struct mdp5_plane_state *pstate;
165 struct msm_drm_private *dev_priv = dev->dev_private;
166 int ret = 0;
167
168 pstate = to_mdp5_plane_state(state);
169
170#define GET_PROPERTY(name, NAME, type) do { \
171 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
172 *val = pstate->name; \
173 DBG("Get property %s %lld", #name, *val); \
174 goto done; \
175 } \
176 } while (0)
177
178 GET_PROPERTY(zpos, ZPOS, uint8_t);
179
180 dev_err(dev->dev, "Invalid property\n");
181 ret = -EINVAL;
182done:
183 return ret;
184#undef SET_PROPERTY
185}
186
187static void mdp5_plane_reset(struct drm_plane *plane)
188{
189 struct mdp5_plane_state *mdp5_state;
190
191 if (plane->state && plane->state->fb)
192 drm_framebuffer_unreference(plane->state->fb);
193
194 kfree(to_mdp5_plane_state(plane->state));
195 mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
196
197
198 mdp5_state->alpha = 255;
199 mdp5_state->premultiplied = 0;
200
201 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
202 mdp5_state->zpos = STAGE_BASE;
203 else
204 mdp5_state->zpos = STAGE0 + drm_plane_index(plane);
205
206 mdp5_state->base.plane = plane;
207
208 plane->state = &mdp5_state->base;
209}
210
211static struct drm_plane_state *
212mdp5_plane_duplicate_state(struct drm_plane *plane)
213{
214 struct mdp5_plane_state *mdp5_state;
215
216 if (WARN_ON(!plane->state))
217 return NULL;
218
219 mdp5_state = kmemdup(to_mdp5_plane_state(plane->state),
220 sizeof(*mdp5_state), GFP_KERNEL);
221
222 if (mdp5_state && mdp5_state->base.fb)
223 drm_framebuffer_reference(mdp5_state->base.fb);
224
225 mdp5_state->mode_changed = false;
226 mdp5_state->pending = false;
227
228 return &mdp5_state->base;
229}
230
231static void mdp5_plane_destroy_state(struct drm_plane *plane,
232 struct drm_plane_state *state)
233{
234 if (state->fb)
235 drm_framebuffer_unreference(state->fb);
236
237 kfree(to_mdp5_plane_state(state));
238}
239
240static const struct drm_plane_funcs mdp5_plane_funcs = {
241 .update_plane = drm_atomic_helper_update_plane,
242 .disable_plane = drm_atomic_helper_disable_plane,
243 .destroy = mdp5_plane_destroy,
244 .set_property = drm_atomic_helper_plane_set_property,
245 .atomic_set_property = mdp5_plane_atomic_set_property,
246 .atomic_get_property = mdp5_plane_atomic_get_property,
247 .reset = mdp5_plane_reset,
248 .atomic_duplicate_state = mdp5_plane_duplicate_state,
249 .atomic_destroy_state = mdp5_plane_destroy_state,
250};
251
252static int mdp5_plane_prepare_fb(struct drm_plane *plane,
253 struct drm_plane_state *new_state)
254{
255 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
256 struct mdp5_kms *mdp5_kms = get_kms(plane);
257 struct drm_framebuffer *fb = new_state->fb;
258
259 if (!new_state->fb)
260 return 0;
261
262 DBG("%s: prepare: FB[%u]", mdp5_plane->name, fb->base.id);
263 return msm_framebuffer_prepare(fb, mdp5_kms->id);
264}
265
266static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
267 struct drm_plane_state *old_state)
268{
269 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
270 struct mdp5_kms *mdp5_kms = get_kms(plane);
271 struct drm_framebuffer *fb = old_state->fb;
272
273 if (!fb)
274 return;
275
276 DBG("%s: cleanup: FB[%u]", mdp5_plane->name, fb->base.id);
277 msm_framebuffer_cleanup(fb, mdp5_kms->id);
278}
279
280static int mdp5_plane_atomic_check(struct drm_plane *plane,
281 struct drm_plane_state *state)
282{
283 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
284 struct drm_plane_state *old_state = plane->state;
285 const struct mdp_format *format;
286 bool vflip, hflip;
287
288 DBG("%s: check (%d -> %d)", mdp5_plane->name,
289 plane_enabled(old_state), plane_enabled(state));
290
291 if (plane_enabled(state)) {
292 format = to_mdp_format(msm_framebuffer_format(state->fb));
293 if (MDP_FORMAT_IS_YUV(format) &&
294 !pipe_supports_yuv(mdp5_plane->caps)) {
295 DBG("Pipe doesn't support YUV\n");
296
297 return -EINVAL;
298 }
299
300 if (!(mdp5_plane->caps & MDP_PIPE_CAP_SCALE) &&
301 (((state->src_w >> 16) != state->crtc_w) ||
302 ((state->src_h >> 16) != state->crtc_h))) {
303 DBG("Pipe doesn't support scaling (%dx%d -> %dx%d)\n",
304 state->src_w >> 16, state->src_h >> 16,
305 state->crtc_w, state->crtc_h);
306
307 return -EINVAL;
308 }
309
310 hflip = !!(state->rotation & DRM_REFLECT_X);
311 vflip = !!(state->rotation & DRM_REFLECT_Y);
312 if ((vflip && !(mdp5_plane->caps & MDP_PIPE_CAP_VFLIP)) ||
313 (hflip && !(mdp5_plane->caps & MDP_PIPE_CAP_HFLIP))) {
314 DBG("Pipe doesn't support flip\n");
315
316 return -EINVAL;
317 }
318 }
319
320 if (plane_enabled(state) && plane_enabled(old_state)) {
321
322 bool full_modeset = false;
323 if (state->fb->pixel_format != old_state->fb->pixel_format) {
324 DBG("%s: pixel_format change!", mdp5_plane->name);
325 full_modeset = true;
326 }
327 if (state->src_w != old_state->src_w) {
328 DBG("%s: src_w change!", mdp5_plane->name);
329 full_modeset = true;
330 }
331 if (to_mdp5_plane_state(old_state)->pending) {
332 DBG("%s: still pending!", mdp5_plane->name);
333 full_modeset = true;
334 }
335 if (full_modeset) {
336 struct drm_crtc_state *crtc_state =
337 drm_atomic_get_crtc_state(state->state, state->crtc);
338 crtc_state->mode_changed = true;
339 to_mdp5_plane_state(state)->mode_changed = true;
340 }
341 } else {
342 to_mdp5_plane_state(state)->mode_changed = true;
343 }
344
345 return 0;
346}
347
348static void mdp5_plane_atomic_update(struct drm_plane *plane,
349 struct drm_plane_state *old_state)
350{
351 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
352 struct drm_plane_state *state = plane->state;
353
354 DBG("%s: update", mdp5_plane->name);
355
356 if (!plane_enabled(state)) {
357 to_mdp5_plane_state(state)->pending = true;
358 } else if (to_mdp5_plane_state(state)->mode_changed) {
359 int ret;
360 to_mdp5_plane_state(state)->pending = true;
361 ret = mdp5_plane_mode_set(plane,
362 state->crtc, state->fb,
363 state->crtc_x, state->crtc_y,
364 state->crtc_w, state->crtc_h,
365 state->src_x, state->src_y,
366 state->src_w, state->src_h);
367
368 WARN_ON(ret < 0);
369 } else {
370 unsigned long flags;
371 spin_lock_irqsave(&mdp5_plane->pipe_lock, flags);
372 set_scanout_locked(plane, state->fb);
373 spin_unlock_irqrestore(&mdp5_plane->pipe_lock, flags);
374 }
375}
376
377static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = {
378 .prepare_fb = mdp5_plane_prepare_fb,
379 .cleanup_fb = mdp5_plane_cleanup_fb,
380 .atomic_check = mdp5_plane_atomic_check,
381 .atomic_update = mdp5_plane_atomic_update,
382};
383
384static void set_scanout_locked(struct drm_plane *plane,
385 struct drm_framebuffer *fb)
386{
387 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
388 struct mdp5_kms *mdp5_kms = get_kms(plane);
389 enum mdp5_pipe pipe = mdp5_plane->pipe;
390
391 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
392 MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
393 MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
394
395 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
396 MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
397 MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
398
399 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
400 msm_framebuffer_iova(fb, mdp5_kms->id, 0));
401 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
402 msm_framebuffer_iova(fb, mdp5_kms->id, 1));
403 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
404 msm_framebuffer_iova(fb, mdp5_kms->id, 2));
405 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
406 msm_framebuffer_iova(fb, mdp5_kms->id, 3));
407
408 plane->fb = fb;
409}
410
411
412static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
413{
414 uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &
415 ~MDP5_PIPE_OP_MODE_CSC_1_EN;
416
417 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);
418}
419
420
421static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
422 struct csc_cfg *csc)
423{
424 uint32_t i, mode = 0;
425 uint32_t *matrix;
426
427 if (unlikely(!csc))
428 return;
429
430 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type))
431 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV);
432 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type))
433 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV);
434 mode |= MDP5_PIPE_OP_MODE_CSC_1_EN;
435 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);
436
437 matrix = csc->matrix;
438 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),
439 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) |
440 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1]));
441 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),
442 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) |
443 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3]));
444 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),
445 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) |
446 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5]));
447 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),
448 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) |
449 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7]));
450 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),
451 MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8]));
452
453 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) {
454 uint32_t *pre_clamp = csc->pre_clamp;
455 uint32_t *post_clamp = csc->post_clamp;
456
457 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),
458 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) |
459 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i]));
460
461 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),
462 MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) |
463 MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i]));
464
465 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),
466 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i]));
467
468 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),
469 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i]));
470 }
471}
472
473#define PHASE_STEP_SHIFT 21
474#define DOWN_SCALE_RATIO_MAX 32
475
476static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
477{
478 uint32_t unit;
479
480 if (src == 0 || dst == 0)
481 return -EINVAL;
482
483
484
485
486
487
488
489 if (src > (dst * DOWN_SCALE_RATIO_MAX))
490 return -EOVERFLOW;
491
492 unit = 1 << PHASE_STEP_SHIFT;
493 *out_phase = mult_frac(unit, src, dst);
494
495 return 0;
496}
497
498static int calc_scalex_steps(struct drm_plane *plane,
499 uint32_t pixel_format, uint32_t src, uint32_t dest,
500 uint32_t phasex_steps[COMP_MAX])
501{
502 struct mdp5_kms *mdp5_kms = get_kms(plane);
503 struct device *dev = mdp5_kms->dev->dev;
504 uint32_t phasex_step;
505 unsigned int hsub;
506 int ret;
507
508 ret = calc_phase_step(src, dest, &phasex_step);
509 if (ret) {
510 dev_err(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret);
511 return ret;
512 }
513
514 hsub = drm_format_horz_chroma_subsampling(pixel_format);
515
516 phasex_steps[COMP_0] = phasex_step;
517 phasex_steps[COMP_3] = phasex_step;
518 phasex_steps[COMP_1_2] = phasex_step / hsub;
519
520 return 0;
521}
522
523static int calc_scaley_steps(struct drm_plane *plane,
524 uint32_t pixel_format, uint32_t src, uint32_t dest,
525 uint32_t phasey_steps[COMP_MAX])
526{
527 struct mdp5_kms *mdp5_kms = get_kms(plane);
528 struct device *dev = mdp5_kms->dev->dev;
529 uint32_t phasey_step;
530 unsigned int vsub;
531 int ret;
532
533 ret = calc_phase_step(src, dest, &phasey_step);
534 if (ret) {
535 dev_err(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret);
536 return ret;
537 }
538
539 vsub = drm_format_vert_chroma_subsampling(pixel_format);
540
541 phasey_steps[COMP_0] = phasey_step;
542 phasey_steps[COMP_3] = phasey_step;
543 phasey_steps[COMP_1_2] = phasey_step / vsub;
544
545 return 0;
546}
547
548static uint32_t get_scale_config(const struct mdp_format *format,
549 uint32_t src, uint32_t dst, bool horz)
550{
551 bool scaling = format->is_yuv ? true : (src != dst);
552 uint32_t sub, pix_fmt = format->base.pixel_format;
553 uint32_t ya_filter, uv_filter;
554 bool yuv = format->is_yuv;
555
556 if (!scaling)
557 return 0;
558
559 if (yuv) {
560 sub = horz ? drm_format_horz_chroma_subsampling(pix_fmt) :
561 drm_format_vert_chroma_subsampling(pix_fmt);
562 uv_filter = ((src / sub) <= dst) ?
563 SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
564 }
565 ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
566
567 if (horz)
568 return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
569 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) |
570 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) |
571 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter));
572 else
573 return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
574 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) |
575 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) |
576 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
577}
578
579static void calc_pixel_ext(const struct mdp_format *format,
580 uint32_t src, uint32_t dst, uint32_t phase_step[2],
581 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
582 bool horz)
583{
584 bool scaling = format->is_yuv ? true : (src != dst);
585 int i;
586
587
588
589
590
591
592
593
594
595 for (i = 0; i < COMP_MAX; i++) {
596 pix_ext_edge1[i] = 0;
597 pix_ext_edge2[i] = scaling ? 1 : 0;
598 }
599}
600
601static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
602 const struct mdp_format *format,
603 uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
604 uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
605{
606 uint32_t pix_fmt = format->base.pixel_format;
607 uint32_t lr, tb, req;
608 int i;
609
610 for (i = 0; i < COMP_MAX; i++) {
611 uint32_t roi_w = src_w;
612 uint32_t roi_h = src_h;
613
614 if (format->is_yuv && i == COMP_1_2) {
615 roi_w /= drm_format_horz_chroma_subsampling(pix_fmt);
616 roi_h /= drm_format_vert_chroma_subsampling(pix_fmt);
617 }
618
619 lr = (pe_left[i] >= 0) ?
620 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) :
621 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]);
622
623 lr |= (pe_right[i] >= 0) ?
624 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) :
625 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]);
626
627 tb = (pe_top[i] >= 0) ?
628 MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) :
629 MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]);
630
631 tb |= (pe_bottom[i] >= 0) ?
632 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) :
633 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]);
634
635 req = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w +
636 pe_left[i] + pe_right[i]);
637
638 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h +
639 pe_top[i] + pe_bottom[i]);
640
641 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr);
642 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb);
643 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req);
644
645 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i,
646 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT),
647 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT),
648 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF),
649 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF),
650 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT));
651
652 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i,
653 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT),
654 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT),
655 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF),
656 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF),
657 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM));
658 }
659}
660
661
662static int mdp5_plane_mode_set(struct drm_plane *plane,
663 struct drm_crtc *crtc, struct drm_framebuffer *fb,
664 int crtc_x, int crtc_y,
665 unsigned int crtc_w, unsigned int crtc_h,
666 uint32_t src_x, uint32_t src_y,
667 uint32_t src_w, uint32_t src_h)
668{
669 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
670 struct drm_plane_state *pstate = plane->state;
671 struct mdp5_kms *mdp5_kms = get_kms(plane);
672 enum mdp5_pipe pipe = mdp5_plane->pipe;
673 const struct mdp_format *format;
674 uint32_t nplanes, config = 0;
675 uint32_t phasex_step[COMP_MAX] = {0,}, phasey_step[COMP_MAX] = {0,};
676 bool pe = mdp5_plane->caps & MDP_PIPE_CAP_SW_PIX_EXT;
677 int pe_left[COMP_MAX], pe_right[COMP_MAX];
678 int pe_top[COMP_MAX], pe_bottom[COMP_MAX];
679 uint32_t hdecm = 0, vdecm = 0;
680 uint32_t pix_format;
681 bool vflip, hflip;
682 unsigned long flags;
683 int ret;
684
685 nplanes = drm_format_num_planes(fb->pixel_format);
686
687
688 if (WARN_ON(nplanes > pipe2nclients(pipe)))
689 return -EINVAL;
690
691 format = to_mdp_format(msm_framebuffer_format(fb));
692 pix_format = format->base.pixel_format;
693
694
695 src_x = src_x >> 16;
696 src_y = src_y >> 16;
697 src_w = src_w >> 16;
698 src_h = src_h >> 16;
699
700 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", mdp5_plane->name,
701 fb->base.id, src_x, src_y, src_w, src_h,
702 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
703
704
705 if (mdp5_kms->smp) {
706 ret = mdp5_smp_request(mdp5_kms->smp,
707 mdp5_plane->pipe, format, src_w, false);
708 if (ret)
709 return ret;
710 }
711
712
713
714
715
716
717
718 if (mdp5_kms->smp)
719 mdp5_smp_configure(mdp5_kms->smp, pipe);
720
721 ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, phasex_step);
722 if (ret)
723 return ret;
724
725 ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, phasey_step);
726 if (ret)
727 return ret;
728
729 if (mdp5_plane->caps & MDP_PIPE_CAP_SW_PIX_EXT) {
730 calc_pixel_ext(format, src_w, crtc_w, phasex_step,
731 pe_left, pe_right, true);
732 calc_pixel_ext(format, src_h, crtc_h, phasey_step,
733 pe_top, pe_bottom, false);
734 }
735
736
737
738
739 config |= get_scale_config(format, src_w, crtc_w, true);
740 config |= get_scale_config(format, src_h, crtc_h, false);
741 DBG("scale config = %x", config);
742
743 hflip = !!(pstate->rotation & DRM_REFLECT_X);
744 vflip = !!(pstate->rotation & DRM_REFLECT_Y);
745
746 spin_lock_irqsave(&mdp5_plane->pipe_lock, flags);
747
748 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
749 MDP5_PIPE_SRC_IMG_SIZE_WIDTH(fb->width) |
750 MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(fb->height));
751
752 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
753 MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
754 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
755
756 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
757 MDP5_PIPE_SRC_XY_X(src_x) |
758 MDP5_PIPE_SRC_XY_Y(src_y));
759
760 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
761 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
762 MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
763
764 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
765 MDP5_PIPE_OUT_XY_X(crtc_x) |
766 MDP5_PIPE_OUT_XY_Y(crtc_y));
767
768 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
769 MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
770 MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
771 MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
772 MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
773 COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
774 MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
775 MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
776 COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
777 MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
778 MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
779
780 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
781 MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
782 MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
783 MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
784 MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
785
786 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
787 (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
788 (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) |
789 COND(pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) |
790 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
791
792
793 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
794
795 if (mdp5_plane->caps & MDP_PIPE_CAP_SW_PIX_EXT)
796 mdp5_write_pixel_ext(mdp5_kms, pipe, format,
797 src_w, pe_left, pe_right,
798 src_h, pe_top, pe_bottom);
799
800 if (mdp5_plane->caps & MDP_PIPE_CAP_SCALE) {
801 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
802 phasex_step[COMP_0]);
803 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
804 phasey_step[COMP_0]);
805 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
806 phasex_step[COMP_1_2]);
807 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
808 phasey_step[COMP_1_2]);
809 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
810 MDP5_PIPE_DECIMATION_VERT(vdecm) |
811 MDP5_PIPE_DECIMATION_HORZ(hdecm));
812 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe), config);
813 }
814
815 if (mdp5_plane->caps & MDP_PIPE_CAP_CSC) {
816 if (MDP_FORMAT_IS_YUV(format))
817 csc_enable(mdp5_kms, pipe,
818 mdp_get_default_csc_cfg(CSC_YUV2RGB));
819 else
820 csc_disable(mdp5_kms, pipe);
821 }
822
823 set_scanout_locked(plane, fb);
824
825 spin_unlock_irqrestore(&mdp5_plane->pipe_lock, flags);
826
827 return ret;
828}
829
830void mdp5_plane_complete_flip(struct drm_plane *plane)
831{
832 struct mdp5_kms *mdp5_kms = get_kms(plane);
833 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
834 enum mdp5_pipe pipe = mdp5_plane->pipe;
835
836 DBG("%s: complete flip", mdp5_plane->name);
837
838 if (mdp5_kms->smp)
839 mdp5_smp_commit(mdp5_kms->smp, pipe);
840
841 to_mdp5_plane_state(plane->state)->pending = false;
842}
843
844enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
845{
846 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
847 return mdp5_plane->pipe;
848}
849
850uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
851{
852 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
853
854 return mdp5_plane->flush_mask;
855}
856
857
858void mdp5_plane_complete_commit(struct drm_plane *plane,
859 struct drm_plane_state *state)
860{
861 struct mdp5_kms *mdp5_kms = get_kms(plane);
862 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
863 enum mdp5_pipe pipe = mdp5_plane->pipe;
864
865 if (!plane_enabled(plane->state) && mdp5_kms->smp) {
866 DBG("%s: free SMP", mdp5_plane->name);
867 mdp5_smp_release(mdp5_kms->smp, pipe);
868 }
869}
870
871
872struct drm_plane *mdp5_plane_init(struct drm_device *dev,
873 enum mdp5_pipe pipe, bool private_plane, uint32_t reg_offset,
874 uint32_t caps)
875{
876 struct drm_plane *plane = NULL;
877 struct mdp5_plane *mdp5_plane;
878 int ret;
879 enum drm_plane_type type;
880
881 mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
882 if (!mdp5_plane) {
883 ret = -ENOMEM;
884 goto fail;
885 }
886
887 plane = &mdp5_plane->base;
888
889 mdp5_plane->pipe = pipe;
890 mdp5_plane->name = pipe2name(pipe);
891 mdp5_plane->caps = caps;
892
893 mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
894 ARRAY_SIZE(mdp5_plane->formats),
895 !pipe_supports_yuv(mdp5_plane->caps));
896
897 mdp5_plane->flush_mask = mdp_ctl_flush_mask_pipe(pipe);
898 mdp5_plane->reg_offset = reg_offset;
899 spin_lock_init(&mdp5_plane->pipe_lock);
900
901 type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
902 ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
903 mdp5_plane->formats, mdp5_plane->nformats,
904 type, NULL);
905 if (ret)
906 goto fail;
907
908 drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
909
910 mdp5_plane_install_properties(plane, &plane->base);
911
912 return plane;
913
914fail:
915 if (plane)
916 mdp5_plane_destroy(plane);
917
918 return ERR_PTR(ret);
919}
920
