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18#include <drm/drmP.h>
19#include <drm/drm_crtc.h>
20#include <drm/drm_crtc_helper.h>
21#include <drm/drm_dp_helper.h>
22#include <drm/drm_encoder_slave.h>
23
24#include <linux/clk.h>
25#include <linux/delay.h>
26#include <linux/device.h>
27#include <linux/module.h>
28#include <linux/mutex.h>
29#include <linux/phy/phy.h>
30#include <linux/phy/phy-zynqmp.h>
31#include <linux/platform_device.h>
32#include <linux/pm_runtime.h>
33
34#include "xilinx_drm_dp_sub.h"
35#include "xilinx_drm_drv.h"
36
37static uint xilinx_drm_dp_aux_timeout_ms = 50;
38module_param_named(aux_timeout_ms, xilinx_drm_dp_aux_timeout_ms, uint, 0444);
39MODULE_PARM_DESC(aux_timeout_ms,
40 "DP aux timeout value in msec (default: 50)");
41
42
43#define XILINX_DP_TX_LINK_BW_SET 0x0
44#define XILINX_DP_TX_LANE_CNT_SET 0x4
45#define XILINX_DP_TX_ENHANCED_FRAME_EN 0x8
46#define XILINX_DP_TX_TRAINING_PATTERN_SET 0xc
47#define XILINX_DP_TX_SCRAMBLING_DISABLE 0x14
48#define XILINX_DP_TX_DOWNSPREAD_CTL 0x18
49#define XILINX_DP_TX_SW_RESET 0x1c
50#define XILINX_DP_TX_SW_RESET_STREAM1 (1 << 0)
51#define XILINX_DP_TX_SW_RESET_STREAM2 (1 << 1)
52#define XILINX_DP_TX_SW_RESET_STREAM3 (1 << 2)
53#define XILINX_DP_TX_SW_RESET_STREAM4 (1 << 3)
54#define XILINX_DP_TX_SW_RESET_AUX (1 << 7)
55#define XILINX_DP_TX_SW_RESET_ALL (XILINX_DP_TX_SW_RESET_STREAM1 | \
56 XILINX_DP_TX_SW_RESET_STREAM2 | \
57 XILINX_DP_TX_SW_RESET_STREAM3 | \
58 XILINX_DP_TX_SW_RESET_STREAM4 | \
59 XILINX_DP_TX_SW_RESET_AUX)
60
61
62#define XILINX_DP_TX_ENABLE 0x80
63#define XILINX_DP_TX_ENABLE_MAIN_STREAM 0x84
64#define XILINX_DP_TX_FORCE_SCRAMBLER_RESET 0xc0
65#define XILINX_DP_TX_VERSION 0xf8
66#define XILINX_DP_TX_VERSION_MAJOR_MASK (0xff << 24)
67#define XILINX_DP_TX_VERSION_MAJOR_SHIFT 24
68#define XILINX_DP_TX_VERSION_MINOR_MASK (0xff << 16)
69#define XILINX_DP_TX_VERSION_MINOR_SHIFT 16
70#define XILINX_DP_TX_VERSION_REVISION_MASK (0xf << 12)
71#define XILINX_DP_TX_VERSION_REVISION_SHIFT 12
72#define XILINX_DP_TX_VERSION_PATCH_MASK (0xf << 8)
73#define XILINX_DP_TX_VERSION_PATCH_SHIFT 8
74#define XILINX_DP_TX_VERSION_INTERNAL_MASK (0xff << 0)
75#define XILINX_DP_TX_VERSION_INTERNAL_SHIFT 0
76
77
78#define XILINX_DP_TX_CORE_ID 0xfc
79#define XILINX_DP_TX_CORE_ID_MAJOR_MASK (0xff << 24)
80#define XILINX_DP_TX_CORE_ID_MAJOR_SHIFT 24
81#define XILINX_DP_TX_CORE_ID_MINOR_MASK (0xff << 16)
82#define XILINX_DP_TX_CORE_ID_MINOR_SHIFT 16
83#define XILINX_DP_TX_CORE_ID_REVISION_MASK (0xff << 8)
84#define XILINX_DP_TX_CORE_ID_REVISION_SHIFT 8
85#define XILINX_DP_TX_CORE_ID_DIRECTION (1 << 0)
86
87
88#define XILINX_DP_TX_AUX_COMMAND 0x100
89#define XILINX_DP_TX_AUX_COMMAND_CMD_SHIFT 8
90#define XILINX_DP_TX_AUX_COMMAND_ADDRESS_ONLY BIT(12)
91#define XILINX_DP_TX_AUX_COMMAND_BYTES_SHIFT 0
92#define XILINX_DP_TX_AUX_WRITE_FIFO 0x104
93#define XILINX_DP_TX_AUX_ADDRESS 0x108
94#define XILINX_DP_TX_CLK_DIVIDER 0x10c
95#define XILINX_DP_TX_CLK_DIVIDER_MHZ 1000000
96#define XILINX_DP_TX_CLK_DIVIDER_AUX_FILTER_SHIFT 8
97#define XILINX_DP_TX_INTR_SIGNAL_STATE 0x130
98#define XILINX_DP_TX_INTR_SIGNAL_STATE_HPD (1 << 0)
99#define XILINX_DP_TX_INTR_SIGNAL_STATE_REQUEST (1 << 1)
100#define XILINX_DP_TX_INTR_SIGNAL_STATE_REPLY (1 << 2)
101#define XILINX_DP_TX_INTR_SIGNAL_STATE_REPLY_TIMEOUT (1 << 3)
102#define XILINX_DP_TX_AUX_REPLY_DATA 0x134
103#define XILINX_DP_TX_AUX_REPLY_CODE 0x138
104#define XILINX_DP_TX_AUX_REPLY_CODE_AUX_ACK (0)
105#define XILINX_DP_TX_AUX_REPLY_CODE_AUX_NACK (1 << 0)
106#define XILINX_DP_TX_AUX_REPLY_CODE_AUX_DEFER (1 << 1)
107#define XILINX_DP_TX_AUX_REPLY_CODE_I2C_ACK (0)
108#define XILINX_DP_TX_AUX_REPLY_CODE_I2C_NACK (1 << 2)
109#define XILINX_DP_TX_AUX_REPLY_CODE_I2C_DEFER (1 << 3)
110#define XILINX_DP_TX_AUX_REPLY_CNT 0x13c
111#define XILINX_DP_TX_AUX_REPLY_CNT_MASK 0xff
112#define XILINX_DP_TX_INTR_STATUS 0x140
113#define XILINX_DP_TX_INTR_MASK 0x144
114#define XILINX_DP_TX_INTR_HPD_IRQ (1 << 0)
115#define XILINX_DP_TX_INTR_HPD_EVENT (1 << 1)
116#define XILINX_DP_TX_INTR_REPLY_RECV (1 << 2)
117#define XILINX_DP_TX_INTR_REPLY_TIMEOUT (1 << 3)
118#define XILINX_DP_TX_INTR_HPD_PULSE (1 << 4)
119#define XILINX_DP_TX_INTR_EXT_PKT_TXD (1 << 5)
120#define XILINX_DP_TX_INTR_LIV_ABUF_UNDRFLW (1 << 12)
121#define XILINX_DP_TX_INTR_VBLANK_START (1 << 13)
122#define XILINX_DP_TX_INTR_PIXEL0_MATCH (1 << 14)
123#define XILINX_DP_TX_INTR_PIXEL1_MATCH (1 << 15)
124#define XILINX_DP_TX_INTR_CHBUF_UNDERFLW_MASK 0x3f0000
125#define XILINX_DP_TX_INTR_CHBUF_OVERFLW_MASK 0xfc00000
126#define XILINX_DP_TX_INTR_CUST_TS_2 (1 << 28)
127#define XILINX_DP_TX_INTR_CUST_TS (1 << 29)
128#define XILINX_DP_TX_INTR_EXT_VSYNC_TS (1 << 30)
129#define XILINX_DP_TX_INTR_VSYNC_TS (1 << 31)
130#define XILINX_DP_TX_INTR_ALL (XILINX_DP_TX_INTR_HPD_IRQ | \
131 XILINX_DP_TX_INTR_HPD_EVENT | \
132 XILINX_DP_TX_INTR_REPLY_RECV | \
133 XILINX_DP_TX_INTR_REPLY_TIMEOUT | \
134 XILINX_DP_TX_INTR_HPD_PULSE | \
135 XILINX_DP_TX_INTR_EXT_PKT_TXD | \
136 XILINX_DP_TX_INTR_LIV_ABUF_UNDRFLW | \
137 XILINX_DP_TX_INTR_VBLANK_START | \
138 XILINX_DP_TX_INTR_CHBUF_UNDERFLW_MASK | \
139 XILINX_DP_TX_INTR_CHBUF_OVERFLW_MASK)
140#define XILINX_DP_TX_REPLY_DATA_CNT 0x148
141#define XILINX_DP_SUB_TX_INTR_STATUS 0x3a0
142#define XILINX_DP_SUB_TX_INTR_MASK 0x3a4
143#define XILINX_DP_SUB_TX_INTR_EN 0x3a8
144#define XILINX_DP_SUB_TX_INTR_DS 0x3ac
145
146
147#define XILINX_DP_TX_MAIN_STREAM_HTOTAL 0x180
148#define XILINX_DP_TX_MAIN_STREAM_VTOTAL 0x184
149#define XILINX_DP_TX_MAIN_STREAM_POLARITY 0x188
150#define XILINX_DP_TX_MAIN_STREAM_POLARITY_HSYNC_SHIFT 0
151#define XILINX_DP_TX_MAIN_STREAM_POLARITY_VSYNC_SHIFT 1
152#define XILINX_DP_TX_MAIN_STREAM_HSWIDTH 0x18c
153#define XILINX_DP_TX_MAIN_STREAM_VSWIDTH 0x190
154#define XILINX_DP_TX_MAIN_STREAM_HRES 0x194
155#define XILINX_DP_TX_MAIN_STREAM_VRES 0x198
156#define XILINX_DP_TX_MAIN_STREAM_HSTART 0x19c
157#define XILINX_DP_TX_MAIN_STREAM_VSTART 0x1a0
158#define XILINX_DP_TX_MAIN_STREAM_MISC0 0x1a4
159#define XILINX_DP_TX_MAIN_STREAM_MISC0_SYNC (1 << 0)
160#define XILINX_DP_TX_MAIN_STREAM_MISC0_FORMAT_SHIFT 1
161#define XILINX_DP_TX_MAIN_STREAM_MISC0_DYNAMIC_RANGE (1 << 3)
162#define XILINX_DP_TX_MAIN_STREAM_MISC0_YCBCR_COLRIMETRY (1 << 4)
163#define XILINX_DP_TX_MAIN_STREAM_MISC0_BPC_SHIFT 5
164#define XILINX_DP_TX_MAIN_STREAM_MISC1 0x1a8
165#define XILINX_DP_TX_MAIN_STREAM_MISC0_INTERLACED_VERT (1 << 0)
166#define XILINX_DP_TX_MAIN_STREAM_MISC0_STEREO_VID_SHIFT 1
167#define XILINX_DP_TX_M_VID 0x1ac
168#define XILINX_DP_TX_TRANSFER_UNIT_SIZE 0x1b0
169#define XILINX_DP_TX_DEF_TRANSFER_UNIT_SIZE 64
170#define XILINX_DP_TX_N_VID 0x1b4
171#define XILINX_DP_TX_USER_PIXEL_WIDTH 0x1b8
172#define XILINX_DP_TX_USER_DATA_CNT_PER_LANE 0x1bc
173#define XILINX_DP_TX_MIN_BYTES_PER_TU 0x1c4
174#define XILINX_DP_TX_FRAC_BYTES_PER_TU 0x1c8
175#define XILINX_DP_TX_INIT_WAIT 0x1cc
176
177
178#define XILINX_DP_TX_PHY_CONFIG 0x200
179#define XILINX_DP_TX_PHY_CONFIG_PHY_RESET (1 << 0)
180#define XILINX_DP_TX_PHY_CONFIG_GTTX_RESET (1 << 1)
181#define XILINX_DP_TX_PHY_CONFIG_PHY_PMA_RESET (1 << 8)
182#define XILINX_DP_TX_PHY_CONFIG_PHY_PCS_RESET (1 << 9)
183#define XILINX_DP_TX_PHY_CONFIG_ALL_RESET (XILINX_DP_TX_PHY_CONFIG_PHY_RESET | \
184 XILINX_DP_TX_PHY_CONFIG_GTTX_RESET | \
185 XILINX_DP_TX_PHY_CONFIG_PHY_PMA_RESET | \
186 XILINX_DP_TX_PHY_CONFIG_PHY_PCS_RESET)
187#define XILINX_DP_TX_PHY_PREEMPHASIS_LANE_0 0x210
188#define XILINX_DP_TX_PHY_PREEMPHASIS_LANE_1 0x214
189#define XILINX_DP_TX_PHY_PREEMPHASIS_LANE_2 0x218
190#define XILINX_DP_TX_PHY_PREEMPHASIS_LANE_3 0x21c
191#define XILINX_DP_TX_PHY_VOLTAGE_DIFF_LANE_0 0x220
192#define XILINX_DP_TX_PHY_VOLTAGE_DIFF_LANE_1 0x224
193#define XILINX_DP_TX_PHY_VOLTAGE_DIFF_LANE_2 0x228
194#define XILINX_DP_TX_PHY_VOLTAGE_DIFF_LANE_3 0x22c
195#define XILINX_DP_TX_PHY_CLOCK_FEEDBACK_SETTING 0x234
196#define XILINX_DP_TX_PHY_CLOCK_FEEDBACK_SETTING_162 0x1
197#define XILINX_DP_TX_PHY_CLOCK_FEEDBACK_SETTING_270 0x3
198#define XILINX_DP_TX_PHY_CLOCK_FEEDBACK_SETTING_540 0x5
199#define XILINX_DP_TX_PHY_POWER_DOWN 0x238
200#define XILINX_DP_TX_PHY_POWER_DOWN_LANE_0 (1 << 0)
201#define XILINX_DP_TX_PHY_POWER_DOWN_LANE_1 (1 << 1)
202#define XILINX_DP_TX_PHY_POWER_DOWN_LANE_2 (1 << 2)
203#define XILINX_DP_TX_PHY_POWER_DOWN_LANE_3 (1 << 3)
204#define XILINX_DP_TX_PHY_POWER_DOWN_ALL 0xf
205#define XILINX_DP_TX_PHY_PRECURSOR_LANE_0 0x23c
206#define XILINX_DP_TX_PHY_PRECURSOR_LANE_1 0x240
207#define XILINX_DP_TX_PHY_PRECURSOR_LANE_2 0x244
208#define XILINX_DP_TX_PHY_PRECURSOR_LANE_3 0x248
209#define XILINX_DP_TX_PHY_POSTCURSOR_LANE_0 0x24c
210#define XILINX_DP_TX_PHY_POSTCURSOR_LANE_1 0x250
211#define XILINX_DP_TX_PHY_POSTCURSOR_LANE_2 0x254
212#define XILINX_DP_TX_PHY_POSTCURSOR_LANE_3 0x258
213#define XILINX_DP_SUB_TX_PHY_PRECURSOR_LANE_0 0x24c
214#define XILINX_DP_SUB_TX_PHY_PRECURSOR_LANE_1 0x250
215#define XILINX_DP_TX_PHY_STATUS 0x280
216#define XILINX_DP_TX_PHY_STATUS_PLL_LOCKED_SHIFT 4
217#define XILINX_DP_TX_PHY_STATUS_FPGA_PLL_LOCKED (1 << 6)
218
219
220#define XILINX_DP_TX_AUDIO_CONTROL 0x300
221#define XILINX_DP_TX_AUDIO_CHANNELS 0x304
222#define XILINX_DP_TX_AUDIO_INFO_DATA 0x308
223#define XILINX_DP_TX_AUDIO_M_AUD 0x328
224#define XILINX_DP_TX_AUDIO_N_AUD 0x32c
225#define XILINX_DP_TX_AUDIO_EXT_DATA 0x330
226
227#define XILINX_DP_MISC0_RGB (0)
228#define XILINX_DP_MISC0_YCRCB_422 (5 << 1)
229#define XILINX_DP_MISC0_YCRCB_444 (6 << 1)
230#define XILINX_DP_MISC0_BPC_6 (0 << 5)
231#define XILINX_DP_MISC0_BPC_8 (1 << 5)
232#define XILINX_DP_MISC0_BPC_10 (2 << 5)
233#define XILINX_DP_MISC0_BPC_12 (3 << 5)
234#define XILINX_DP_MISC0_BPC_16 (4 << 5)
235#define XILINX_DP_MISC1_Y_ONLY (1 << 7)
236
237#define DP_REDUCED_BIT_RATE 162000
238#define DP_HIGH_BIT_RATE 270000
239#define DP_HIGH_BIT_RATE2 540000
240#define DP_MAX_TRAINING_TRIES 5
241#define DP_MAX_LANES 4
242
243enum dp_version {
244 DP_V1_1A = 0x11,
245 DP_V1_2 = 0x12
246};
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253struct xilinx_drm_dp_link_config {
254 int max_rate;
255 u8 max_lanes;
256};
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264struct xilinx_drm_dp_mode {
265 u8 bw_code;
266 u8 lane_cnt;
267 int pclock;
268};
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283struct xilinx_drm_dp_config {
284 enum dp_version dp_version;
285 u32 max_lanes;
286 u32 max_link_rate;
287 u32 max_bpc;
288 u32 max_pclock;
289 bool enable_yonly;
290 bool enable_ycrcb;
291
292 u8 misc0;
293 u8 misc1;
294 u8 bpp;
295};
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315struct xilinx_drm_dp {
316 struct drm_encoder *encoder;
317 struct device *dev;
318 void __iomem *iomem;
319
320 struct xilinx_drm_dp_config config;
321 struct drm_dp_aux aux;
322 struct xilinx_drm_dp_sub *dp_sub;
323 struct phy *phy[DP_MAX_LANES];
324 struct clk *aclk;
325 struct clk *aud_clk;
326
327 int dpms;
328 u8 dpcd[DP_RECEIVER_CAP_SIZE];
329 struct xilinx_drm_dp_link_config link_config;
330 struct xilinx_drm_dp_mode mode;
331 u8 train_set[DP_MAX_LANES];
332 bool suspend;
333};
334
335static inline struct xilinx_drm_dp *to_dp(struct drm_encoder *encoder)
336{
337 return to_encoder_slave(encoder)->slave_priv;
338}
339
340#define AUX_READ_BIT 0x1
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364static int xilinx_drm_dp_aux_cmd_submit(struct xilinx_drm_dp *dp, u32 cmd,
365 u16 addr, u8 *buf, u8 bytes, u8 *reply)
366{
367 bool is_read = (cmd & AUX_READ_BIT) ? true : false;
368 void __iomem *iomem = dp->iomem;
369 u32 reg, i;
370
371 reg = xilinx_drm_readl(iomem, XILINX_DP_TX_INTR_SIGNAL_STATE);
372 if (reg & XILINX_DP_TX_INTR_SIGNAL_STATE_REQUEST)
373 return -EBUSY;
374
375 xilinx_drm_writel(iomem, XILINX_DP_TX_AUX_ADDRESS, addr);
376
377 if (!is_read)
378 for (i = 0; i < bytes; i++)
379 xilinx_drm_writel(iomem, XILINX_DP_TX_AUX_WRITE_FIFO,
380 buf[i]);
381
382 reg = cmd << XILINX_DP_TX_AUX_COMMAND_CMD_SHIFT;
383 if (!buf || !bytes)
384 reg |= XILINX_DP_TX_AUX_COMMAND_ADDRESS_ONLY;
385 else
386 reg |= (bytes - 1) << XILINX_DP_TX_AUX_COMMAND_BYTES_SHIFT;
387 xilinx_drm_writel(iomem, XILINX_DP_TX_AUX_COMMAND, reg);
388
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390 for (i = 0; ; i++) {
391 reg = xilinx_drm_readl(iomem, XILINX_DP_TX_INTR_SIGNAL_STATE);
392
393 if (reg & XILINX_DP_TX_INTR_SIGNAL_STATE_REPLY)
394 break;
395
396 if (reg & XILINX_DP_TX_INTR_SIGNAL_STATE_REPLY_TIMEOUT ||
397 i == 2)
398 return -ETIMEDOUT;
399
400 usleep_range(1000, 1100);
401 }
402
403 reg = xilinx_drm_readl(iomem, XILINX_DP_TX_AUX_REPLY_CODE);
404 if (reply)
405 *reply = reg;
406
407 if (is_read &&
408 (reg == XILINX_DP_TX_AUX_REPLY_CODE_AUX_ACK ||
409 reg == XILINX_DP_TX_AUX_REPLY_CODE_I2C_ACK)) {
410 reg = xilinx_drm_readl(iomem, XILINX_DP_TX_REPLY_DATA_CNT);
411 if ((reg & XILINX_DP_TX_AUX_REPLY_CNT_MASK) != bytes)
412 return -EIO;
413
414 for (i = 0; i < bytes; i++)
415 buf[i] = xilinx_drm_readl(iomem,
416 XILINX_DP_TX_AUX_REPLY_DATA);
417 }
418
419 return 0;
420}
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431static int xilinx_drm_dp_phy_ready(struct xilinx_drm_dp *dp)
432{
433 u32 i, reg, ready, lane;
434
435 lane = dp->config.max_lanes;
436 ready = (1 << lane) - 1;
437 if (!dp->dp_sub)
438 ready |= XILINX_DP_TX_PHY_STATUS_FPGA_PLL_LOCKED;
439
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441 for (i = 0; ; i++) {
442 reg = xilinx_drm_readl(dp->iomem, XILINX_DP_TX_PHY_STATUS);
443 if ((reg & ready) == ready)
444 return 0;
445
446 if (i == 100) {
447 DRM_ERROR("PHY isn't ready\n");
448 return -ENODEV;
449 }
450
451 usleep_range(1000, 1100);
452 }
453
454 return 0;
455}
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465static inline int xilinx_drm_dp_max_rate(int link_rate, u8 lane_num, u8 bpp)
466{
467 return link_rate * lane_num * 8 / bpp;
468}
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483static int xilinx_drm_dp_mode_configure(struct xilinx_drm_dp *dp, int pclock,
484 u8 current_bw)
485{
486 int max_rate = dp->link_config.max_rate;
487 u8 bws[3] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
488 u8 max_lanes = dp->link_config.max_lanes;
489 u8 max_link_rate_code = drm_dp_link_rate_to_bw_code(max_rate);
490 u8 bpp = dp->config.bpp;
491 u8 lane_cnt;
492 s8 clock, i;
493
494 for (i = ARRAY_SIZE(bws) - 1; i >= 0; i--) {
495 if (current_bw && bws[i] >= current_bw)
496 continue;
497
498 if (bws[i] <= max_link_rate_code)
499 break;
500 }
501
502 for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) {
503 for (clock = i; clock >= 0; clock--) {
504 int bw;
505 u32 rate;
506
507 bw = drm_dp_bw_code_to_link_rate(bws[clock]);
508 rate = xilinx_drm_dp_max_rate(bw, lane_cnt, bpp);
509 if (pclock <= rate) {
510 dp->mode.bw_code = bws[clock];
511 dp->mode.lane_cnt = lane_cnt;
512 dp->mode.pclock = pclock;
513 return bws[clock];
514 }
515 }
516 }
517
518 DRM_ERROR("failed to configure link values\n");
519
520 return -EINVAL;
521}
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528static void xilinx_drm_dp_adjust_train(struct xilinx_drm_dp *dp,
529 u8 link_status[DP_LINK_STATUS_SIZE])
530{
531 u8 *train_set = dp->train_set;
532 u8 voltage = 0, preemphasis = 0;
533 u8 max_preemphasis;
534 u8 i;
535
536 for (i = 0; i < dp->mode.lane_cnt; i++) {
537 u8 v = drm_dp_get_adjust_request_voltage(link_status, i);
538 u8 p = drm_dp_get_adjust_request_pre_emphasis(link_status, i);
539
540 if (v > voltage)
541 voltage = v;
542
543 if (p > preemphasis)
544 preemphasis = p;
545 }
546
547 if (voltage >= DP_TRAIN_VOLTAGE_SWING_LEVEL_3)
548 voltage |= DP_TRAIN_MAX_SWING_REACHED;
549
550 max_preemphasis = (dp->dp_sub) ? DP_TRAIN_PRE_EMPH_LEVEL_2 :
551 DP_TRAIN_PRE_EMPH_LEVEL_3;
552
553 if (preemphasis >= max_preemphasis)
554 preemphasis |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
555
556 for (i = 0; i < dp->mode.lane_cnt; i++)
557 train_set[i] = voltage | preemphasis;
558}
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570static int xilinx_drm_dp_update_vs_emph(struct xilinx_drm_dp *dp)
571{
572 u8 *train_set = dp->train_set;
573 u8 i, v_level, p_level;
574 int ret;
575 static u8 vs[4][4] = { { 0x2a, 0x27, 0x24, 0x20 },
576 { 0x27, 0x23, 0x20, 0xff },
577 { 0x24, 0x20, 0xff, 0xff },
578 { 0xff, 0xff, 0xff, 0xff } };
579 static u8 pe[4][4] = { { 0x2, 0x2, 0x2, 0x2 },
580 { 0x1, 0x1, 0x1, 0xff },
581 { 0x0, 0x0, 0xff, 0xff },
582 { 0xff, 0xff, 0xff, 0xff } };
583
584 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, train_set,
585 dp->mode.lane_cnt);
586 if (ret < 0)
587 return ret;
588
589 for (i = 0; i < dp->mode.lane_cnt; i++) {
590 v_level = (train_set[i] & DP_TRAIN_VOLTAGE_SWING_MASK) >>
591 DP_TRAIN_VOLTAGE_SWING_SHIFT;
592 p_level = (train_set[i] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
593 DP_TRAIN_PRE_EMPHASIS_SHIFT;
594
595 if (dp->phy[i]) {
596 u32 reg = XILINX_DP_SUB_TX_PHY_PRECURSOR_LANE_0 + i * 4;
597
598 xpsgtr_margining_factor(dp->phy[i], p_level, v_level);
599 xpsgtr_override_deemph(dp->phy[i], p_level, v_level);
600 xilinx_drm_writel(dp->iomem, reg, 0x2);
601 } else {
602 u32 reg;
603
604 reg = XILINX_DP_TX_PHY_VOLTAGE_DIFF_LANE_0 + i + 4;
605 xilinx_drm_writel(dp->iomem, reg, vs[p_level][v_level]);
606 reg = XILINX_DP_TX_PHY_PRECURSOR_LANE_0 + i + 4;
607 xilinx_drm_writel(dp->iomem, reg, pe[p_level][v_level]);
608 reg = XILINX_DP_TX_PHY_POSTCURSOR_LANE_0 + i + 4;
609 xilinx_drm_writel(dp->iomem, reg, 0);
610 }
611 }
612
613 return 0;
614}
615
616
617
618
619
620
621
622
623static int xilinx_drm_dp_link_train_cr(struct xilinx_drm_dp *dp)
624{
625 u8 link_status[DP_LINK_STATUS_SIZE];
626 u8 lane_cnt = dp->mode.lane_cnt;
627 u8 vs = 0, tries = 0;
628 u16 max_tries, i;
629 bool cr_done;
630 int ret;
631
632 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
633 DP_TRAINING_PATTERN_1 |
634 DP_LINK_SCRAMBLING_DISABLE);
635 if (ret < 0)
636 return ret;
637
638 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_TRAINING_PATTERN_SET,
639 DP_TRAINING_PATTERN_1);
640
641
642
643 for (max_tries = 0; max_tries < 512; max_tries++) {
644 ret = xilinx_drm_dp_update_vs_emph(dp);
645 if (ret)
646 return ret;
647
648 drm_dp_link_train_clock_recovery_delay(dp->dpcd);
649
650 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status);
651 if (ret < 0)
652 return ret;
653
654 cr_done = drm_dp_clock_recovery_ok(link_status, lane_cnt);
655 if (cr_done)
656 break;
657
658 for (i = 0; i < lane_cnt; i++)
659 if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED))
660 break;
661
662 if (i == lane_cnt)
663 break;
664
665 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs)
666 tries++;
667 else
668 tries = 0;
669
670 if (tries == DP_MAX_TRAINING_TRIES)
671 break;
672
673 vs = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
674
675 xilinx_drm_dp_adjust_train(dp, link_status);
676 }
677
678 if (!cr_done)
679 return -EIO;
680
681 return 0;
682}
683
684
685
686
687
688
689
690
691static int xilinx_drm_dp_link_train_ce(struct xilinx_drm_dp *dp)
692{
693 u8 link_status[DP_LINK_STATUS_SIZE];
694 u8 lane_cnt = dp->mode.lane_cnt;
695 u32 pat, tries;
696 int ret;
697 bool ce_done;
698
699 if (dp->config.dp_version == DP_V1_2 &&
700 dp->dpcd[DP_DPCD_REV] >= DP_V1_2 &&
701 dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED)
702 pat = DP_TRAINING_PATTERN_3;
703 else
704 pat = DP_TRAINING_PATTERN_2;
705
706 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
707 pat | DP_LINK_SCRAMBLING_DISABLE);
708 if (ret < 0)
709 return ret;
710
711 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_TRAINING_PATTERN_SET, pat);
712
713 for (tries = 0; tries < DP_MAX_TRAINING_TRIES; tries++) {
714 ret = xilinx_drm_dp_update_vs_emph(dp);
715 if (ret)
716 return ret;
717
718 drm_dp_link_train_channel_eq_delay(dp->dpcd);
719
720 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status);
721 if (ret < 0)
722 return ret;
723
724 ce_done = drm_dp_channel_eq_ok(link_status, lane_cnt);
725 if (ce_done)
726 break;
727
728 xilinx_drm_dp_adjust_train(dp, link_status);
729 }
730
731 if (!ce_done)
732 return -EIO;
733
734 return 0;
735}
736
737
738
739
740
741
742
743static int xilinx_drm_dp_train(struct xilinx_drm_dp *dp)
744{
745 u32 reg;
746 u8 bw_code = dp->mode.bw_code;
747 u8 lane_cnt = dp->mode.lane_cnt;
748 u8 aux_lane_cnt = lane_cnt;
749 bool enhanced;
750 int ret;
751
752 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_LANE_CNT_SET, lane_cnt);
753
754 enhanced = drm_dp_enhanced_frame_cap(dp->dpcd);
755 if (enhanced) {
756 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_ENHANCED_FRAME_EN, 1);
757 aux_lane_cnt |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
758 }
759
760 if (dp->dpcd[3] & 0x1) {
761 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_DOWNSPREAD_CTL, 1);
762 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL,
763 DP_SPREAD_AMP_0_5);
764 } else {
765 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_DOWNSPREAD_CTL, 0);
766 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, 0);
767 }
768
769 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, aux_lane_cnt);
770 if (ret < 0) {
771 DRM_ERROR("failed to set lane count\n");
772 return ret;
773 }
774
775 ret = drm_dp_dpcd_writeb(&dp->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
776 DP_SET_ANSI_8B10B);
777 if (ret < 0) {
778 DRM_ERROR("failed to set ANSI 8B/10B encoding\n");
779 return ret;
780 }
781
782 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LINK_BW_SET, bw_code);
783 if (ret < 0) {
784 DRM_ERROR("failed to set DP bandwidth\n");
785 return ret;
786 }
787
788 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_LINK_BW_SET, bw_code);
789
790 switch (bw_code) {
791 case DP_LINK_BW_1_62:
792 reg = XILINX_DP_TX_PHY_CLOCK_FEEDBACK_SETTING_162;
793 break;
794 case DP_LINK_BW_2_7:
795 reg = XILINX_DP_TX_PHY_CLOCK_FEEDBACK_SETTING_270;
796 break;
797 case DP_LINK_BW_5_4:
798 default:
799 reg = XILINX_DP_TX_PHY_CLOCK_FEEDBACK_SETTING_540;
800 break;
801 }
802
803 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_PHY_CLOCK_FEEDBACK_SETTING,
804 reg);
805 ret = xilinx_drm_dp_phy_ready(dp);
806 if (ret < 0)
807 return ret;
808
809 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_SCRAMBLING_DISABLE, 1);
810
811 memset(dp->train_set, 0, 4);
812
813 ret = xilinx_drm_dp_link_train_cr(dp);
814 if (ret)
815 return ret;
816
817 ret = xilinx_drm_dp_link_train_ce(dp);
818 if (ret)
819 return ret;
820
821 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_TRAINING_PATTERN_SET,
822 DP_TRAINING_PATTERN_DISABLE);
823 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
824 DP_TRAINING_PATTERN_DISABLE);
825 if (ret < 0) {
826 DRM_ERROR("failed to disable training pattern\n");
827 return ret;
828 }
829
830 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_SCRAMBLING_DISABLE, 0);
831
832 return 0;
833}
834
835
836
837
838
839
840
841static void xilinx_drm_dp_train_loop(struct xilinx_drm_dp *dp)
842{
843 struct xilinx_drm_dp_mode *mode = &dp->mode;
844 u8 bw = mode->bw_code;
845 int ret;
846
847 do {
848 ret = xilinx_drm_dp_train(dp);
849 if (!ret)
850 return;
851
852 ret = xilinx_drm_dp_mode_configure(dp, mode->pclock, bw);
853 if (ret < 0)
854 return;
855 bw = ret;
856 } while (bw >= DP_LINK_BW_1_62);
857
858 DRM_ERROR("failed to train the DP link\n");
859}
860
861
862
863
864
865
866
867
868
869
870
871static int xilinx_drm_dp_init_aux(struct xilinx_drm_dp *dp)
872{
873 int clock_rate;
874 u32 reg, w;
875
876 clock_rate = clk_get_rate(dp->aclk);
877 if (clock_rate < XILINX_DP_TX_CLK_DIVIDER_MHZ) {
878 DRM_ERROR("aclk should be higher than 1MHz\n");
879 return -EINVAL;
880 }
881
882
883 for (w = 8; w <= 48; w += 8) {
884
885 if (w >= (4 * clock_rate / 10000000) &&
886 w <= (6 * clock_rate / 10000000))
887 break;
888 }
889
890 if (w > 48) {
891 DRM_ERROR("aclk frequency too high\n");
892 return -EINVAL;
893 }
894 reg = w << XILINX_DP_TX_CLK_DIVIDER_AUX_FILTER_SHIFT;
895
896 reg |= clock_rate / XILINX_DP_TX_CLK_DIVIDER_MHZ;
897 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_CLK_DIVIDER, reg);
898
899 if (dp->dp_sub)
900 xilinx_drm_writel(dp->iomem, XILINX_DP_SUB_TX_INTR_EN,
901 XILINX_DP_TX_INTR_ALL);
902 else
903 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_INTR_MASK,
904 ~XILINX_DP_TX_INTR_ALL);
905 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_ENABLE, 1);
906
907 return 0;
908}
909
910
911
912
913
914
915
916
917
918
919static int xilinx_drm_dp_init_phy(struct xilinx_drm_dp *dp)
920{
921 unsigned int i;
922 int ret;
923
924 for (i = 0; i < dp->config.max_lanes; i++) {
925 ret = phy_init(dp->phy[i]);
926 if (ret) {
927 dev_err(dp->dev, "failed to init phy lane %d\n", i);
928 return ret;
929 }
930 }
931
932 if (dp->dp_sub)
933 xilinx_drm_writel(dp->iomem, XILINX_DP_SUB_TX_INTR_DS,
934 XILINX_DP_TX_INTR_ALL);
935 else
936 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_INTR_MASK,
937 XILINX_DP_TX_INTR_ALL);
938
939 xilinx_drm_clr(dp->iomem, XILINX_DP_TX_PHY_CONFIG,
940 XILINX_DP_TX_PHY_CONFIG_ALL_RESET);
941
942
943 if (dp->phy[0]) {
944 ret = xpsgtr_wait_pll_lock(dp->phy[0]);
945 if (ret) {
946 dev_err(dp->dev, "failed to lock pll\n");
947 return ret;
948 }
949 }
950
951 return 0;
952}
953
954
955
956
957
958
959
960static void xilinx_drm_dp_exit_phy(struct xilinx_drm_dp *dp)
961{
962 unsigned int i;
963 int ret;
964
965 for (i = 0; i < dp->config.max_lanes; i++) {
966 ret = phy_exit(dp->phy[i]);
967 if (ret) {
968 dev_err(dp->dev,
969 "failed to exit phy (%d) %d\n", i, ret);
970 }
971 }
972}
973
974static void xilinx_drm_dp_dpms(struct drm_encoder *encoder, int dpms)
975{
976 struct xilinx_drm_dp *dp = to_dp(encoder);
977 void __iomem *iomem = dp->iomem;
978 unsigned int i;
979 int ret;
980
981 if (dp->dpms == dpms)
982 return;
983
984 dp->dpms = dpms;
985
986 switch (dpms) {
987 case DRM_MODE_DPMS_ON:
988 pm_runtime_get_sync(dp->dev);
989
990 if (dp->suspend) {
991 xilinx_drm_dp_init_phy(dp);
992 xilinx_drm_dp_init_aux(dp);
993 dp->suspend = false;
994 }
995
996 if (dp->aud_clk)
997 xilinx_drm_writel(iomem, XILINX_DP_TX_AUDIO_CONTROL, 1);
998 xilinx_drm_writel(iomem, XILINX_DP_TX_PHY_POWER_DOWN, 0);
999
1000 for (i = 0; i < 3; i++) {
1001 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER,
1002 DP_SET_POWER_D0);
1003 if (ret == 1)
1004 break;
1005 usleep_range(300, 500);
1006 }
1007 xilinx_drm_dp_train_loop(dp);
1008 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_SW_RESET,
1009 XILINX_DP_TX_SW_RESET_ALL);
1010 xilinx_drm_writel(iomem, XILINX_DP_TX_ENABLE_MAIN_STREAM, 1);
1011
1012 return;
1013 case DRM_MODE_DPMS_SUSPEND:
1014 dp->suspend = true;
1015 xilinx_drm_dp_exit_phy(dp);
1016 default:
1017 xilinx_drm_writel(iomem, XILINX_DP_TX_ENABLE_MAIN_STREAM, 0);
1018 drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D3);
1019 xilinx_drm_writel(iomem, XILINX_DP_TX_PHY_POWER_DOWN,
1020 XILINX_DP_TX_PHY_POWER_DOWN_ALL);
1021 if (dp->aud_clk)
1022 xilinx_drm_writel(iomem, XILINX_DP_TX_AUDIO_CONTROL, 0);
1023
1024 pm_runtime_put_sync(dp->dev);
1025
1026 return;
1027 }
1028}
1029
1030static void xilinx_drm_dp_save(struct drm_encoder *encoder)
1031{
1032
1033}
1034
1035static void xilinx_drm_dp_restore(struct drm_encoder *encoder)
1036{
1037
1038}
1039
1040#define XILINX_DP_SUB_TX_MIN_H_BACKPORCH 20
1041
1042static bool xilinx_drm_dp_mode_fixup(struct drm_encoder *encoder,
1043 const struct drm_display_mode *mode,
1044 struct drm_display_mode *adjusted_mode)
1045{
1046 struct xilinx_drm_dp *dp = to_dp(encoder);
1047 int diff = mode->htotal - mode->hsync_end;
1048
1049
1050
1051
1052
1053 if (dp->dp_sub && diff < XILINX_DP_SUB_TX_MIN_H_BACKPORCH) {
1054 int vrefresh = (adjusted_mode->clock * 1000) /
1055 (adjusted_mode->vtotal * adjusted_mode->htotal);
1056
1057 diff = XILINX_DP_SUB_TX_MIN_H_BACKPORCH - diff;
1058 adjusted_mode->htotal += diff;
1059 adjusted_mode->clock = adjusted_mode->vtotal *
1060 adjusted_mode->htotal * vrefresh / 1000;
1061 }
1062
1063 return true;
1064}
1065
1066static int xilinx_drm_dp_mode_valid(struct drm_encoder *encoder,
1067 struct drm_display_mode *mode)
1068{
1069 struct xilinx_drm_dp *dp = to_dp(encoder);
1070 u8 max_lanes = dp->link_config.max_lanes;
1071 u8 bpp = dp->config.bpp;
1072 u32 max_pclock = dp->config.max_pclock;
1073 int max_rate = dp->link_config.max_rate;
1074 int rate;
1075
1076 if (max_pclock && mode->clock > max_pclock)
1077 return MODE_CLOCK_HIGH;
1078
1079 rate = xilinx_drm_dp_max_rate(max_rate, max_lanes, bpp);
1080 if (mode->clock > rate)
1081 return MODE_CLOCK_HIGH;
1082
1083 return MODE_OK;
1084}
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094static void xilinx_drm_dp_mode_set_transfer_unit(struct xilinx_drm_dp *dp,
1095 struct drm_display_mode *mode)
1096{
1097 u32 tu = XILINX_DP_TX_DEF_TRANSFER_UNIT_SIZE;
1098 u32 bw, vid_kbytes, avg_bytes_per_tu, init_wait;
1099
1100
1101 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_TRANSFER_UNIT_SIZE, tu);
1102
1103 vid_kbytes = mode->clock * (dp->config.bpp / 8);
1104 bw = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
1105 avg_bytes_per_tu = vid_kbytes * tu / (dp->mode.lane_cnt * bw / 1000);
1106
1107 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MIN_BYTES_PER_TU,
1108 avg_bytes_per_tu / 1000);
1109 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_FRAC_BYTES_PER_TU,
1110 avg_bytes_per_tu % 1000);
1111
1112
1113 if (tu < (avg_bytes_per_tu / 1000))
1114 init_wait = 0;
1115 else if ((avg_bytes_per_tu / 1000) <= 4)
1116 init_wait = tu;
1117 else
1118 init_wait = tu - avg_bytes_per_tu / 1000;
1119
1120 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_INIT_WAIT, init_wait);
1121}
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131static void xilinx_drm_dp_mode_set_stream(struct xilinx_drm_dp *dp,
1132 struct drm_display_mode *mode)
1133{
1134 u8 lane_cnt = dp->mode.lane_cnt;
1135 u32 reg, wpl;
1136
1137 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_HTOTAL,
1138 mode->htotal);
1139 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_VTOTAL,
1140 mode->vtotal);
1141
1142 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_POLARITY,
1143 (!!(mode->flags & DRM_MODE_FLAG_PVSYNC) <<
1144 XILINX_DP_TX_MAIN_STREAM_POLARITY_VSYNC_SHIFT) |
1145 (!!(mode->flags & DRM_MODE_FLAG_PHSYNC) <<
1146 XILINX_DP_TX_MAIN_STREAM_POLARITY_HSYNC_SHIFT));
1147
1148 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_HSWIDTH,
1149 mode->hsync_end - mode->hsync_start);
1150 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_VSWIDTH,
1151 mode->vsync_end - mode->vsync_start);
1152
1153 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_HRES,
1154 mode->hdisplay);
1155 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_VRES,
1156 mode->vdisplay);
1157
1158 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_HSTART,
1159 mode->htotal - mode->hsync_start);
1160 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_VSTART,
1161 mode->vtotal - mode->vsync_start);
1162
1163 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_MISC0,
1164 dp->config.misc0);
1165 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_MAIN_STREAM_MISC1,
1166 dp->config.misc1);
1167
1168
1169 if (dp->config.misc0 & XILINX_DP_TX_MAIN_STREAM_MISC0_SYNC) {
1170 reg = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
1171 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_N_VID, reg);
1172 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_M_VID, mode->clock);
1173 if (dp->aud_clk) {
1174 int aud_rate = clk_get_rate(dp->aud_clk) / 512;
1175
1176 if (aud_rate != 44100 && aud_rate != 48000)
1177 dev_dbg(dp->dev, "Audio rate: %d\n", aud_rate);
1178
1179 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_AUDIO_N_AUD,
1180 reg);
1181 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_AUDIO_M_AUD,
1182 aud_rate);
1183 }
1184 }
1185
1186
1187 if (dp->aud_clk)
1188 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_AUDIO_CHANNELS, 1);
1189
1190 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_USER_PIXEL_WIDTH, 1);
1191
1192
1193 wpl = (mode->hdisplay * dp->config.bpp + 15) / 16;
1194 reg = wpl + wpl % lane_cnt - lane_cnt;
1195 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_USER_DATA_CNT_PER_LANE, reg);
1196}
1197
1198
1199static void xilinx_drm_dp_mode_set(struct drm_encoder *encoder,
1200 struct drm_display_mode *mode,
1201 struct drm_display_mode *adjusted_mode)
1202{
1203 struct xilinx_drm_dp *dp = to_dp(encoder);
1204 int ret;
1205
1206 ret = xilinx_drm_dp_mode_configure(dp, adjusted_mode->clock, 0);
1207 if (ret < 0)
1208 return;
1209
1210 xilinx_drm_dp_mode_set_stream(dp, adjusted_mode);
1211 xilinx_drm_dp_mode_set_transfer_unit(dp, adjusted_mode);
1212}
1213
1214static enum drm_connector_status
1215xilinx_drm_dp_detect(struct drm_encoder *encoder,
1216 struct drm_connector *connector)
1217{
1218 struct xilinx_drm_dp *dp = to_dp(encoder);
1219 struct xilinx_drm_dp_link_config *link_config = &dp->link_config;
1220 u32 state;
1221 int ret;
1222
1223 state = xilinx_drm_readl(dp->iomem, XILINX_DP_TX_INTR_SIGNAL_STATE);
1224 if (state & XILINX_DP_TX_INTR_SIGNAL_STATE_HPD) {
1225 ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd,
1226 sizeof(dp->dpcd));
1227 if (ret < 0)
1228 return connector_status_disconnected;
1229
1230 link_config->max_rate = min_t(int,
1231 drm_dp_max_link_rate(dp->dpcd),
1232 dp->config.max_link_rate);
1233 link_config->max_lanes = min_t(u8,
1234 drm_dp_max_lane_count(dp->dpcd),
1235 dp->config.max_lanes);
1236
1237 return connector_status_connected;
1238 }
1239
1240 return connector_status_disconnected;
1241}
1242
1243static int xilinx_drm_dp_get_modes(struct drm_encoder *encoder,
1244 struct drm_connector *connector)
1245{
1246 struct xilinx_drm_dp *dp = to_dp(encoder);
1247 struct edid *edid;
1248 int ret;
1249
1250 edid = drm_get_edid(connector, &dp->aux.ddc);
1251 if (!edid)
1252 return 0;
1253
1254 drm_mode_connector_update_edid_property(connector, edid);
1255 ret = drm_add_edid_modes(connector, edid);
1256
1257 kfree(edid);
1258
1259 return ret;
1260}
1261
1262static struct drm_encoder_slave_funcs xilinx_drm_dp_encoder_funcs = {
1263 .dpms = xilinx_drm_dp_dpms,
1264 .save = xilinx_drm_dp_save,
1265 .restore = xilinx_drm_dp_restore,
1266 .mode_fixup = xilinx_drm_dp_mode_fixup,
1267 .mode_valid = xilinx_drm_dp_mode_valid,
1268 .mode_set = xilinx_drm_dp_mode_set,
1269 .detect = xilinx_drm_dp_detect,
1270 .get_modes = xilinx_drm_dp_get_modes,
1271};
1272
1273static int xilinx_drm_dp_encoder_init(struct platform_device *pdev,
1274 struct drm_device *dev,
1275 struct drm_encoder_slave *encoder)
1276{
1277 struct xilinx_drm_dp *dp = platform_get_drvdata(pdev);
1278
1279 encoder->slave_priv = dp;
1280 encoder->slave_funcs = &xilinx_drm_dp_encoder_funcs;
1281
1282 dp->encoder = &encoder->base;
1283
1284 return xilinx_drm_dp_init_aux(dp);
1285}
1286
1287static irqreturn_t xilinx_drm_dp_irq_handler(int irq, void *data)
1288{
1289 struct xilinx_drm_dp *dp = (struct xilinx_drm_dp *)data;
1290 u32 reg, status;
1291
1292 reg = dp->dp_sub ?
1293 XILINX_DP_SUB_TX_INTR_STATUS : XILINX_DP_TX_INTR_STATUS;
1294 status = xilinx_drm_readl(dp->iomem, reg);
1295 if (!status)
1296 return IRQ_NONE;
1297
1298 if (status & XILINX_DP_TX_INTR_CHBUF_UNDERFLW_MASK)
1299 dev_dbg(dp->dev, "underflow interrupt\n");
1300 if (status & XILINX_DP_TX_INTR_CHBUF_OVERFLW_MASK)
1301 dev_dbg(dp->dev, "overflow interrupt\n");
1302
1303 xilinx_drm_writel(dp->iomem, reg, status);
1304
1305 if (status & XILINX_DP_TX_INTR_VBLANK_START)
1306 xilinx_drm_dp_sub_handle_vblank(dp->dp_sub);
1307
1308 if (status & XILINX_DP_TX_INTR_HPD_EVENT)
1309 drm_helper_hpd_irq_event(dp->encoder->dev);
1310
1311 if (status & XILINX_DP_TX_INTR_HPD_IRQ) {
1312 u8 status[DP_LINK_STATUS_SIZE + 2];
1313
1314 drm_dp_dpcd_read(&dp->aux, DP_SINK_COUNT, status,
1315 DP_LINK_STATUS_SIZE + 2);
1316
1317 if (status[4] & DP_LINK_STATUS_UPDATED ||
1318 !drm_dp_clock_recovery_ok(&status[2], dp->mode.lane_cnt) ||
1319 !drm_dp_channel_eq_ok(&status[2], dp->mode.lane_cnt))
1320 xilinx_drm_dp_train_loop(dp);
1321 }
1322
1323 return IRQ_HANDLED;
1324}
1325
1326static ssize_t
1327xilinx_drm_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1328{
1329 struct xilinx_drm_dp *dp = container_of(aux, struct xilinx_drm_dp, aux);
1330 int ret;
1331 unsigned int i, iter;
1332
1333
1334 iter = xilinx_drm_dp_aux_timeout_ms * 1000 / 400;
1335 iter = iter ? iter : 1;
1336
1337 for (i = 0; i < iter; i++) {
1338 ret = xilinx_drm_dp_aux_cmd_submit(dp, msg->request,
1339 msg->address, msg->buffer,
1340 msg->size, &msg->reply);
1341 if (!ret) {
1342 dev_dbg(dp->dev, "aux %d retries\n", i);
1343 return msg->size;
1344 }
1345
1346 usleep_range(400, 500);
1347 }
1348
1349 dev_dbg(dp->dev, "failed to do aux transfer (%d)\n", ret);
1350
1351 return ret;
1352}
1353
1354static int xilinx_drm_dp_parse_of(struct xilinx_drm_dp *dp)
1355{
1356 struct device_node *node = dp->dev->of_node;
1357 struct xilinx_drm_dp_config *config = &dp->config;
1358 const char *string;
1359 u32 num_colors, bpc;
1360 bool sync;
1361 int ret;
1362
1363 ret = of_property_read_string(node, "xlnx,dp-version", &string);
1364 if (ret < 0) {
1365 dev_err(dp->dev, "No DP version in DT\n");
1366 return ret;
1367 }
1368
1369 if (strcmp(string, "v1.1a") == 0) {
1370 config->dp_version = DP_V1_1A;
1371 } else if (strcmp(string, "v1.2") == 0) {
1372 config->dp_version = DP_V1_2;
1373 } else {
1374 dev_err(dp->dev, "Invalid DP version in DT\n");
1375 return -EINVAL;
1376 }
1377
1378 ret = of_property_read_u32(node, "xlnx,max-lanes", &config->max_lanes);
1379 if (ret < 0) {
1380 dev_err(dp->dev, "No lane count in DT\n");
1381 return ret;
1382 }
1383
1384 if (config->max_lanes != 1 && config->max_lanes != 2 &&
1385 config->max_lanes != 4) {
1386 dev_err(dp->dev, "Invalid max lanes in DT\n");
1387 return -EINVAL;
1388 }
1389
1390 ret = of_property_read_u32(node, "xlnx,max-link-rate",
1391 &config->max_link_rate);
1392 if (ret < 0) {
1393 dev_err(dp->dev, "No link rate in DT\n");
1394 return ret;
1395 }
1396
1397 if (config->max_link_rate != DP_REDUCED_BIT_RATE &&
1398 config->max_link_rate != DP_HIGH_BIT_RATE &&
1399 config->max_link_rate != DP_HIGH_BIT_RATE2) {
1400 dev_err(dp->dev, "Invalid link rate in DT\n");
1401 return -EINVAL;
1402 }
1403
1404 config->enable_yonly = of_property_read_bool(node, "xlnx,enable-yonly");
1405 config->enable_ycrcb = of_property_read_bool(node, "xlnx,enable-ycrcb");
1406
1407 sync = of_property_read_bool(node, "xlnx,sync");
1408 if (sync)
1409 config->misc0 |= XILINX_DP_TX_MAIN_STREAM_MISC0_SYNC;
1410
1411 ret = of_property_read_string(node, "xlnx,colormetry", &string);
1412 if (ret < 0) {
1413 dev_err(dp->dev, "No colormetry in DT\n");
1414 return ret;
1415 }
1416
1417 if (strcmp(string, "rgb") == 0) {
1418 config->misc0 |= XILINX_DP_MISC0_RGB;
1419 num_colors = 3;
1420 } else if (config->enable_ycrcb && strcmp(string, "ycrcb422") == 0) {
1421 config->misc0 |= XILINX_DP_MISC0_YCRCB_422;
1422 num_colors = 2;
1423 } else if (config->enable_ycrcb && strcmp(string, "ycrcb444") == 0) {
1424 config->misc0 |= XILINX_DP_MISC0_YCRCB_444;
1425 num_colors = 3;
1426 } else if (config->enable_yonly && strcmp(string, "yonly") == 0) {
1427 config->misc1 |= XILINX_DP_MISC1_Y_ONLY;
1428 num_colors = 1;
1429 } else {
1430 dev_err(dp->dev, "Invalid colormetry in DT\n");
1431 return -EINVAL;
1432 }
1433
1434 ret = of_property_read_u32(node, "xlnx,max-bpc", &config->max_bpc);
1435 if (ret < 0) {
1436 dev_err(dp->dev, "No max bpc in DT\n");
1437 return ret;
1438 }
1439
1440 if (config->max_bpc != 8 && config->max_bpc != 10 &&
1441 config->max_bpc != 12 && config->max_bpc != 16) {
1442 dev_err(dp->dev, "Invalid max bpc in DT\n");
1443 return -EINVAL;
1444 }
1445
1446 ret = of_property_read_u32(node, "xlnx,bpc", &bpc);
1447 if (ret < 0) {
1448 dev_err(dp->dev, "No color depth(bpc) in DT\n");
1449 return ret;
1450 }
1451
1452 if (bpc > config->max_bpc) {
1453 dev_err(dp->dev, "Invalid color depth(bpc) in DT\n");
1454 return -EINVAL;
1455 }
1456
1457 switch (bpc) {
1458 case 6:
1459 config->misc0 |= XILINX_DP_MISC0_BPC_6;
1460 break;
1461 case 8:
1462 config->misc0 |= XILINX_DP_MISC0_BPC_8;
1463 break;
1464 case 10:
1465 config->misc0 |= XILINX_DP_MISC0_BPC_10;
1466 break;
1467 case 12:
1468 config->misc0 |= XILINX_DP_MISC0_BPC_12;
1469 break;
1470 case 16:
1471 config->misc0 |= XILINX_DP_MISC0_BPC_16;
1472 break;
1473 default:
1474 dev_err(dp->dev, "Not supported color depth in DT\n");
1475 return -EINVAL;
1476 }
1477
1478 config->bpp = num_colors * bpc;
1479
1480 of_property_read_u32(node, "xlnx,max-pclock-frequency",
1481 &config->max_pclock);
1482
1483 return 0;
1484}
1485
1486static int xilinx_drm_dp_probe(struct platform_device *pdev)
1487{
1488 struct xilinx_drm_dp *dp;
1489 struct resource *res;
1490 u32 version, i;
1491 int irq, ret;
1492
1493 dp = devm_kzalloc(&pdev->dev, sizeof(*dp), GFP_KERNEL);
1494 if (!dp)
1495 return -ENOMEM;
1496
1497 dp->dpms = DRM_MODE_DPMS_OFF;
1498 dp->dev = &pdev->dev;
1499
1500 ret = xilinx_drm_dp_parse_of(dp);
1501 if (ret < 0)
1502 return ret;
1503
1504 dp->aclk = devm_clk_get(dp->dev, "aclk");
1505 if (IS_ERR(dp->aclk))
1506 return PTR_ERR(dp->aclk);
1507
1508 ret = clk_prepare_enable(dp->aclk);
1509 if (ret) {
1510 dev_err(dp->dev, "failed to enable the aclk\n");
1511 return ret;
1512 }
1513
1514 dp->aud_clk = devm_clk_get(dp->dev, "aud_clk");
1515 if (IS_ERR(dp->aud_clk)) {
1516 ret = PTR_ERR(dp->aud_clk);
1517 if (ret == -EPROBE_DEFER)
1518 goto error_aclk;
1519 dp->aud_clk = NULL;
1520 dev_dbg(dp->dev, "failed to get the aud_clk:\n");
1521 } else {
1522 ret = clk_prepare_enable(dp->aud_clk);
1523 if (ret) {
1524 dev_err(dp->dev, "failed to enable aud_clk\n");
1525 goto error_aclk;
1526 }
1527 }
1528
1529 dp->dp_sub = xilinx_drm_dp_sub_of_get(pdev->dev.of_node);
1530 if (IS_ERR(dp->dp_sub)) {
1531 ret = PTR_ERR(dp->dp_sub);
1532 goto error_aud_clk;
1533 }
1534
1535 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1536 dp->iomem = devm_ioremap_resource(dp->dev, res);
1537 if (IS_ERR(dp->iomem)) {
1538 ret = PTR_ERR(dp->iomem);
1539 goto error_dp_sub;
1540 }
1541
1542 platform_set_drvdata(pdev, dp);
1543
1544 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_PHY_POWER_DOWN,
1545 XILINX_DP_TX_PHY_POWER_DOWN_ALL);
1546 xilinx_drm_set(dp->iomem, XILINX_DP_TX_PHY_CONFIG,
1547 XILINX_DP_TX_PHY_CONFIG_ALL_RESET);
1548 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_FORCE_SCRAMBLER_RESET, 1);
1549 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_ENABLE, 0);
1550
1551 if (dp->dp_sub) {
1552 for (i = 0; i < dp->config.max_lanes; i++) {
1553 char phy_name[16];
1554
1555 snprintf(phy_name, sizeof(phy_name), "dp-phy%d", i);
1556 dp->phy[i] = devm_phy_get(dp->dev, phy_name);
1557 if (IS_ERR(dp->phy[i])) {
1558 dev_err(dp->dev, "failed to get phy lane\n");
1559 ret = PTR_ERR(dp->phy[i]);
1560 dp->phy[i] = NULL;
1561 goto error_dp_sub;
1562 }
1563 }
1564 }
1565
1566 ret = xilinx_drm_dp_init_phy(dp);
1567 if (ret)
1568 goto error_phy;
1569
1570 dp->aux.name = "Xilinx DP AUX";
1571 dp->aux.dev = dp->dev;
1572 dp->aux.transfer = xilinx_drm_dp_aux_transfer;
1573 ret = drm_dp_aux_register(&dp->aux);
1574 if (ret < 0) {
1575 dev_err(dp->dev, "failed to initialize DP aux\n");
1576 goto error;
1577 }
1578
1579 irq = platform_get_irq(pdev, 0);
1580 if (irq < 0) {
1581 ret = irq;
1582 goto error;
1583 }
1584
1585 ret = devm_request_threaded_irq(dp->dev, irq, NULL,
1586 xilinx_drm_dp_irq_handler, IRQF_ONESHOT,
1587 dev_name(dp->dev), dp);
1588 if (ret < 0)
1589 goto error;
1590
1591 version = xilinx_drm_readl(dp->iomem, XILINX_DP_TX_VERSION);
1592
1593 dev_info(dp->dev, "device found, version %u.%02x%x\n",
1594 ((version & XILINX_DP_TX_VERSION_MAJOR_MASK) >>
1595 XILINX_DP_TX_VERSION_MAJOR_SHIFT),
1596 ((version & XILINX_DP_TX_VERSION_MINOR_MASK) >>
1597 XILINX_DP_TX_VERSION_MINOR_SHIFT),
1598 ((version & XILINX_DP_TX_VERSION_REVISION_MASK) >>
1599 XILINX_DP_TX_VERSION_REVISION_SHIFT));
1600
1601 version = xilinx_drm_readl(dp->iomem, XILINX_DP_TX_CORE_ID);
1602 if (version & XILINX_DP_TX_CORE_ID_DIRECTION) {
1603 dev_err(dp->dev, "Receiver is not supported\n");
1604 ret = -ENODEV;
1605 goto error;
1606 }
1607
1608 dev_info(dp->dev, "Display Port, version %u.%02x%02x (tx)\n",
1609 ((version & XILINX_DP_TX_CORE_ID_MAJOR_MASK) >>
1610 XILINX_DP_TX_CORE_ID_MAJOR_SHIFT),
1611 ((version & XILINX_DP_TX_CORE_ID_MINOR_MASK) >>
1612 XILINX_DP_TX_CORE_ID_MINOR_SHIFT),
1613 ((version & XILINX_DP_TX_CORE_ID_REVISION_MASK) >>
1614 XILINX_DP_TX_CORE_ID_REVISION_SHIFT));
1615
1616 pm_runtime_enable(dp->dev);
1617
1618 return 0;
1619
1620error:
1621 drm_dp_aux_unregister(&dp->aux);
1622error_dp_sub:
1623 xilinx_drm_dp_sub_put(dp->dp_sub);
1624error_phy:
1625 xilinx_drm_dp_exit_phy(dp);
1626error_aud_clk:
1627 if (dp->aud_clk)
1628 clk_disable_unprepare(dp->aud_clk);
1629error_aclk:
1630 clk_disable_unprepare(dp->aclk);
1631 return ret;
1632}
1633
1634static int xilinx_drm_dp_remove(struct platform_device *pdev)
1635{
1636 struct xilinx_drm_dp *dp = platform_get_drvdata(pdev);
1637
1638 pm_runtime_disable(dp->dev);
1639 xilinx_drm_writel(dp->iomem, XILINX_DP_TX_ENABLE, 0);
1640
1641 drm_dp_aux_unregister(&dp->aux);
1642 xilinx_drm_dp_exit_phy(dp);
1643 xilinx_drm_dp_sub_put(dp->dp_sub);
1644
1645 if (dp->aud_clk)
1646 clk_disable_unprepare(dp->aud_clk);
1647 clk_disable_unprepare(dp->aclk);
1648
1649 return 0;
1650}
1651
1652static const struct of_device_id xilinx_drm_dp_of_match[] = {
1653 { .compatible = "xlnx,v-dp", },
1654 { },
1655};
1656MODULE_DEVICE_TABLE(of, xilinx_drm_dp_of_match);
1657
1658static struct drm_platform_encoder_driver xilinx_drm_dp_driver = {
1659 .platform_driver = {
1660 .probe = xilinx_drm_dp_probe,
1661 .remove = xilinx_drm_dp_remove,
1662 .driver = {
1663 .owner = THIS_MODULE,
1664 .name = "xilinx-drm-dp",
1665 .of_match_table = xilinx_drm_dp_of_match,
1666 },
1667 },
1668
1669 .encoder_init = xilinx_drm_dp_encoder_init,
1670};
1671
1672static int __init xilinx_drm_dp_init(void)
1673{
1674 return platform_driver_register(&xilinx_drm_dp_driver.platform_driver);
1675}
1676
1677static void __exit xilinx_drm_dp_exit(void)
1678{
1679 platform_driver_unregister(&xilinx_drm_dp_driver.platform_driver);
1680}
1681
1682module_init(xilinx_drm_dp_init);
1683module_exit(xilinx_drm_dp_exit);
1684
1685MODULE_AUTHOR("Xilinx, Inc.");
1686MODULE_DESCRIPTION("Xilinx DRM KMS DiplayPort Driver");
1687MODULE_LICENSE("GPL v2");
1688