LXR linux/drivers/gpu/drm/xilinx/xilinx_drm

   1/*
   2 * Xilinx DRM KMS Header for Xilinx
   3 *
   4 *  Copyright (C) 2013 Xilinx, Inc.
   5 *
   6 *  Author: Hyun Woo Kwon <hyunk@xilinx.com>
   7 *
   8 * This software is licensed under the terms of the GNU General Public
   9 * License version 2, as published by the Free Software Foundation, and
  10 * may be copied, distributed, and modified under those terms.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 */
  17
  18#ifndef _XILINX_DRM_H_
  19#define _XILINX_DRM_H_
  20
  21enum xilinx_video_format {
  22        XILINX_VIDEO_FORMAT_YUV422 = 0,
  23        XILINX_VIDEO_FORMAT_YUV444 = 1,
  24        XILINX_VIDEO_FORMAT_RGB = 2,
  25        XILINX_VIDEO_FORMAT_YUV420 = 3,
  26        XILINX_VIDEO_FORMAT_XRGB = 16,
  27        XILINX_VIDEO_FORMAT_NONE = 32,
  28};
  29
  30/* convert the xilinx format to the drm format */
  31int xilinx_drm_format_by_code(unsigned int xilinx_format, uint32_t *drm_format);
  32int xilinx_drm_format_by_name(const char *name, uint32_t *drm_format);
  33
  34unsigned int xilinx_drm_format_bpp(uint32_t drm_format);
  35unsigned int xilinx_drm_format_depth(uint32_t drm_format);
  36
  37/* io write operations */
  38static inline void xilinx_drm_writel(void __iomem *base, int offset, u32 val)
  39{
  40        writel(val, base + offset);
  41}
  42
  43/* io read operations */
  44static inline u32 xilinx_drm_readl(void __iomem *base, int offset)
  45{
  46        return readl(base + offset);
  47}
  48
  49static inline void xilinx_drm_clr(void __iomem *base, int offset, u32 clr)
  50{
  51        xilinx_drm_writel(base, offset, xilinx_drm_readl(base, offset) & ~clr);
  52}
  53
  54static inline void xilinx_drm_set(void __iomem *base, int offset, u32 set)
  55{
  56        xilinx_drm_writel(base, offset, xilinx_drm_readl(base, offset) | set);
  57}
  58
  59struct drm_device;
  60struct drm_mode_set;
  61
  62bool xilinx_drm_check_format(struct drm_device *drm, uint32_t fourcc);
  63uint32_t xilinx_drm_get_format(struct drm_device *drm);
  64unsigned int xilinx_drm_get_align(struct drm_device *drm);
  65void xilinx_drm_set_config(struct drm_device *drm, struct drm_mode_set *set);
  66
  67#endif /* _XILINX_DRM_H_ */
  68