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24#include <linux/export.h>
25#include <linux/errno.h>
26#include <linux/err.h>
27#include <linux/i2c.h>
28#include <linux/interrupt.h>
29#include <linux/io.h>
30#include <linux/pm_runtime.h>
31#include <linux/delay.h>
32#include <linux/module.h>
33#include "i2c-designware-core.h"
34
35
36
37
38#define DW_IC_CON 0x0
39#define DW_IC_TAR 0x4
40#define DW_IC_DATA_CMD 0x10
41#define DW_IC_SS_SCL_HCNT 0x14
42#define DW_IC_SS_SCL_LCNT 0x18
43#define DW_IC_FS_SCL_HCNT 0x1c
44#define DW_IC_FS_SCL_LCNT 0x20
45#define DW_IC_HS_SCL_HCNT 0x24
46#define DW_IC_HS_SCL_LCNT 0x28
47#define DW_IC_INTR_STAT 0x2c
48#define DW_IC_INTR_MASK 0x30
49#define DW_IC_RAW_INTR_STAT 0x34
50#define DW_IC_RX_TL 0x38
51#define DW_IC_TX_TL 0x3c
52#define DW_IC_CLR_INTR 0x40
53#define DW_IC_CLR_RX_UNDER 0x44
54#define DW_IC_CLR_RX_OVER 0x48
55#define DW_IC_CLR_TX_OVER 0x4c
56#define DW_IC_CLR_RD_REQ 0x50
57#define DW_IC_CLR_TX_ABRT 0x54
58#define DW_IC_CLR_RX_DONE 0x58
59#define DW_IC_CLR_ACTIVITY 0x5c
60#define DW_IC_CLR_STOP_DET 0x60
61#define DW_IC_CLR_START_DET 0x64
62#define DW_IC_CLR_GEN_CALL 0x68
63#define DW_IC_ENABLE 0x6c
64#define DW_IC_STATUS 0x70
65#define DW_IC_TXFLR 0x74
66#define DW_IC_RXFLR 0x78
67#define DW_IC_SDA_HOLD 0x7c
68#define DW_IC_TX_ABRT_SOURCE 0x80
69#define DW_IC_ENABLE_STATUS 0x9c
70#define DW_IC_COMP_PARAM_1 0xf4
71#define DW_IC_COMP_VERSION 0xf8
72#define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
73#define DW_IC_COMP_TYPE 0xfc
74#define DW_IC_COMP_TYPE_VALUE 0x44570140
75
76#define DW_IC_INTR_RX_UNDER 0x001
77#define DW_IC_INTR_RX_OVER 0x002
78#define DW_IC_INTR_RX_FULL 0x004
79#define DW_IC_INTR_TX_OVER 0x008
80#define DW_IC_INTR_TX_EMPTY 0x010
81#define DW_IC_INTR_RD_REQ 0x020
82#define DW_IC_INTR_TX_ABRT 0x040
83#define DW_IC_INTR_RX_DONE 0x080
84#define DW_IC_INTR_ACTIVITY 0x100
85#define DW_IC_INTR_STOP_DET 0x200
86#define DW_IC_INTR_START_DET 0x400
87#define DW_IC_INTR_GEN_CALL 0x800
88
89#define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
90 DW_IC_INTR_TX_EMPTY | \
91 DW_IC_INTR_TX_ABRT | \
92 DW_IC_INTR_STOP_DET)
93
94#define DW_IC_STATUS_ACTIVITY 0x1
95
96#define DW_IC_SDA_HOLD_RX_SHIFT 16
97#define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, DW_IC_SDA_HOLD_RX_SHIFT)
98
99#define DW_IC_ERR_TX_ABRT 0x1
100
101#define DW_IC_TAR_10BITADDR_MASTER BIT(12)
102
103#define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3))
104#define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2)
105
106
107
108
109#define STATUS_IDLE 0x0
110#define STATUS_WRITE_IN_PROGRESS 0x1
111#define STATUS_READ_IN_PROGRESS 0x2
112
113#define TIMEOUT 20
114
115
116
117
118
119
120
121#define ABRT_7B_ADDR_NOACK 0
122#define ABRT_10ADDR1_NOACK 1
123#define ABRT_10ADDR2_NOACK 2
124#define ABRT_TXDATA_NOACK 3
125#define ABRT_GCALL_NOACK 4
126#define ABRT_GCALL_READ 5
127#define ABRT_SBYTE_ACKDET 7
128#define ABRT_SBYTE_NORSTRT 9
129#define ABRT_10B_RD_NORSTRT 10
130#define ABRT_MASTER_DIS 11
131#define ARB_LOST 12
132
133#define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
134#define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
135#define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
136#define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
137#define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
138#define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
139#define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
140#define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
141#define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
142#define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
143#define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
144
145#define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
146 DW_IC_TX_ABRT_10ADDR1_NOACK | \
147 DW_IC_TX_ABRT_10ADDR2_NOACK | \
148 DW_IC_TX_ABRT_TXDATA_NOACK | \
149 DW_IC_TX_ABRT_GCALL_NOACK)
150
151static char *abort_sources[] = {
152 [ABRT_7B_ADDR_NOACK] =
153 "slave address not acknowledged (7bit mode)",
154 [ABRT_10ADDR1_NOACK] =
155 "first address byte not acknowledged (10bit mode)",
156 [ABRT_10ADDR2_NOACK] =
157 "second address byte not acknowledged (10bit mode)",
158 [ABRT_TXDATA_NOACK] =
159 "data not acknowledged",
160 [ABRT_GCALL_NOACK] =
161 "no acknowledgement for a general call",
162 [ABRT_GCALL_READ] =
163 "read after general call",
164 [ABRT_SBYTE_ACKDET] =
165 "start byte acknowledged",
166 [ABRT_SBYTE_NORSTRT] =
167 "trying to send start byte when restart is disabled",
168 [ABRT_10B_RD_NORSTRT] =
169 "trying to read when restart is disabled (10bit mode)",
170 [ABRT_MASTER_DIS] =
171 "trying to use disabled adapter",
172 [ARB_LOST] =
173 "lost arbitration",
174};
175
176static u32 dw_readl(struct dw_i2c_dev *dev, int offset)
177{
178 u32 value;
179
180 if (dev->accessor_flags & ACCESS_16BIT)
181 value = readw_relaxed(dev->base + offset) |
182 (readw_relaxed(dev->base + offset + 2) << 16);
183 else
184 value = readl_relaxed(dev->base + offset);
185
186 if (dev->accessor_flags & ACCESS_SWAP)
187 return swab32(value);
188 else
189 return value;
190}
191
192static void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
193{
194 if (dev->accessor_flags & ACCESS_SWAP)
195 b = swab32(b);
196
197 if (dev->accessor_flags & ACCESS_16BIT) {
198 writew_relaxed((u16)b, dev->base + offset);
199 writew_relaxed((u16)(b >> 16), dev->base + offset + 2);
200 } else {
201 writel_relaxed(b, dev->base + offset);
202 }
203}
204
205static u32
206i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
207{
208
209
210
211
212
213 if (cond)
214
215
216
217
218
219
220
221
222
223
224
225 return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset;
226 else
227
228
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230
231
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233
234
235
236
237
238
239
240
241 return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000
242 - 3 + offset;
243}
244
245static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
246{
247
248
249
250
251
252
253
254
255
256
257
258 return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset;
259}
260
261static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable)
262{
263 dw_writel(dev, enable, DW_IC_ENABLE);
264}
265
266static void __i2c_dw_enable_and_wait(struct dw_i2c_dev *dev, bool enable)
267{
268 int timeout = 100;
269
270 do {
271 __i2c_dw_enable(dev, enable);
272 if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable)
273 return;
274
275
276
277
278
279
280 usleep_range(25, 250);
281 } while (timeout--);
282
283 dev_warn(dev->dev, "timeout in %sabling adapter\n",
284 enable ? "en" : "dis");
285}
286
287static unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev)
288{
289
290
291
292
293 if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
294 return 0;
295 return dev->get_clk_rate_khz(dev);
296}
297
298static int i2c_dw_acquire_lock(struct dw_i2c_dev *dev)
299{
300 int ret;
301
302 if (!dev->acquire_lock)
303 return 0;
304
305 ret = dev->acquire_lock(dev);
306 if (!ret)
307 return 0;
308
309 dev_err(dev->dev, "couldn't acquire bus ownership\n");
310
311 return ret;
312}
313
314static void i2c_dw_release_lock(struct dw_i2c_dev *dev)
315{
316 if (dev->release_lock)
317 dev->release_lock(dev);
318}
319
320
321
322
323
324
325
326
327
328int i2c_dw_init(struct dw_i2c_dev *dev)
329{
330 u32 hcnt, lcnt;
331 u32 reg, comp_param1;
332 u32 sda_falling_time, scl_falling_time;
333 int ret;
334
335 ret = i2c_dw_acquire_lock(dev);
336 if (ret)
337 return ret;
338
339 reg = dw_readl(dev, DW_IC_COMP_TYPE);
340 if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
341
342 dev->accessor_flags |= ACCESS_SWAP;
343 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
344
345 dev->accessor_flags |= ACCESS_16BIT;
346 } else if (reg != DW_IC_COMP_TYPE_VALUE) {
347 dev_err(dev->dev, "Unknown Synopsys component type: "
348 "0x%08x\n", reg);
349 i2c_dw_release_lock(dev);
350 return -ENODEV;
351 }
352
353 comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
354
355
356 __i2c_dw_enable_and_wait(dev, false);
357
358
359
360 sda_falling_time = dev->sda_falling_time ?: 300;
361 scl_falling_time = dev->scl_falling_time ?: 300;
362
363
364 if (dev->ss_hcnt && dev->ss_lcnt) {
365 hcnt = dev->ss_hcnt;
366 lcnt = dev->ss_lcnt;
367 } else {
368 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
369 4000,
370 sda_falling_time,
371 0,
372 0);
373 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
374 4700,
375 scl_falling_time,
376 0);
377 }
378 dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
379 dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
380 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
381
382
383 if ((dev->clk_freq == 1000000) && dev->fp_hcnt && dev->fp_lcnt) {
384 hcnt = dev->fp_hcnt;
385 lcnt = dev->fp_lcnt;
386 } else if (dev->fs_hcnt && dev->fs_lcnt) {
387 hcnt = dev->fs_hcnt;
388 lcnt = dev->fs_lcnt;
389 } else {
390 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
391 600,
392 sda_falling_time,
393 0,
394 0);
395 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
396 1300,
397 scl_falling_time,
398 0);
399 }
400 dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
401 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
402 dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
403
404 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
405 DW_IC_CON_SPEED_HIGH) {
406 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
407 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
408 dev_err(dev->dev, "High Speed not supported!\n");
409 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
410 dev->master_cfg |= DW_IC_CON_SPEED_FAST;
411 } else if (dev->hs_hcnt && dev->hs_lcnt) {
412 hcnt = dev->hs_hcnt;
413 lcnt = dev->hs_lcnt;
414 dw_writel(dev, hcnt, DW_IC_HS_SCL_HCNT);
415 dw_writel(dev, lcnt, DW_IC_HS_SCL_LCNT);
416 dev_dbg(dev->dev, "HighSpeed-mode HCNT:LCNT = %d:%d\n",
417 hcnt, lcnt);
418 }
419 }
420
421
422 reg = dw_readl(dev, DW_IC_COMP_VERSION);
423 if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
424 if (!dev->sda_hold_time) {
425
426 dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD);
427 }
428
429
430
431
432
433
434
435 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
436 dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
437 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
438 } else {
439 dev_warn(dev->dev,
440 "Hardware too old to adjust SDA hold time.\n");
441 }
442
443
444 dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
445 dw_writel(dev, 0, DW_IC_RX_TL);
446
447
448 dw_writel(dev, dev->master_cfg , DW_IC_CON);
449
450 i2c_dw_release_lock(dev);
451
452 return 0;
453}
454EXPORT_SYMBOL_GPL(i2c_dw_init);
455
456
457
458
459static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
460{
461 int timeout = TIMEOUT;
462
463 while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
464 if (timeout <= 0) {
465 dev_warn(dev->dev, "timeout waiting for bus ready\n");
466 return -ETIMEDOUT;
467 }
468 timeout--;
469 usleep_range(1000, 1100);
470 }
471
472 return 0;
473}
474
475static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
476{
477 struct i2c_msg *msgs = dev->msgs;
478 u32 ic_tar = 0;
479
480
481 __i2c_dw_enable_and_wait(dev, false);
482
483
484 if (dev->dynamic_tar_update_enabled) {
485
486
487
488
489
490 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
491 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
492 } else {
493 u32 ic_con = dw_readl(dev, DW_IC_CON);
494
495 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
496 ic_con |= DW_IC_CON_10BITADDR_MASTER;
497 else
498 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
499 dw_writel(dev, ic_con, DW_IC_CON);
500 }
501
502
503
504
505
506 dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
507
508
509 i2c_dw_disable_int(dev);
510
511
512 __i2c_dw_enable(dev, true);
513
514
515 dw_readl(dev, DW_IC_CLR_INTR);
516 dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
517}
518
519
520
521
522
523
524
525static void
526i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
527{
528 struct i2c_msg *msgs = dev->msgs;
529 u32 intr_mask;
530 int tx_limit, rx_limit;
531 u32 addr = msgs[dev->msg_write_idx].addr;
532 u32 buf_len = dev->tx_buf_len;
533 u8 *buf = dev->tx_buf;
534 bool need_restart = false;
535
536 intr_mask = DW_IC_INTR_DEFAULT_MASK;
537
538 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
539
540
541
542
543
544 if (msgs[dev->msg_write_idx].addr != addr) {
545 dev_err(dev->dev,
546 "%s: invalid target address\n", __func__);
547 dev->msg_err = -EINVAL;
548 break;
549 }
550
551 if (msgs[dev->msg_write_idx].len == 0) {
552 dev_err(dev->dev,
553 "%s: invalid message length\n", __func__);
554 dev->msg_err = -EINVAL;
555 break;
556 }
557
558 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
559
560 buf = msgs[dev->msg_write_idx].buf;
561 buf_len = msgs[dev->msg_write_idx].len;
562
563
564
565
566
567 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
568 (dev->msg_write_idx > 0))
569 need_restart = true;
570 }
571
572 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
573 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
574
575 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
576 u32 cmd = 0;
577
578
579
580
581
582
583
584 if (dev->msg_write_idx == dev->msgs_num - 1 &&
585 buf_len == 1)
586 cmd |= BIT(9);
587
588 if (need_restart) {
589 cmd |= BIT(10);
590 need_restart = false;
591 }
592
593 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
594
595
596 if (dev->rx_outstanding >= dev->rx_fifo_depth)
597 break;
598
599 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
600 rx_limit--;
601 dev->rx_outstanding++;
602 } else
603 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
604 tx_limit--; buf_len--;
605 }
606
607 dev->tx_buf = buf;
608 dev->tx_buf_len = buf_len;
609
610 if (buf_len > 0) {
611
612 dev->status |= STATUS_WRITE_IN_PROGRESS;
613 break;
614 } else
615 dev->status &= ~STATUS_WRITE_IN_PROGRESS;
616 }
617
618
619
620
621
622 if (dev->msg_write_idx == dev->msgs_num)
623 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
624
625 if (dev->msg_err)
626 intr_mask = 0;
627
628 dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
629}
630
631static void
632i2c_dw_read(struct dw_i2c_dev *dev)
633{
634 struct i2c_msg *msgs = dev->msgs;
635 int rx_valid;
636
637 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
638 u32 len;
639 u8 *buf;
640
641 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
642 continue;
643
644 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
645 len = msgs[dev->msg_read_idx].len;
646 buf = msgs[dev->msg_read_idx].buf;
647 } else {
648 len = dev->rx_buf_len;
649 buf = dev->rx_buf;
650 }
651
652 rx_valid = dw_readl(dev, DW_IC_RXFLR);
653
654 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
655 *buf++ = dw_readl(dev, DW_IC_DATA_CMD);
656 dev->rx_outstanding--;
657 }
658
659 if (len > 0) {
660 dev->status |= STATUS_READ_IN_PROGRESS;
661 dev->rx_buf_len = len;
662 dev->rx_buf = buf;
663 return;
664 } else
665 dev->status &= ~STATUS_READ_IN_PROGRESS;
666 }
667}
668
669static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
670{
671 unsigned long abort_source = dev->abort_source;
672 int i;
673
674 if (abort_source & DW_IC_TX_ABRT_NOACK) {
675 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
676 dev_dbg(dev->dev,
677 "%s: %s\n", __func__, abort_sources[i]);
678 return -EREMOTEIO;
679 }
680
681 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
682 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
683
684 if (abort_source & DW_IC_TX_ARB_LOST)
685 return -EAGAIN;
686 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
687 return -EINVAL;
688 else
689 return -EIO;
690}
691
692
693
694
695static int
696i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
697{
698 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
699 int ret;
700
701 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
702
703 pm_runtime_get_sync(dev->dev);
704
705 reinit_completion(&dev->cmd_complete);
706 dev->msgs = msgs;
707 dev->msgs_num = num;
708 dev->cmd_err = 0;
709 dev->msg_write_idx = 0;
710 dev->msg_read_idx = 0;
711 dev->msg_err = 0;
712 dev->status = STATUS_IDLE;
713 dev->abort_source = 0;
714 dev->rx_outstanding = 0;
715
716 ret = i2c_dw_acquire_lock(dev);
717 if (ret)
718 goto done_nolock;
719
720 ret = i2c_dw_wait_bus_not_busy(dev);
721 if (ret < 0)
722 goto done;
723
724
725 i2c_dw_xfer_init(dev);
726
727
728 if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
729 dev_err(dev->dev, "controller timed out\n");
730
731 i2c_dw_init(dev);
732 ret = -ETIMEDOUT;
733 goto done;
734 }
735
736
737
738
739
740
741
742
743
744 __i2c_dw_enable(dev, false);
745
746 if (dev->msg_err) {
747 ret = dev->msg_err;
748 goto done;
749 }
750
751
752 if (likely(!dev->cmd_err && !dev->status)) {
753 ret = num;
754 goto done;
755 }
756
757
758 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
759 ret = i2c_dw_handle_tx_abort(dev);
760 goto done;
761 }
762
763 if (dev->status)
764 dev_err(dev->dev,
765 "transfer terminated early - interrupt latency too high?\n");
766
767 ret = -EIO;
768
769done:
770 i2c_dw_release_lock(dev);
771
772done_nolock:
773 pm_runtime_mark_last_busy(dev->dev);
774 pm_runtime_put_autosuspend(dev->dev);
775
776 return ret;
777}
778
779static u32 i2c_dw_func(struct i2c_adapter *adap)
780{
781 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
782 return dev->functionality;
783}
784
785static struct i2c_algorithm i2c_dw_algo = {
786 .master_xfer = i2c_dw_xfer,
787 .functionality = i2c_dw_func,
788};
789
790static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
791{
792 u32 stat;
793
794
795
796
797
798
799
800
801
802
803
804
805
806 stat = dw_readl(dev, DW_IC_INTR_STAT);
807
808
809
810
811
812
813
814
815 if (stat & DW_IC_INTR_RX_UNDER)
816 dw_readl(dev, DW_IC_CLR_RX_UNDER);
817 if (stat & DW_IC_INTR_RX_OVER)
818 dw_readl(dev, DW_IC_CLR_RX_OVER);
819 if (stat & DW_IC_INTR_TX_OVER)
820 dw_readl(dev, DW_IC_CLR_TX_OVER);
821 if (stat & DW_IC_INTR_RD_REQ)
822 dw_readl(dev, DW_IC_CLR_RD_REQ);
823 if (stat & DW_IC_INTR_TX_ABRT) {
824
825
826
827
828 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
829 dw_readl(dev, DW_IC_CLR_TX_ABRT);
830 }
831 if (stat & DW_IC_INTR_RX_DONE)
832 dw_readl(dev, DW_IC_CLR_RX_DONE);
833 if (stat & DW_IC_INTR_ACTIVITY)
834 dw_readl(dev, DW_IC_CLR_ACTIVITY);
835 if (stat & DW_IC_INTR_STOP_DET)
836 dw_readl(dev, DW_IC_CLR_STOP_DET);
837 if (stat & DW_IC_INTR_START_DET)
838 dw_readl(dev, DW_IC_CLR_START_DET);
839 if (stat & DW_IC_INTR_GEN_CALL)
840 dw_readl(dev, DW_IC_CLR_GEN_CALL);
841
842 return stat;
843}
844
845
846
847
848
849static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
850{
851 struct dw_i2c_dev *dev = dev_id;
852 u32 stat, enabled;
853
854 enabled = dw_readl(dev, DW_IC_ENABLE);
855 stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
856 dev_dbg(dev->dev, "%s: enabled=%#x stat=%#x\n", __func__, enabled, stat);
857 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
858 return IRQ_NONE;
859
860 stat = i2c_dw_read_clear_intrbits(dev);
861
862 if (stat & DW_IC_INTR_TX_ABRT) {
863 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
864 dev->status = STATUS_IDLE;
865
866
867
868
869
870 dw_writel(dev, 0, DW_IC_INTR_MASK);
871 goto tx_aborted;
872 }
873
874 if (stat & DW_IC_INTR_RX_FULL)
875 i2c_dw_read(dev);
876
877 if (stat & DW_IC_INTR_TX_EMPTY)
878 i2c_dw_xfer_msg(dev);
879
880
881
882
883
884
885
886tx_aborted:
887 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
888 complete(&dev->cmd_complete);
889 else if (unlikely(dev->accessor_flags & ACCESS_INTR_MASK)) {
890
891 stat = dw_readl(dev, DW_IC_INTR_MASK);
892 i2c_dw_disable_int(dev);
893 dw_writel(dev, stat, DW_IC_INTR_MASK);
894 }
895
896 return IRQ_HANDLED;
897}
898
899void i2c_dw_disable(struct dw_i2c_dev *dev)
900{
901
902 __i2c_dw_enable_and_wait(dev, false);
903
904
905 dw_writel(dev, 0, DW_IC_INTR_MASK);
906 dw_readl(dev, DW_IC_CLR_INTR);
907}
908EXPORT_SYMBOL_GPL(i2c_dw_disable);
909
910void i2c_dw_disable_int(struct dw_i2c_dev *dev)
911{
912 dw_writel(dev, 0, DW_IC_INTR_MASK);
913}
914EXPORT_SYMBOL_GPL(i2c_dw_disable_int);
915
916u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
917{
918 return dw_readl(dev, DW_IC_COMP_PARAM_1);
919}
920EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
921
922int i2c_dw_probe(struct dw_i2c_dev *dev)
923{
924 struct i2c_adapter *adap = &dev->adapter;
925 int r;
926 u32 reg;
927
928 init_completion(&dev->cmd_complete);
929
930 r = i2c_dw_init(dev);
931 if (r)
932 return r;
933
934 r = i2c_dw_acquire_lock(dev);
935 if (r)
936 return r;
937
938
939
940
941
942
943 reg = dw_readl(dev, DW_IC_CON);
944 dw_writel(dev, reg ^ DW_IC_CON_10BITADDR_MASTER, DW_IC_CON);
945
946 if ((dw_readl(dev, DW_IC_CON) & DW_IC_CON_10BITADDR_MASTER) ==
947 (reg & DW_IC_CON_10BITADDR_MASTER)) {
948 dev->dynamic_tar_update_enabled = true;
949 dev_dbg(dev->dev, "Dynamic TAR update enabled");
950 }
951
952 i2c_dw_release_lock(dev);
953
954 snprintf(adap->name, sizeof(adap->name),
955 "Synopsys DesignWare I2C adapter");
956 adap->retries = 3;
957 adap->algo = &i2c_dw_algo;
958 adap->dev.parent = dev->dev;
959 i2c_set_adapdata(adap, dev);
960
961 i2c_dw_disable_int(dev);
962 r = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr,
963 IRQF_SHARED | IRQF_COND_SUSPEND,
964 dev_name(dev->dev), dev);
965 if (r) {
966 dev_err(dev->dev, "failure requesting irq %i: %d\n",
967 dev->irq, r);
968 return r;
969 }
970
971
972
973
974
975
976
977 pm_runtime_get_noresume(dev->dev);
978 r = i2c_add_numbered_adapter(adap);
979 if (r)
980 dev_err(dev->dev, "failure adding adapter: %d\n", r);
981 pm_runtime_put_noidle(dev->dev);
982
983 return r;
984}
985EXPORT_SYMBOL_GPL(i2c_dw_probe);
986
987MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
988MODULE_LICENSE("GPL");
989