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16#include <linux/module.h>
17#include <linux/i2c.h>
18#include <linux/iio/iio.h>
19#include <linux/acpi.h>
20#include <linux/regmap.h>
21#include <linux/iio/sysfs.h>
22#include <linux/iio/trigger.h>
23#include <linux/iio/buffer.h>
24#include <linux/iio/triggered_buffer.h>
25#include <linux/iio/trigger_consumer.h>
26
27#define MXC4005_DRV_NAME "mxc4005"
28#define MXC4005_IRQ_NAME "mxc4005_event"
29#define MXC4005_REGMAP_NAME "mxc4005_regmap"
30
31#define MXC4005_REG_XOUT_UPPER 0x03
32#define MXC4005_REG_XOUT_LOWER 0x04
33#define MXC4005_REG_YOUT_UPPER 0x05
34#define MXC4005_REG_YOUT_LOWER 0x06
35#define MXC4005_REG_ZOUT_UPPER 0x07
36#define MXC4005_REG_ZOUT_LOWER 0x08
37
38#define MXC4005_REG_INT_MASK1 0x0B
39#define MXC4005_REG_INT_MASK1_BIT_DRDYE 0x01
40
41#define MXC4005_REG_INT_CLR1 0x01
42#define MXC4005_REG_INT_CLR1_BIT_DRDYC 0x01
43
44#define MXC4005_REG_CONTROL 0x0D
45#define MXC4005_REG_CONTROL_MASK_FSR GENMASK(6, 5)
46#define MXC4005_CONTROL_FSR_SHIFT 5
47
48#define MXC4005_REG_DEVICE_ID 0x0E
49
50enum mxc4005_axis {
51 AXIS_X,
52 AXIS_Y,
53 AXIS_Z,
54};
55
56enum mxc4005_range {
57 MXC4005_RANGE_2G,
58 MXC4005_RANGE_4G,
59 MXC4005_RANGE_8G,
60};
61
62struct mxc4005_data {
63 struct device *dev;
64 struct mutex mutex;
65 struct regmap *regmap;
66 struct iio_trigger *dready_trig;
67 __be16 buffer[8];
68 bool trigger_enabled;
69};
70
71
72
73
74
75
76
77
78
79static const struct {
80 u8 range;
81 int scale;
82} mxc4005_scale_table[] = {
83 {MXC4005_RANGE_2G, 9582},
84 {MXC4005_RANGE_4G, 19164},
85 {MXC4005_RANGE_8G, 38329},
86};
87
88
89static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019164 0.038329");
90
91static struct attribute *mxc4005_attributes[] = {
92 &iio_const_attr_in_accel_scale_available.dev_attr.attr,
93 NULL,
94};
95
96static const struct attribute_group mxc4005_attrs_group = {
97 .attrs = mxc4005_attributes,
98};
99
100static bool mxc4005_is_readable_reg(struct device *dev, unsigned int reg)
101{
102 switch (reg) {
103 case MXC4005_REG_XOUT_UPPER:
104 case MXC4005_REG_XOUT_LOWER:
105 case MXC4005_REG_YOUT_UPPER:
106 case MXC4005_REG_YOUT_LOWER:
107 case MXC4005_REG_ZOUT_UPPER:
108 case MXC4005_REG_ZOUT_LOWER:
109 case MXC4005_REG_DEVICE_ID:
110 case MXC4005_REG_CONTROL:
111 return true;
112 default:
113 return false;
114 }
115}
116
117static bool mxc4005_is_writeable_reg(struct device *dev, unsigned int reg)
118{
119 switch (reg) {
120 case MXC4005_REG_INT_CLR1:
121 case MXC4005_REG_INT_MASK1:
122 case MXC4005_REG_CONTROL:
123 return true;
124 default:
125 return false;
126 }
127}
128
129static const struct regmap_config mxc4005_regmap_config = {
130 .name = MXC4005_REGMAP_NAME,
131
132 .reg_bits = 8,
133 .val_bits = 8,
134
135 .max_register = MXC4005_REG_DEVICE_ID,
136
137 .readable_reg = mxc4005_is_readable_reg,
138 .writeable_reg = mxc4005_is_writeable_reg,
139};
140
141static int mxc4005_read_xyz(struct mxc4005_data *data)
142{
143 int ret;
144
145 ret = regmap_bulk_read(data->regmap, MXC4005_REG_XOUT_UPPER,
146 (u8 *) data->buffer, sizeof(data->buffer));
147 if (ret < 0) {
148 dev_err(data->dev, "failed to read axes\n");
149 return ret;
150 }
151
152 return 0;
153}
154
155static int mxc4005_read_axis(struct mxc4005_data *data,
156 unsigned int addr)
157{
158 __be16 reg;
159 int ret;
160
161 ret = regmap_bulk_read(data->regmap, addr, (u8 *) ®, sizeof(reg));
162 if (ret < 0) {
163 dev_err(data->dev, "failed to read reg %02x\n", addr);
164 return ret;
165 }
166
167 return be16_to_cpu(reg);
168}
169
170static int mxc4005_read_scale(struct mxc4005_data *data)
171{
172 unsigned int reg;
173 int ret;
174 int i;
175
176 ret = regmap_read(data->regmap, MXC4005_REG_CONTROL, ®);
177 if (ret < 0) {
178 dev_err(data->dev, "failed to read reg_control\n");
179 return ret;
180 }
181
182 i = reg >> MXC4005_CONTROL_FSR_SHIFT;
183
184 if (i < 0 || i >= ARRAY_SIZE(mxc4005_scale_table))
185 return -EINVAL;
186
187 return mxc4005_scale_table[i].scale;
188}
189
190static int mxc4005_set_scale(struct mxc4005_data *data, int val)
191{
192 unsigned int reg;
193 int i;
194 int ret;
195
196 for (i = 0; i < ARRAY_SIZE(mxc4005_scale_table); i++) {
197 if (mxc4005_scale_table[i].scale == val) {
198 reg = i << MXC4005_CONTROL_FSR_SHIFT;
199 ret = regmap_update_bits(data->regmap,
200 MXC4005_REG_CONTROL,
201 MXC4005_REG_CONTROL_MASK_FSR,
202 reg);
203 if (ret < 0)
204 dev_err(data->dev,
205 "failed to write reg_control\n");
206 return ret;
207 }
208 }
209
210 return -EINVAL;
211}
212
213static int mxc4005_read_raw(struct iio_dev *indio_dev,
214 struct iio_chan_spec const *chan,
215 int *val, int *val2, long mask)
216{
217 struct mxc4005_data *data = iio_priv(indio_dev);
218 int ret;
219
220 switch (mask) {
221 case IIO_CHAN_INFO_RAW:
222 switch (chan->type) {
223 case IIO_ACCEL:
224 if (iio_buffer_enabled(indio_dev))
225 return -EBUSY;
226
227 ret = mxc4005_read_axis(data, chan->address);
228 if (ret < 0)
229 return ret;
230 *val = sign_extend32(ret >> chan->scan_type.shift,
231 chan->scan_type.realbits - 1);
232 return IIO_VAL_INT;
233 default:
234 return -EINVAL;
235 }
236 case IIO_CHAN_INFO_SCALE:
237 ret = mxc4005_read_scale(data);
238 if (ret < 0)
239 return ret;
240
241 *val = 0;
242 *val2 = ret;
243 return IIO_VAL_INT_PLUS_MICRO;
244 default:
245 return -EINVAL;
246 }
247}
248
249static int mxc4005_write_raw(struct iio_dev *indio_dev,
250 struct iio_chan_spec const *chan,
251 int val, int val2, long mask)
252{
253 struct mxc4005_data *data = iio_priv(indio_dev);
254
255 switch (mask) {
256 case IIO_CHAN_INFO_SCALE:
257 if (val != 0)
258 return -EINVAL;
259
260 return mxc4005_set_scale(data, val2);
261 default:
262 return -EINVAL;
263 }
264}
265
266static const struct iio_info mxc4005_info = {
267 .driver_module = THIS_MODULE,
268 .read_raw = mxc4005_read_raw,
269 .write_raw = mxc4005_write_raw,
270 .attrs = &mxc4005_attrs_group,
271};
272
273static const unsigned long mxc4005_scan_masks[] = {
274 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
275 0
276};
277
278#define MXC4005_CHANNEL(_axis, _addr) { \
279 .type = IIO_ACCEL, \
280 .modified = 1, \
281 .channel2 = IIO_MOD_##_axis, \
282 .address = _addr, \
283 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
284 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
285 .scan_index = AXIS_##_axis, \
286 .scan_type = { \
287 .sign = 's', \
288 .realbits = 12, \
289 .storagebits = 16, \
290 .shift = 4, \
291 .endianness = IIO_BE, \
292 }, \
293}
294
295static const struct iio_chan_spec mxc4005_channels[] = {
296 MXC4005_CHANNEL(X, MXC4005_REG_XOUT_UPPER),
297 MXC4005_CHANNEL(Y, MXC4005_REG_YOUT_UPPER),
298 MXC4005_CHANNEL(Z, MXC4005_REG_ZOUT_UPPER),
299 IIO_CHAN_SOFT_TIMESTAMP(3),
300};
301
302static irqreturn_t mxc4005_trigger_handler(int irq, void *private)
303{
304 struct iio_poll_func *pf = private;
305 struct iio_dev *indio_dev = pf->indio_dev;
306 struct mxc4005_data *data = iio_priv(indio_dev);
307 int ret;
308
309 ret = mxc4005_read_xyz(data);
310 if (ret < 0)
311 goto err;
312
313 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
314 pf->timestamp);
315
316err:
317 iio_trigger_notify_done(indio_dev->trig);
318
319 return IRQ_HANDLED;
320}
321
322static int mxc4005_clr_intr(struct mxc4005_data *data)
323{
324 int ret;
325
326
327 ret = regmap_write(data->regmap, MXC4005_REG_INT_CLR1,
328 MXC4005_REG_INT_CLR1_BIT_DRDYC);
329 if (ret < 0) {
330 dev_err(data->dev, "failed to write to reg_int_clr1\n");
331 return ret;
332 }
333
334 return 0;
335}
336
337static int mxc4005_set_trigger_state(struct iio_trigger *trig,
338 bool state)
339{
340 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
341 struct mxc4005_data *data = iio_priv(indio_dev);
342 int ret;
343
344 mutex_lock(&data->mutex);
345 if (state) {
346 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1,
347 MXC4005_REG_INT_MASK1_BIT_DRDYE);
348 } else {
349 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1,
350 ~MXC4005_REG_INT_MASK1_BIT_DRDYE);
351 }
352
353 if (ret < 0) {
354 mutex_unlock(&data->mutex);
355 dev_err(data->dev, "failed to update reg_int_mask1");
356 return ret;
357 }
358
359 data->trigger_enabled = state;
360 mutex_unlock(&data->mutex);
361
362 return 0;
363}
364
365static int mxc4005_trigger_try_reen(struct iio_trigger *trig)
366{
367 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
368 struct mxc4005_data *data = iio_priv(indio_dev);
369
370 if (!data->dready_trig)
371 return 0;
372
373 return mxc4005_clr_intr(data);
374}
375
376static const struct iio_trigger_ops mxc4005_trigger_ops = {
377 .set_trigger_state = mxc4005_set_trigger_state,
378 .try_reenable = mxc4005_trigger_try_reen,
379 .owner = THIS_MODULE,
380};
381
382static int mxc4005_chip_init(struct mxc4005_data *data)
383{
384 int ret;
385 unsigned int reg;
386
387 ret = regmap_read(data->regmap, MXC4005_REG_DEVICE_ID, ®);
388 if (ret < 0) {
389 dev_err(data->dev, "failed to read chip id\n");
390 return ret;
391 }
392
393 dev_dbg(data->dev, "MXC4005 chip id %02x\n", reg);
394
395 return 0;
396}
397
398static int mxc4005_probe(struct i2c_client *client,
399 const struct i2c_device_id *id)
400{
401 struct mxc4005_data *data;
402 struct iio_dev *indio_dev;
403 struct regmap *regmap;
404 int ret;
405
406 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
407 if (!indio_dev)
408 return -ENOMEM;
409
410 regmap = devm_regmap_init_i2c(client, &mxc4005_regmap_config);
411 if (IS_ERR(regmap)) {
412 dev_err(&client->dev, "failed to initialize regmap\n");
413 return PTR_ERR(regmap);
414 }
415
416 data = iio_priv(indio_dev);
417 i2c_set_clientdata(client, indio_dev);
418 data->dev = &client->dev;
419 data->regmap = regmap;
420
421 ret = mxc4005_chip_init(data);
422 if (ret < 0) {
423 dev_err(&client->dev, "failed to initialize chip\n");
424 return ret;
425 }
426
427 mutex_init(&data->mutex);
428
429 indio_dev->dev.parent = &client->dev;
430 indio_dev->channels = mxc4005_channels;
431 indio_dev->num_channels = ARRAY_SIZE(mxc4005_channels);
432 indio_dev->available_scan_masks = mxc4005_scan_masks;
433 indio_dev->name = MXC4005_DRV_NAME;
434 indio_dev->modes = INDIO_DIRECT_MODE;
435 indio_dev->info = &mxc4005_info;
436
437 ret = iio_triggered_buffer_setup(indio_dev,
438 iio_pollfunc_store_time,
439 mxc4005_trigger_handler,
440 NULL);
441 if (ret < 0) {
442 dev_err(&client->dev,
443 "failed to setup iio triggered buffer\n");
444 return ret;
445 }
446
447 if (client->irq > 0) {
448 data->dready_trig = devm_iio_trigger_alloc(&client->dev,
449 "%s-dev%d",
450 indio_dev->name,
451 indio_dev->id);
452 if (!data->dready_trig)
453 return -ENOMEM;
454
455 ret = devm_request_threaded_irq(&client->dev, client->irq,
456 iio_trigger_generic_data_rdy_poll,
457 NULL,
458 IRQF_TRIGGER_FALLING |
459 IRQF_ONESHOT,
460 MXC4005_IRQ_NAME,
461 data->dready_trig);
462 if (ret) {
463 dev_err(&client->dev,
464 "failed to init threaded irq\n");
465 goto err_buffer_cleanup;
466 }
467
468 data->dready_trig->dev.parent = &client->dev;
469 data->dready_trig->ops = &mxc4005_trigger_ops;
470 iio_trigger_set_drvdata(data->dready_trig, indio_dev);
471 indio_dev->trig = data->dready_trig;
472 iio_trigger_get(indio_dev->trig);
473 ret = iio_trigger_register(data->dready_trig);
474 if (ret) {
475 dev_err(&client->dev,
476 "failed to register trigger\n");
477 goto err_trigger_unregister;
478 }
479 }
480
481 ret = iio_device_register(indio_dev);
482 if (ret < 0) {
483 dev_err(&client->dev,
484 "unable to register iio device %d\n", ret);
485 goto err_buffer_cleanup;
486 }
487
488 return 0;
489
490err_trigger_unregister:
491 iio_trigger_unregister(data->dready_trig);
492err_buffer_cleanup:
493 iio_triggered_buffer_cleanup(indio_dev);
494
495 return ret;
496}
497
498static int mxc4005_remove(struct i2c_client *client)
499{
500 struct iio_dev *indio_dev = i2c_get_clientdata(client);
501 struct mxc4005_data *data = iio_priv(indio_dev);
502
503 iio_device_unregister(indio_dev);
504
505 iio_triggered_buffer_cleanup(indio_dev);
506 if (data->dready_trig)
507 iio_trigger_unregister(data->dready_trig);
508
509 return 0;
510}
511
512static const struct acpi_device_id mxc4005_acpi_match[] = {
513 {"MXC4005", 0},
514 { },
515};
516MODULE_DEVICE_TABLE(acpi, mxc4005_acpi_match);
517
518static const struct i2c_device_id mxc4005_id[] = {
519 {"mxc4005", 0},
520 { },
521};
522MODULE_DEVICE_TABLE(i2c, mxc4005_id);
523
524static struct i2c_driver mxc4005_driver = {
525 .driver = {
526 .name = MXC4005_DRV_NAME,
527 .acpi_match_table = ACPI_PTR(mxc4005_acpi_match),
528 },
529 .probe = mxc4005_probe,
530 .remove = mxc4005_remove,
531 .id_table = mxc4005_id,
532};
533
534module_i2c_driver(mxc4005_driver);
535
536MODULE_AUTHOR("Teodora Baluta <teodora.baluta@intel.com>");
537MODULE_LICENSE("GPL v2");
538MODULE_DESCRIPTION("MXC4005 3-axis accelerometer driver");
539
