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23#include "cx18-driver.h"
24#include "cx18-io.h"
25#include "cx18-irq.h"
26
27void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)
28{
29 u8 __iomem *dst = addr;
30 u16 val2 = val | (val << 8);
31 u32 val4 = val2 | (val2 << 16);
32
33
34 if ((count > 0) && ((unsigned long)dst & 1)) {
35 cx18_writeb(cx, (u8) val, dst);
36 count--;
37 dst++;
38 }
39 if ((count > 1) && ((unsigned long)dst & 2)) {
40 cx18_writew(cx, val2, dst);
41 count -= 2;
42 dst += 2;
43 }
44 while (count > 3) {
45 cx18_writel(cx, val4, dst);
46 count -= 4;
47 dst += 4;
48 }
49 if (count > 1) {
50 cx18_writew(cx, val2, dst);
51 count -= 2;
52 dst += 2;
53 }
54 if (count > 0)
55 cx18_writeb(cx, (u8) val, dst);
56}
57
58void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
59{
60 cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
61 cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val;
62 cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
63}
64
65void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
66{
67 cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val;
68 cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
69}
70
71void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
72{
73 cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val);
74 cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | val;
75 cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
76}
77
78void cx18_sw2_irq_disable(struct cx18 *cx, u32 val)
79{
80 cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) & ~val;
81 cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
82}
83
84void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val)
85{
86 u32 r;
87 r = cx18_read_reg(cx, SW2_INT_ENABLE_CPU);
88 cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU);
89}
90
91void cx18_setup_page(struct cx18 *cx, u32 addr)
92{
93 u32 val;
94 val = cx18_read_reg(cx, 0xD000F8);
95 val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00);
96 cx18_write_reg(cx, val, 0xD000F8);
97}
98