1
2
3
4
5
6
7
8
9
10
11
12#include <linux/slab.h>
13#include <linux/gpio.h>
14#include <linux/module.h>
15#include <linux/interrupt.h>
16#include <linux/mtd/mtd.h>
17#include <linux/mtd/nand.h>
18#include <linux/mtd/partitions.h>
19#include <linux/platform_device.h>
20#include <asm/io.h>
21#include <asm/mach-au1x00/au1000.h>
22#include <asm/mach-au1x00/au1550nd.h>
23
24
25struct au1550nd_ctx {
26 struct nand_chip chip;
27
28 int cs;
29 void __iomem *base;
30 void (*write_byte)(struct mtd_info *, u_char);
31};
32
33
34
35
36
37
38
39static u_char au_read_byte(struct mtd_info *mtd)
40{
41 struct nand_chip *this = mtd_to_nand(mtd);
42 u_char ret = readb(this->IO_ADDR_R);
43 wmb();
44 return ret;
45}
46
47
48
49
50
51
52
53
54static void au_write_byte(struct mtd_info *mtd, u_char byte)
55{
56 struct nand_chip *this = mtd_to_nand(mtd);
57 writeb(byte, this->IO_ADDR_W);
58 wmb();
59}
60
61
62
63
64
65
66
67static u_char au_read_byte16(struct mtd_info *mtd)
68{
69 struct nand_chip *this = mtd_to_nand(mtd);
70 u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
71 wmb();
72 return ret;
73}
74
75
76
77
78
79
80
81
82static void au_write_byte16(struct mtd_info *mtd, u_char byte)
83{
84 struct nand_chip *this = mtd_to_nand(mtd);
85 writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
86 wmb();
87}
88
89
90
91
92
93
94
95static u16 au_read_word(struct mtd_info *mtd)
96{
97 struct nand_chip *this = mtd_to_nand(mtd);
98 u16 ret = readw(this->IO_ADDR_R);
99 wmb();
100 return ret;
101}
102
103
104
105
106
107
108
109
110
111static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
112{
113 int i;
114 struct nand_chip *this = mtd_to_nand(mtd);
115
116 for (i = 0; i < len; i++) {
117 writeb(buf[i], this->IO_ADDR_W);
118 wmb();
119 }
120}
121
122
123
124
125
126
127
128
129
130static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
131{
132 int i;
133 struct nand_chip *this = mtd_to_nand(mtd);
134
135 for (i = 0; i < len; i++) {
136 buf[i] = readb(this->IO_ADDR_R);
137 wmb();
138 }
139}
140
141
142
143
144
145
146
147
148
149static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
150{
151 int i;
152 struct nand_chip *this = mtd_to_nand(mtd);
153 u16 *p = (u16 *) buf;
154 len >>= 1;
155
156 for (i = 0; i < len; i++) {
157 writew(p[i], this->IO_ADDR_W);
158 wmb();
159 }
160
161}
162
163
164
165
166
167
168
169
170
171static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
172{
173 int i;
174 struct nand_chip *this = mtd_to_nand(mtd);
175 u16 *p = (u16 *) buf;
176 len >>= 1;
177
178 for (i = 0; i < len; i++) {
179 p[i] = readw(this->IO_ADDR_R);
180 wmb();
181 }
182}
183
184
185#define NAND_CTL_SETNCE 1
186
187#define NAND_CTL_CLRNCE 2
188
189#define NAND_CTL_SETCLE 3
190
191#define NAND_CTL_CLRCLE 4
192
193#define NAND_CTL_SETALE 5
194
195#define NAND_CTL_CLRALE 6
196
197static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
198{
199 struct nand_chip *this = mtd_to_nand(mtd);
200 struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx,
201 chip);
202
203 switch (cmd) {
204
205 case NAND_CTL_SETCLE:
206 this->IO_ADDR_W = ctx->base + MEM_STNAND_CMD;
207 break;
208
209 case NAND_CTL_CLRCLE:
210 this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
211 break;
212
213 case NAND_CTL_SETALE:
214 this->IO_ADDR_W = ctx->base + MEM_STNAND_ADDR;
215 break;
216
217 case NAND_CTL_CLRALE:
218 this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
219
220
221 udelay(1);
222 break;
223
224 case NAND_CTL_SETNCE:
225
226 alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL);
227 break;
228
229 case NAND_CTL_CLRNCE:
230
231 alchemy_wrsmem(0, AU1000_MEM_STNDCTL);
232 break;
233 }
234
235 this->IO_ADDR_R = this->IO_ADDR_W;
236
237 wmb();
238}
239
240int au1550_device_ready(struct mtd_info *mtd)
241{
242 return (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1) ? 1 : 0;
243}
244
245
246
247
248
249
250
251
252
253
254
255
256
257static void au1550_select_chip(struct mtd_info *mtd, int chip)
258{
259}
260
261
262
263
264
265
266
267
268static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
269{
270 struct nand_chip *this = mtd_to_nand(mtd);
271 struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx,
272 chip);
273 int ce_override = 0, i;
274 unsigned long flags = 0;
275
276
277 au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
278
279
280
281 if (command == NAND_CMD_SEQIN) {
282 int readcmd;
283
284 if (column >= mtd->writesize) {
285
286 column -= mtd->writesize;
287 readcmd = NAND_CMD_READOOB;
288 } else if (column < 256) {
289
290 readcmd = NAND_CMD_READ0;
291 } else {
292 column -= 256;
293 readcmd = NAND_CMD_READ1;
294 }
295 ctx->write_byte(mtd, readcmd);
296 }
297 ctx->write_byte(mtd, command);
298
299
300 au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
301
302 if (column != -1 || page_addr != -1) {
303 au1550_hwcontrol(mtd, NAND_CTL_SETALE);
304
305
306 if (column != -1) {
307
308 if (this->options & NAND_BUSWIDTH_16 &&
309 !nand_opcode_8bits(command))
310 column >>= 1;
311 ctx->write_byte(mtd, column);
312 }
313 if (page_addr != -1) {
314 ctx->write_byte(mtd, (u8)(page_addr & 0xff));
315
316 if (command == NAND_CMD_READ0 ||
317 command == NAND_CMD_READ1 ||
318 command == NAND_CMD_READOOB) {
319
320
321
322
323
324
325
326
327 ce_override = 1;
328 local_irq_save(flags);
329 au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
330 }
331
332 ctx->write_byte(mtd, (u8)(page_addr >> 8));
333
334
335 if (this->chipsize > (32 << 20))
336 ctx->write_byte(mtd,
337 ((page_addr >> 16) & 0x0f));
338 }
339
340 au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
341 }
342
343
344
345
346
347 switch (command) {
348
349 case NAND_CMD_PAGEPROG:
350 case NAND_CMD_ERASE1:
351 case NAND_CMD_ERASE2:
352 case NAND_CMD_SEQIN:
353 case NAND_CMD_STATUS:
354 return;
355
356 case NAND_CMD_RESET:
357 break;
358
359 case NAND_CMD_READ0:
360 case NAND_CMD_READ1:
361 case NAND_CMD_READOOB:
362
363 if (unlikely(!ce_override))
364 break;
365
366
367 ndelay(100);
368
369 for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
370 udelay(1);
371
372
373 au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
374 local_irq_restore(flags);
375 return;
376 }
377
378 ndelay(100);
379
380 while(!this->dev_ready(mtd));
381}
382
383static int find_nand_cs(unsigned long nand_base)
384{
385 void __iomem *base =
386 (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
387 unsigned long addr, staddr, start, mask, end;
388 int i;
389
390 for (i = 0; i < 4; i++) {
391 addr = 0x1000 + (i * 0x10);
392 staddr = __raw_readl(base + addr + 0x08);
393
394 start = (staddr << 4) & 0xfffc0000;
395 mask = (staddr << 18) & 0xfffc0000;
396 end = (start | (start - 1)) & ~(start ^ mask);
397 if ((nand_base >= start) && (nand_base < end))
398 return i;
399 }
400
401 return -ENODEV;
402}
403
404static int au1550nd_probe(struct platform_device *pdev)
405{
406 struct au1550nd_platdata *pd;
407 struct au1550nd_ctx *ctx;
408 struct nand_chip *this;
409 struct mtd_info *mtd;
410 struct resource *r;
411 int ret, cs;
412
413 pd = dev_get_platdata(&pdev->dev);
414 if (!pd) {
415 dev_err(&pdev->dev, "missing platform data\n");
416 return -ENODEV;
417 }
418
419 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
420 if (!ctx)
421 return -ENOMEM;
422
423 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
424 if (!r) {
425 dev_err(&pdev->dev, "no NAND memory resource\n");
426 ret = -ENODEV;
427 goto out1;
428 }
429 if (request_mem_region(r->start, resource_size(r), "au1550-nand")) {
430 dev_err(&pdev->dev, "cannot claim NAND memory area\n");
431 ret = -ENOMEM;
432 goto out1;
433 }
434
435 ctx->base = ioremap_nocache(r->start, 0x1000);
436 if (!ctx->base) {
437 dev_err(&pdev->dev, "cannot remap NAND memory area\n");
438 ret = -ENODEV;
439 goto out2;
440 }
441
442 this = &ctx->chip;
443 mtd = nand_to_mtd(this);
444 mtd->dev.parent = &pdev->dev;
445
446
447 cs = find_nand_cs(r->start);
448 if (cs < 0) {
449 dev_err(&pdev->dev, "cannot detect NAND chipselect\n");
450 ret = -ENODEV;
451 goto out3;
452 }
453 ctx->cs = cs;
454
455 this->dev_ready = au1550_device_ready;
456 this->select_chip = au1550_select_chip;
457 this->cmdfunc = au1550_command;
458
459
460 this->chip_delay = 30;
461 this->ecc.mode = NAND_ECC_SOFT;
462 this->ecc.algo = NAND_ECC_HAMMING;
463
464 if (pd->devwidth)
465 this->options |= NAND_BUSWIDTH_16;
466
467 this->read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte;
468 ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte;
469 this->read_word = au_read_word;
470 this->write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf;
471 this->read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf;
472
473 ret = nand_scan(mtd, 1);
474 if (ret) {
475 dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);
476 goto out3;
477 }
478
479 mtd_device_register(mtd, pd->parts, pd->num_parts);
480
481 platform_set_drvdata(pdev, ctx);
482
483 return 0;
484
485out3:
486 iounmap(ctx->base);
487out2:
488 release_mem_region(r->start, resource_size(r));
489out1:
490 kfree(ctx);
491 return ret;
492}
493
494static int au1550nd_remove(struct platform_device *pdev)
495{
496 struct au1550nd_ctx *ctx = platform_get_drvdata(pdev);
497 struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
498
499 nand_release(nand_to_mtd(&ctx->chip));
500 iounmap(ctx->base);
501 release_mem_region(r->start, 0x1000);
502 kfree(ctx);
503 return 0;
504}
505
506static struct platform_driver au1550nd_driver = {
507 .driver = {
508 .name = "au1550-nand",
509 },
510 .probe = au1550nd_probe,
511 .remove = au1550nd_remove,
512};
513
514module_platform_driver(au1550nd_driver);
515
516MODULE_LICENSE("GPL");
517MODULE_AUTHOR("Embedded Edge, LLC");
518MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");
519