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35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
38#include "t4_hw.h"
39
40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/interrupt.h>
43#include <linux/list.h>
44#include <linux/netdevice.h>
45#include <linux/pci.h>
46#include <linux/spinlock.h>
47#include <linux/timer.h>
48#include <linux/vmalloc.h>
49#include <linux/etherdevice.h>
50#include <linux/net_tstamp.h>
51#include <asm/io.h>
52#include "t4_chip_type.h"
53#include "cxgb4_uld.h"
54
55#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
56extern struct list_head adapter_list;
57extern struct mutex uld_mutex;
58
59enum {
60 MAX_NPORTS = 4,
61 SERNUM_LEN = 24,
62 EC_LEN = 16,
63 ID_LEN = 16,
64 PN_LEN = 16,
65 MACADDR_LEN = 12,
66};
67
68enum {
69 T4_REGMAP_SIZE = (160 * 1024),
70 T5_REGMAP_SIZE = (332 * 1024),
71};
72
73enum {
74 MEM_EDC0,
75 MEM_EDC1,
76 MEM_MC,
77 MEM_MC0 = MEM_MC,
78 MEM_MC1
79};
80
81enum {
82 MEMWIN0_APERTURE = 2048,
83 MEMWIN0_BASE = 0x1b800,
84 MEMWIN1_APERTURE = 32768,
85 MEMWIN1_BASE = 0x28000,
86 MEMWIN1_BASE_T5 = 0x52000,
87 MEMWIN2_APERTURE = 65536,
88 MEMWIN2_BASE = 0x30000,
89 MEMWIN2_APERTURE_T5 = 131072,
90 MEMWIN2_BASE_T5 = 0x60000,
91};
92
93enum dev_master {
94 MASTER_CANT,
95 MASTER_MAY,
96 MASTER_MUST
97};
98
99enum dev_state {
100 DEV_STATE_UNINIT,
101 DEV_STATE_INIT,
102 DEV_STATE_ERR
103};
104
105enum {
106 PAUSE_RX = 1 << 0,
107 PAUSE_TX = 1 << 1,
108 PAUSE_AUTONEG = 1 << 2
109};
110
111struct port_stats {
112 u64 tx_octets;
113 u64 tx_frames;
114 u64 tx_bcast_frames;
115 u64 tx_mcast_frames;
116 u64 tx_ucast_frames;
117 u64 tx_error_frames;
118
119 u64 tx_frames_64;
120 u64 tx_frames_65_127;
121 u64 tx_frames_128_255;
122 u64 tx_frames_256_511;
123 u64 tx_frames_512_1023;
124 u64 tx_frames_1024_1518;
125 u64 tx_frames_1519_max;
126
127 u64 tx_drop;
128 u64 tx_pause;
129 u64 tx_ppp0;
130 u64 tx_ppp1;
131 u64 tx_ppp2;
132 u64 tx_ppp3;
133 u64 tx_ppp4;
134 u64 tx_ppp5;
135 u64 tx_ppp6;
136 u64 tx_ppp7;
137
138 u64 rx_octets;
139 u64 rx_frames;
140 u64 rx_bcast_frames;
141 u64 rx_mcast_frames;
142 u64 rx_ucast_frames;
143 u64 rx_too_long;
144 u64 rx_jabber;
145 u64 rx_fcs_err;
146 u64 rx_len_err;
147 u64 rx_symbol_err;
148 u64 rx_runt;
149
150 u64 rx_frames_64;
151 u64 rx_frames_65_127;
152 u64 rx_frames_128_255;
153 u64 rx_frames_256_511;
154 u64 rx_frames_512_1023;
155 u64 rx_frames_1024_1518;
156 u64 rx_frames_1519_max;
157
158 u64 rx_pause;
159 u64 rx_ppp0;
160 u64 rx_ppp1;
161 u64 rx_ppp2;
162 u64 rx_ppp3;
163 u64 rx_ppp4;
164 u64 rx_ppp5;
165 u64 rx_ppp6;
166 u64 rx_ppp7;
167
168 u64 rx_ovflow0;
169 u64 rx_ovflow1;
170 u64 rx_ovflow2;
171 u64 rx_ovflow3;
172 u64 rx_trunc0;
173 u64 rx_trunc1;
174 u64 rx_trunc2;
175 u64 rx_trunc3;
176};
177
178struct lb_port_stats {
179 u64 octets;
180 u64 frames;
181 u64 bcast_frames;
182 u64 mcast_frames;
183 u64 ucast_frames;
184 u64 error_frames;
185
186 u64 frames_64;
187 u64 frames_65_127;
188 u64 frames_128_255;
189 u64 frames_256_511;
190 u64 frames_512_1023;
191 u64 frames_1024_1518;
192 u64 frames_1519_max;
193
194 u64 drop;
195
196 u64 ovflow0;
197 u64 ovflow1;
198 u64 ovflow2;
199 u64 ovflow3;
200 u64 trunc0;
201 u64 trunc1;
202 u64 trunc2;
203 u64 trunc3;
204};
205
206struct tp_tcp_stats {
207 u32 tcp_out_rsts;
208 u64 tcp_in_segs;
209 u64 tcp_out_segs;
210 u64 tcp_retrans_segs;
211};
212
213struct tp_usm_stats {
214 u32 frames;
215 u32 drops;
216 u64 octets;
217};
218
219struct tp_fcoe_stats {
220 u32 frames_ddp;
221 u32 frames_drop;
222 u64 octets_ddp;
223};
224
225struct tp_err_stats {
226 u32 mac_in_errs[4];
227 u32 hdr_in_errs[4];
228 u32 tcp_in_errs[4];
229 u32 tnl_cong_drops[4];
230 u32 ofld_chan_drops[4];
231 u32 tnl_tx_drops[4];
232 u32 ofld_vlan_drops[4];
233 u32 tcp6_in_errs[4];
234 u32 ofld_no_neigh;
235 u32 ofld_cong_defer;
236};
237
238struct tp_cpl_stats {
239 u32 req[4];
240 u32 rsp[4];
241};
242
243struct tp_rdma_stats {
244 u32 rqe_dfr_pkt;
245 u32 rqe_dfr_mod;
246};
247
248struct sge_params {
249 u32 hps;
250 u32 eq_qpp;
251 u32 iq_qpp;
252};
253
254struct tp_params {
255 unsigned int tre;
256 unsigned int la_mask;
257 unsigned short tx_modq_map;
258
259
260 uint32_t dack_re;
261 unsigned short tx_modq[NCHAN];
262
263 u32 vlan_pri_map;
264 u32 ingress_config;
265
266
267
268
269
270
271
272
273
274
275
276
277 int vlan_shift;
278 int vnic_shift;
279 int port_shift;
280 int protocol_shift;
281};
282
283struct vpd_params {
284 unsigned int cclk;
285 u8 ec[EC_LEN + 1];
286 u8 sn[SERNUM_LEN + 1];
287 u8 id[ID_LEN + 1];
288 u8 pn[PN_LEN + 1];
289 u8 na[MACADDR_LEN + 1];
290};
291
292struct pci_params {
293 unsigned char speed;
294 unsigned char width;
295};
296
297struct devlog_params {
298 u32 memtype;
299 u32 start;
300 u32 size;
301};
302
303
304struct arch_specific_params {
305 u8 nchan;
306 u8 pm_stats_cnt;
307 u8 cng_ch_bits_log;
308 u16 mps_rplc_size;
309 u16 vfcount;
310 u32 sge_fl_db;
311 u16 mps_tcam_size;
312};
313
314struct adapter_params {
315 struct sge_params sge;
316 struct tp_params tp;
317 struct vpd_params vpd;
318 struct pci_params pci;
319 struct devlog_params devlog;
320 enum pcie_memwin drv_memwin;
321
322 unsigned int cim_la_size;
323
324 unsigned int sf_size;
325 unsigned int sf_nsec;
326 unsigned int sf_fw_start;
327
328 unsigned int fw_vers;
329 unsigned int bs_vers;
330 unsigned int tp_vers;
331 unsigned int er_vers;
332 u8 api_vers[7];
333
334 unsigned short mtus[NMTUS];
335 unsigned short a_wnd[NCCTRL_WIN];
336 unsigned short b_wnd[NCCTRL_WIN];
337
338 unsigned char nports;
339 unsigned char portvec;
340 enum chip_type chip;
341 struct arch_specific_params arch;
342 unsigned char offload;
343 unsigned char crypto;
344
345 unsigned char bypass;
346
347 unsigned int ofldq_wr_cred;
348 bool ulptx_memwrite_dsgl;
349
350 unsigned int nsched_cls;
351 unsigned int max_ordird_qp;
352 unsigned int max_ird_adapter;
353 bool fr_nsmr_tpte_wr_support;
354};
355
356
357
358
359struct sge_idma_monitor_state {
360 unsigned int idma_1s_thresh;
361 unsigned int idma_stalled[2];
362 unsigned int idma_state[2];
363 unsigned int idma_qid[2];
364 unsigned int idma_warn[2];
365};
366
367
368
369
370
371struct mbox_cmd {
372 u64 cmd[MBOX_LEN / 8];
373 u64 timestamp;
374 u32 seqno;
375 s16 access;
376 s16 execute;
377};
378
379struct mbox_cmd_log {
380 unsigned int size;
381 unsigned int cursor;
382 u32 seqno;
383
384};
385
386
387
388
389static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
390 unsigned int entry_idx)
391{
392 return &((struct mbox_cmd *)&(log)[1])[entry_idx];
393}
394
395#include "t4fw_api.h"
396
397#define FW_VERSION(chip) ( \
398 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
399 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
400 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
401 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
402#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
403
404struct fw_info {
405 u8 chip;
406 char *fs_name;
407 char *fw_mod_name;
408 struct fw_hdr fw_hdr;
409};
410
411struct trace_params {
412 u32 data[TRACE_LEN / 4];
413 u32 mask[TRACE_LEN / 4];
414 unsigned short snap_len;
415 unsigned short min_len;
416 unsigned char skip_ofst;
417 unsigned char skip_len;
418 unsigned char invert;
419 unsigned char port;
420};
421
422struct link_config {
423 unsigned short supported;
424 unsigned short advertising;
425 unsigned short lp_advertising;
426 unsigned int requested_speed;
427 unsigned int speed;
428 unsigned char requested_fc;
429 unsigned char fc;
430 unsigned char autoneg;
431 unsigned char link_ok;
432 unsigned char link_down_rc;
433};
434
435#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
436
437enum {
438 MAX_ETH_QSETS = 32,
439 MAX_OFLD_QSETS = 16,
440 MAX_CTRL_QUEUES = NCHAN,
441};
442
443enum {
444 MAX_TXQ_ENTRIES = 16384,
445 MAX_CTRL_TXQ_ENTRIES = 1024,
446 MAX_RSPQ_ENTRIES = 16384,
447 MAX_RX_BUFFERS = 16384,
448 MIN_TXQ_ENTRIES = 32,
449 MIN_CTRL_TXQ_ENTRIES = 32,
450 MIN_RSPQ_ENTRIES = 128,
451 MIN_FL_ENTRIES = 16
452};
453
454enum {
455 INGQ_EXTRAS = 2,
456
457 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS,
458};
459
460struct adapter;
461struct sge_rspq;
462
463#include "cxgb4_dcb.h"
464
465#ifdef CONFIG_CHELSIO_T4_FCOE
466#include "cxgb4_fcoe.h"
467#endif
468
469struct port_info {
470 struct adapter *adapter;
471 u16 viid;
472 s16 xact_addr_filt;
473 u16 rss_size;
474 s8 mdio_addr;
475 enum fw_port_type port_type;
476 u8 mod_type;
477 u8 port_id;
478 u8 tx_chan;
479 u8 lport;
480 u8 nqsets;
481 u8 first_qset;
482 u8 rss_mode;
483 struct link_config link_cfg;
484 u16 *rss;
485 struct port_stats stats_base;
486#ifdef CONFIG_CHELSIO_T4_DCB
487 struct port_dcb_info dcb;
488#endif
489#ifdef CONFIG_CHELSIO_T4_FCOE
490 struct cxgb_fcoe fcoe;
491#endif
492 bool rxtstamp;
493 struct hwtstamp_config tstamp_config;
494 struct sched_table *sched_tbl;
495};
496
497struct dentry;
498struct work_struct;
499
500enum {
501 FULL_INIT_DONE = (1 << 0),
502 DEV_ENABLED = (1 << 1),
503 USING_MSI = (1 << 2),
504 USING_MSIX = (1 << 3),
505 FW_OK = (1 << 4),
506 RSS_TNLALLLOOKUP = (1 << 5),
507 USING_SOFT_PARAMS = (1 << 6),
508 MASTER_PF = (1 << 7),
509 FW_OFLD_CONN = (1 << 9),
510};
511
512enum {
513 ULP_CRYPTO_LOOKASIDE = 1 << 0,
514};
515
516struct rx_sw_desc;
517
518struct sge_fl {
519 unsigned int avail;
520 unsigned int pend_cred;
521 unsigned int cidx;
522 unsigned int pidx;
523 unsigned long alloc_failed;
524 unsigned long large_alloc_failed;
525 unsigned long mapping_err;
526 unsigned long low;
527 unsigned long starving;
528
529 unsigned int cntxt_id;
530 unsigned int size;
531 struct rx_sw_desc *sdesc;
532 __be64 *desc;
533 dma_addr_t addr;
534 void __iomem *bar2_addr;
535 unsigned int bar2_qid;
536};
537
538
539struct pkt_gl {
540 u64 sgetstamp;
541 struct page_frag frags[MAX_SKB_FRAGS];
542 void *va;
543 unsigned int nfrags;
544 unsigned int tot_len;
545};
546
547typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
548 const struct pkt_gl *gl);
549typedef void (*rspq_flush_handler_t)(struct sge_rspq *q);
550
551struct t4_lro_mgr {
552#define MAX_LRO_SESSIONS 64
553 u8 lro_session_cnt;
554 unsigned long lro_pkts;
555 unsigned long lro_merged;
556 struct sk_buff_head lroq;
557};
558
559struct sge_rspq {
560 struct napi_struct napi;
561 const __be64 *cur_desc;
562 unsigned int cidx;
563 u8 gen;
564 u8 intr_params;
565 u8 next_intr_params;
566 u8 adaptive_rx;
567 u8 pktcnt_idx;
568 u8 uld;
569 u8 idx;
570 int offset;
571 u16 cntxt_id;
572 u16 abs_id;
573 __be64 *desc;
574 dma_addr_t phys_addr;
575 void __iomem *bar2_addr;
576 unsigned int bar2_qid;
577 unsigned int iqe_len;
578 unsigned int size;
579 struct adapter *adap;
580 struct net_device *netdev;
581 rspq_handler_t handler;
582 rspq_flush_handler_t flush_handler;
583 struct t4_lro_mgr lro_mgr;
584#ifdef CONFIG_NET_RX_BUSY_POLL
585#define CXGB_POLL_STATE_IDLE 0
586#define CXGB_POLL_STATE_NAPI BIT(0)
587#define CXGB_POLL_STATE_POLL BIT(1)
588#define CXGB_POLL_STATE_NAPI_YIELD BIT(2)
589#define CXGB_POLL_STATE_POLL_YIELD BIT(3)
590#define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \
591 CXGB_POLL_STATE_POLL_YIELD)
592#define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \
593 CXGB_POLL_STATE_POLL)
594#define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \
595 CXGB_POLL_STATE_POLL_YIELD)
596 unsigned int bpoll_state;
597 spinlock_t bpoll_lock;
598#endif
599
600};
601
602struct sge_eth_stats {
603 unsigned long pkts;
604 unsigned long lro_pkts;
605 unsigned long lro_merged;
606 unsigned long rx_cso;
607 unsigned long vlan_ex;
608 unsigned long rx_drops;
609};
610
611struct sge_eth_rxq {
612 struct sge_rspq rspq;
613 struct sge_fl fl;
614 struct sge_eth_stats stats;
615} ____cacheline_aligned_in_smp;
616
617struct sge_ofld_stats {
618 unsigned long pkts;
619 unsigned long imm;
620 unsigned long an;
621 unsigned long nomem;
622};
623
624struct sge_ofld_rxq {
625 struct sge_rspq rspq;
626 struct sge_fl fl;
627 struct sge_ofld_stats stats;
628} ____cacheline_aligned_in_smp;
629
630struct tx_desc {
631 __be64 flit[8];
632};
633
634struct tx_sw_desc;
635
636struct sge_txq {
637 unsigned int in_use;
638 unsigned int size;
639 unsigned int cidx;
640 unsigned int pidx;
641 unsigned long stops;
642 unsigned long restarts;
643 unsigned int cntxt_id;
644 struct tx_desc *desc;
645 struct tx_sw_desc *sdesc;
646 struct sge_qstat *stat;
647 dma_addr_t phys_addr;
648 spinlock_t db_lock;
649 int db_disabled;
650 unsigned short db_pidx;
651 unsigned short db_pidx_inc;
652 void __iomem *bar2_addr;
653 unsigned int bar2_qid;
654};
655
656struct sge_eth_txq {
657 struct sge_txq q;
658 struct netdev_queue *txq;
659#ifdef CONFIG_CHELSIO_T4_DCB
660 u8 dcb_prio;
661#endif
662 unsigned long tso;
663 unsigned long tx_cso;
664 unsigned long vlan_ins;
665 unsigned long mapping_err;
666} ____cacheline_aligned_in_smp;
667
668struct sge_ofld_txq {
669 struct sge_txq q;
670 struct adapter *adap;
671 struct sk_buff_head sendq;
672 struct tasklet_struct qresume_tsk;
673 bool service_ofldq_running;
674 u8 full;
675 unsigned long mapping_err;
676} ____cacheline_aligned_in_smp;
677
678struct sge_ctrl_txq {
679 struct sge_txq q;
680 struct adapter *adap;
681 struct sk_buff_head sendq;
682 struct tasklet_struct qresume_tsk;
683 u8 full;
684} ____cacheline_aligned_in_smp;
685
686struct sge_uld_rxq_info {
687 char name[IFNAMSIZ];
688 struct sge_ofld_rxq *uldrxq;
689 u16 *msix_tbl;
690 u16 *rspq_id;
691 u16 nrxq;
692 u16 nciq;
693 u8 uld;
694};
695
696struct sge {
697 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
698 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
699 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
700
701 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
702 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
703 struct sge_uld_rxq_info **uld_rxq_info;
704
705 struct sge_rspq intrq ____cacheline_aligned_in_smp;
706 spinlock_t intrq_lock;
707
708 u16 max_ethqsets;
709 u16 ethqsets;
710 u16 ethtxq_rover;
711 u16 ofldqsets;
712 u16 nqs_per_uld;
713 u16 timer_val[SGE_NTIMERS];
714 u8 counter_val[SGE_NCOUNTERS];
715 u32 fl_pg_order;
716 u32 stat_len;
717 u32 pktshift;
718 u32 fl_align;
719 u32 fl_starve_thres;
720
721 struct sge_idma_monitor_state idma_monitor;
722 unsigned int egr_start;
723 unsigned int egr_sz;
724 unsigned int ingr_start;
725 unsigned int ingr_sz;
726 void **egr_map;
727 struct sge_rspq **ingr_map;
728 unsigned long *starving_fl;
729 unsigned long *txq_maperr;
730 unsigned long *blocked_fl;
731 struct timer_list rx_timer;
732 struct timer_list tx_timer;
733};
734
735#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
736#define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
737
738struct l2t_data;
739
740#ifdef CONFIG_PCI_IOV
741
742
743
744
745
746#define NUM_OF_PF_WITH_SRIOV 4
747
748#endif
749
750struct doorbell_stats {
751 u32 db_drop;
752 u32 db_empty;
753 u32 db_full;
754};
755
756struct hash_mac_addr {
757 struct list_head list;
758 u8 addr[ETH_ALEN];
759};
760
761struct uld_msix_bmap {
762 unsigned long *msix_bmap;
763 unsigned int mapsize;
764 spinlock_t lock;
765};
766
767struct uld_msix_info {
768 unsigned short vec;
769 char desc[IFNAMSIZ + 10];
770 unsigned int idx;
771};
772
773struct vf_info {
774 unsigned char vf_mac_addr[ETH_ALEN];
775 bool pf_set_mac;
776};
777
778struct adapter {
779 void __iomem *regs;
780 void __iomem *bar2;
781 u32 t4_bar0;
782 struct pci_dev *pdev;
783 struct device *pdev_dev;
784 const char *name;
785 unsigned int mbox;
786 unsigned int pf;
787 unsigned int flags;
788 unsigned int adap_idx;
789 enum chip_type chip;
790
791 int msg_enable;
792
793 struct adapter_params params;
794 struct cxgb4_virt_res vres;
795 unsigned int swintr;
796
797 struct {
798 unsigned short vec;
799 char desc[IFNAMSIZ + 10];
800 } msix_info[MAX_INGQ + 1];
801 struct uld_msix_info *msix_info_ulds;
802 struct uld_msix_bmap msix_bmap_ulds;
803 int msi_idx;
804
805 struct doorbell_stats db_stats;
806 struct sge sge;
807
808 struct net_device *port[MAX_NPORTS];
809 u8 chan_map[NCHAN];
810
811 struct vf_info *vfinfo;
812 u8 num_vfs;
813
814 u32 filter_mode;
815 unsigned int l2t_start;
816 unsigned int l2t_end;
817 struct l2t_data *l2t;
818 unsigned int clipt_start;
819 unsigned int clipt_end;
820 struct clip_tbl *clipt;
821 struct cxgb4_uld_info *uld;
822 void *uld_handle[CXGB4_ULD_MAX];
823 unsigned int num_uld;
824 unsigned int num_ofld_uld;
825 struct list_head list_node;
826 struct list_head rcu_node;
827 struct list_head mac_hlist;
828
829 void *iscsi_ppm;
830
831 struct tid_info tids;
832 void **tid_release_head;
833 spinlock_t tid_release_lock;
834 struct workqueue_struct *workq;
835 struct work_struct tid_release_task;
836 struct work_struct db_full_task;
837 struct work_struct db_drop_task;
838 bool tid_release_task_busy;
839
840
841#define T4_OS_LOG_MBOX_CMDS 256
842 struct mbox_cmd_log *mbox_log;
843
844 struct mutex uld_mutex;
845
846 struct dentry *debugfs_root;
847 bool use_bd;
848 bool trace_rss;
849
850
851
852
853 spinlock_t stats_lock;
854 spinlock_t win0_lock ____cacheline_aligned_in_smp;
855
856
857 struct cxgb4_tc_u32_table *tc_u32;
858};
859
860
861
862
863struct ch_sched_params {
864 s8 type;
865 union {
866 struct {
867 s8 level;
868 s8 mode;
869 s8 rateunit;
870 s8 ratemode;
871 s8 channel;
872 s8 class;
873 s32 minrate;
874 s32 maxrate;
875 s16 weight;
876 s16 pktsize;
877 } params;
878 } u;
879};
880
881enum {
882 SCHED_CLASS_TYPE_PACKET = 0,
883};
884
885enum {
886 SCHED_CLASS_LEVEL_CL_RL = 0,
887};
888
889enum {
890 SCHED_CLASS_MODE_CLASS = 0,
891};
892
893enum {
894 SCHED_CLASS_RATEUNIT_BITS = 0,
895};
896
897enum {
898 SCHED_CLASS_RATEMODE_ABS = 1,
899};
900
901
902
903
904struct ch_sched_queue {
905 s8 queue;
906 s8 class;
907};
908
909
910
911#define ETHTYPE_BITWIDTH 16
912#define FRAG_BITWIDTH 1
913#define MACIDX_BITWIDTH 9
914#define FCOE_BITWIDTH 1
915#define IPORT_BITWIDTH 3
916#define MATCHTYPE_BITWIDTH 3
917#define PROTO_BITWIDTH 8
918#define TOS_BITWIDTH 8
919#define PF_BITWIDTH 8
920#define VF_BITWIDTH 8
921#define IVLAN_BITWIDTH 16
922#define OVLAN_BITWIDTH 16
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941struct ch_filter_tuple {
942
943
944
945
946
947
948 uint32_t ethtype:ETHTYPE_BITWIDTH;
949 uint32_t frag:FRAG_BITWIDTH;
950 uint32_t ivlan_vld:1;
951 uint32_t ovlan_vld:1;
952 uint32_t pfvf_vld:1;
953 uint32_t macidx:MACIDX_BITWIDTH;
954 uint32_t fcoe:FCOE_BITWIDTH;
955 uint32_t iport:IPORT_BITWIDTH;
956 uint32_t matchtype:MATCHTYPE_BITWIDTH;
957 uint32_t proto:PROTO_BITWIDTH;
958 uint32_t tos:TOS_BITWIDTH;
959 uint32_t pf:PF_BITWIDTH;
960 uint32_t vf:VF_BITWIDTH;
961 uint32_t ivlan:IVLAN_BITWIDTH;
962 uint32_t ovlan:OVLAN_BITWIDTH;
963
964
965
966
967 uint8_t lip[16];
968 uint8_t fip[16];
969 uint16_t lport;
970 uint16_t fport;
971};
972
973
974
975struct ch_filter_specification {
976
977
978 uint32_t hitcnts:1;
979 uint32_t prio:1;
980
981
982
983
984 uint32_t type:1;
985
986
987
988
989
990 uint32_t action:2;
991
992 uint32_t rpttid:1;
993
994 uint32_t dirsteer:1;
995 uint32_t iq:10;
996
997 uint32_t maskhash:1;
998 uint32_t dirsteerhash:1;
999
1000
1001
1002
1003
1004
1005 uint32_t eport:2;
1006 uint32_t newdmac:1;
1007 uint32_t newsmac:1;
1008 uint32_t newvlan:2;
1009 uint8_t dmac[ETH_ALEN];
1010 uint8_t smac[ETH_ALEN];
1011 uint16_t vlan;
1012
1013
1014
1015 struct ch_filter_tuple val;
1016 struct ch_filter_tuple mask;
1017};
1018
1019enum {
1020 FILTER_PASS = 0,
1021 FILTER_DROP,
1022 FILTER_SWITCH
1023};
1024
1025enum {
1026 VLAN_NOCHANGE = 0,
1027 VLAN_REMOVE,
1028 VLAN_INSERT,
1029 VLAN_REWRITE
1030};
1031
1032
1033
1034
1035
1036
1037
1038struct filter_entry {
1039
1040 u32 valid:1;
1041 u32 locked:1;
1042
1043 u32 pending:1;
1044 u32 smtidx:8;
1045 struct filter_ctx *ctx;
1046 struct l2t_entry *l2t;
1047 struct net_device *dev;
1048 u32 tid;
1049
1050
1051
1052
1053
1054
1055 struct ch_filter_specification fs;
1056};
1057
1058static inline int is_offload(const struct adapter *adap)
1059{
1060 return adap->params.offload;
1061}
1062
1063static inline int is_pci_uld(const struct adapter *adap)
1064{
1065 return adap->params.crypto;
1066}
1067
1068static inline int is_uld(const struct adapter *adap)
1069{
1070 return (adap->params.offload || adap->params.crypto);
1071}
1072
1073static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
1074{
1075 return readl(adap->regs + reg_addr);
1076}
1077
1078static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
1079{
1080 writel(val, adap->regs + reg_addr);
1081}
1082
1083#ifndef readq
1084static inline u64 readq(const volatile void __iomem *addr)
1085{
1086 return readl(addr) + ((u64)readl(addr + 4) << 32);
1087}
1088
1089static inline void writeq(u64 val, volatile void __iomem *addr)
1090{
1091 writel(val, addr);
1092 writel(val >> 32, addr + 4);
1093}
1094#endif
1095
1096static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
1097{
1098 return readq(adap->regs + reg_addr);
1099}
1100
1101static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
1102{
1103 writeq(val, adap->regs + reg_addr);
1104}
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
1116 u8 hw_addr[])
1117{
1118 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
1119 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
1120}
1121
1122
1123
1124
1125
1126
1127
1128static inline struct port_info *netdev2pinfo(const struct net_device *dev)
1129{
1130 return netdev_priv(dev);
1131}
1132
1133
1134
1135
1136
1137
1138
1139
1140static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
1141{
1142 return netdev_priv(adap->port[idx]);
1143}
1144
1145
1146
1147
1148
1149
1150
1151static inline struct adapter *netdev2adap(const struct net_device *dev)
1152{
1153 return netdev2pinfo(dev)->adapter;
1154}
1155
1156#ifdef CONFIG_NET_RX_BUSY_POLL
1157static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
1158{
1159 spin_lock_init(&q->bpoll_lock);
1160 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1161}
1162
1163static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
1164{
1165 bool rc = true;
1166
1167 spin_lock(&q->bpoll_lock);
1168 if (q->bpoll_state & CXGB_POLL_LOCKED) {
1169 q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD;
1170 rc = false;
1171 } else {
1172 q->bpoll_state = CXGB_POLL_STATE_NAPI;
1173 }
1174 spin_unlock(&q->bpoll_lock);
1175 return rc;
1176}
1177
1178static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
1179{
1180 bool rc = false;
1181
1182 spin_lock(&q->bpoll_lock);
1183 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
1184 rc = true;
1185 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1186 spin_unlock(&q->bpoll_lock);
1187 return rc;
1188}
1189
1190static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1191{
1192 bool rc = true;
1193
1194 spin_lock_bh(&q->bpoll_lock);
1195 if (q->bpoll_state & CXGB_POLL_LOCKED) {
1196 q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD;
1197 rc = false;
1198 } else {
1199 q->bpoll_state |= CXGB_POLL_STATE_POLL;
1200 }
1201 spin_unlock_bh(&q->bpoll_lock);
1202 return rc;
1203}
1204
1205static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1206{
1207 bool rc = false;
1208
1209 spin_lock_bh(&q->bpoll_lock);
1210 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
1211 rc = true;
1212 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1213 spin_unlock_bh(&q->bpoll_lock);
1214 return rc;
1215}
1216
1217static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1218{
1219 return q->bpoll_state & CXGB_POLL_USER_PEND;
1220}
1221#else
1222static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
1223{
1224}
1225
1226static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
1227{
1228 return true;
1229}
1230
1231static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
1232{
1233 return false;
1234}
1235
1236static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1237{
1238 return false;
1239}
1240
1241static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1242{
1243 return false;
1244}
1245
1246static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1247{
1248 return false;
1249}
1250#endif
1251
1252
1253
1254
1255
1256
1257static inline unsigned int mk_adap_vers(struct adapter *ap)
1258{
1259 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1260 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1261}
1262
1263
1264static inline unsigned int qtimer_val(const struct adapter *adap,
1265 const struct sge_rspq *q)
1266{
1267 unsigned int idx = q->intr_params >> 1;
1268
1269 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1270}
1271
1272
1273extern char cxgb4_driver_name[];
1274extern const char cxgb4_driver_version[];
1275
1276void t4_os_portmod_changed(const struct adapter *adap, int port_id);
1277void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1278
1279void *t4_alloc_mem(size_t size);
1280
1281void t4_free_sge_resources(struct adapter *adap);
1282void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
1283irq_handler_t t4_intr_handler(struct adapter *adap);
1284netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
1285int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1286 const struct pkt_gl *gl);
1287int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1288int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1289int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1290 struct net_device *dev, int intr_idx,
1291 struct sge_fl *fl, rspq_handler_t hnd,
1292 rspq_flush_handler_t flush_handler, int cong);
1293int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1294 struct net_device *dev, struct netdev_queue *netdevq,
1295 unsigned int iqid);
1296int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1297 struct net_device *dev, unsigned int iqid,
1298 unsigned int cmplqid);
1299int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
1300 unsigned int cmplqid);
1301int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
1302 struct net_device *dev, unsigned int iqid);
1303irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
1304int t4_sge_init(struct adapter *adap);
1305void t4_sge_start(struct adapter *adap);
1306void t4_sge_stop(struct adapter *adap);
1307int cxgb_busy_poll(struct napi_struct *napi);
1308void cxgb4_set_ethtool_ops(struct net_device *netdev);
1309int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
1310extern int dbfifo_int_thresh;
1311
1312#define for_each_port(adapter, iter) \
1313 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1314
1315static inline int is_bypass(struct adapter *adap)
1316{
1317 return adap->params.bypass;
1318}
1319
1320static inline int is_bypass_device(int device)
1321{
1322
1323 switch (device) {
1324 case 0x440b:
1325 case 0x440c:
1326 return 1;
1327 default:
1328 return 0;
1329 }
1330}
1331
1332static inline int is_10gbt_device(int device)
1333{
1334
1335 switch (device) {
1336 case 0x4409:
1337 case 0x4486:
1338 return 1;
1339
1340 default:
1341 return 0;
1342 }
1343}
1344
1345static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1346{
1347 return adap->params.vpd.cclk / 1000;
1348}
1349
1350static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1351 unsigned int us)
1352{
1353 return (us * adap->params.vpd.cclk) / 1000;
1354}
1355
1356static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1357 unsigned int ticks)
1358{
1359
1360 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1361 adapter->params.vpd.cclk);
1362}
1363
1364void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1365 u32 val);
1366
1367int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1368 int size, void *rpl, bool sleep_ok, int timeout);
1369int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1370 void *rpl, bool sleep_ok);
1371
1372static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1373 const void *cmd, int size, void *rpl,
1374 int timeout)
1375{
1376 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1377 timeout);
1378}
1379
1380static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1381 int size, void *rpl)
1382{
1383 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1384}
1385
1386static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1387 int size, void *rpl)
1388{
1389 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1390}
1391
1392
1393
1394
1395
1396
1397
1398
1399static inline int hash_mac_addr(const u8 *addr)
1400{
1401 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1402 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1403
1404 a ^= b;
1405 a ^= (a >> 12);
1406 a ^= (a >> 6);
1407 return a & 0x3f;
1408}
1409
1410int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1411 unsigned int cnt);
1412static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
1413 unsigned int us, unsigned int cnt,
1414 unsigned int size, unsigned int iqe_size)
1415{
1416 q->adap = adap;
1417 cxgb4_set_rspq_intr_params(q, us, cnt);
1418 q->iqe_len = iqe_size;
1419 q->size = size;
1420}
1421
1422void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1423 unsigned int data_reg, const u32 *vals,
1424 unsigned int nregs, unsigned int start_idx);
1425void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1426 unsigned int data_reg, u32 *vals, unsigned int nregs,
1427 unsigned int start_idx);
1428void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
1429
1430struct fw_filter_wr;
1431
1432void t4_intr_enable(struct adapter *adapter);
1433void t4_intr_disable(struct adapter *adapter);
1434int t4_slow_intr_handler(struct adapter *adapter);
1435
1436int t4_wait_dev_ready(void __iomem *regs);
1437int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
1438 struct link_config *lc);
1439int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
1440
1441u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1442u32 t4_get_util_window(struct adapter *adap);
1443void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1444
1445#define T4_MEMORY_WRITE 0
1446#define T4_MEMORY_READ 1
1447int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
1448 void *buf, int dir);
1449static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1450 u32 len, __be32 *buf)
1451{
1452 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1453}
1454
1455unsigned int t4_get_regs_len(struct adapter *adapter);
1456void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1457
1458int t4_seeprom_wp(struct adapter *adapter, bool enable);
1459int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1460int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
1461int t4_read_flash(struct adapter *adapter, unsigned int addr,
1462 unsigned int nwords, u32 *data, int byte_oriented);
1463int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
1464int t4_load_phy_fw(struct adapter *adap,
1465 int win, spinlock_t *lock,
1466 int (*phy_fw_version)(const u8 *, size_t),
1467 const u8 *phy_fw_data, size_t phy_fw_size);
1468int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
1469int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
1470int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1471 const u8 *fw_data, unsigned int size, int force);
1472int t4_fl_pkt_align(struct adapter *adap);
1473unsigned int t4_flash_cfg_addr(struct adapter *adapter);
1474int t4_check_fw_version(struct adapter *adap);
1475int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1476int t4_get_bs_version(struct adapter *adapter, u32 *vers);
1477int t4_get_tp_version(struct adapter *adapter, u32 *vers);
1478int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
1479int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1480 const u8 *fw_data, unsigned int fw_size,
1481 struct fw_hdr *card_fw, enum dev_state state, int *reset);
1482int t4_prep_adapter(struct adapter *adapter);
1483
1484enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1485int t4_bar2_sge_qregs(struct adapter *adapter,
1486 unsigned int qid,
1487 enum t4_bar2_qtype qtype,
1488 int user,
1489 u64 *pbar2_qoffset,
1490 unsigned int *pbar2_qid);
1491
1492unsigned int qtimer_val(const struct adapter *adap,
1493 const struct sge_rspq *q);
1494
1495int t4_init_devlog_params(struct adapter *adapter);
1496int t4_init_sge_params(struct adapter *adapter);
1497int t4_init_tp_params(struct adapter *adap);
1498int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
1499int t4_init_rss_mode(struct adapter *adap, int mbox);
1500int t4_init_portinfo(struct port_info *pi, int mbox,
1501 int port, int pf, int vf, u8 mac[]);
1502int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1503void t4_fatal_err(struct adapter *adapter);
1504int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1505 int start, int n, const u16 *rspq, unsigned int nrspq);
1506int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1507 unsigned int flags);
1508int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1509 unsigned int flags, unsigned int defq);
1510int t4_read_rss(struct adapter *adapter, u16 *entries);
1511void t4_read_rss_key(struct adapter *adapter, u32 *key);
1512void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx);
1513void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1514 u32 *valp);
1515void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1516 u32 *vfl, u32 *vfh);
1517u32 t4_read_rss_pf_map(struct adapter *adapter);
1518u32 t4_read_rss_pf_mask(struct adapter *adapter);
1519
1520unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx);
1521void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1522void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1523int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1524 size_t n);
1525int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1526 size_t n);
1527int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1528 unsigned int *valp);
1529int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1530 const unsigned int *valp);
1531int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
1532void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1533 unsigned int *pif_req_wrptr,
1534 unsigned int *pif_rsp_wrptr);
1535void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
1536void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
1537const char *t4_get_port_type_description(enum fw_port_type port_type);
1538void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
1539void t4_get_port_stats_offset(struct adapter *adap, int idx,
1540 struct port_stats *stats,
1541 struct port_stats *offset);
1542void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
1543void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
1544void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
1545void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1546 unsigned int mask, unsigned int val);
1547void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
1548void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st);
1549void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st);
1550void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st);
1551void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st);
1552void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1553 struct tp_tcp_stats *v6);
1554void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
1555 struct tp_fcoe_stats *st);
1556void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1557 const unsigned short *alpha, const unsigned short *beta);
1558
1559void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1560
1561void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
1562void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1563
1564void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1565 const u8 *addr);
1566int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1567 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1568
1569int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1570 enum dev_master master, enum dev_state *state);
1571int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1572int t4_early_init(struct adapter *adap, unsigned int mbox);
1573int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
1574int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1575 unsigned int cache_line_size);
1576int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
1577int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1578 unsigned int vf, unsigned int nparams, const u32 *params,
1579 u32 *val);
1580int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1581 unsigned int vf, unsigned int nparams, const u32 *params,
1582 u32 *val, int rw);
1583int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1584 unsigned int pf, unsigned int vf,
1585 unsigned int nparams, const u32 *params,
1586 const u32 *val, int timeout);
1587int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1588 unsigned int vf, unsigned int nparams, const u32 *params,
1589 const u32 *val);
1590int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1591 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1592 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1593 unsigned int vi, unsigned int cmask, unsigned int pmask,
1594 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1595int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1596 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1597 unsigned int *rss_size);
1598int t4_free_vi(struct adapter *adap, unsigned int mbox,
1599 unsigned int pf, unsigned int vf,
1600 unsigned int viid);
1601int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
1602 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1603 bool sleep_ok);
1604int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1605 unsigned int viid, bool free, unsigned int naddr,
1606 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1607int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
1608 unsigned int viid, unsigned int naddr,
1609 const u8 **addr, bool sleep_ok);
1610int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1611 int idx, const u8 *addr, bool persist, bool add_smt);
1612int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1613 bool ucast, u64 vec, bool sleep_ok);
1614int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1615 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
1616int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1617 bool rx_en, bool tx_en);
1618int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1619 unsigned int nblinks);
1620int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1621 unsigned int mmd, unsigned int reg, u16 *valp);
1622int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1623 unsigned int mmd, unsigned int reg, u16 val);
1624int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
1625 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1626 unsigned int fl0id, unsigned int fl1id);
1627int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1628 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1629 unsigned int fl0id, unsigned int fl1id);
1630int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1631 unsigned int vf, unsigned int eqid);
1632int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1633 unsigned int vf, unsigned int eqid);
1634int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1635 unsigned int vf, unsigned int eqid);
1636int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox);
1637void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);
1638int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
1639void t4_db_full(struct adapter *adapter);
1640void t4_db_dropped(struct adapter *adapter);
1641int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
1642 int filter_index, int enable);
1643void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
1644 int filter_index, int *enabled);
1645int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1646 u32 addr, u32 val);
1647int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
1648 int rateunit, int ratemode, int channel, int class,
1649 int minrate, int maxrate, int weight, int pktsize);
1650void t4_sge_decode_idma_state(struct adapter *adapter, int state);
1651void t4_free_mem(void *addr);
1652void t4_idma_monitor_init(struct adapter *adapter,
1653 struct sge_idma_monitor_state *idma);
1654void t4_idma_monitor(struct adapter *adapter,
1655 struct sge_idma_monitor_state *idma,
1656 int hz, int ticks);
1657int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
1658 unsigned int naddr, u8 *addr);
1659void t4_uld_mem_free(struct adapter *adap);
1660int t4_uld_mem_alloc(struct adapter *adap);
1661void t4_uld_clean_up(struct adapter *adap);
1662void t4_register_netevent_notifier(void);
1663void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl);
1664#endif
1665