LXR linux/drivers/net/ethernet/chelsio/cxgb4/t4

   1/*
   2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3 *
   4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
   5 *
   6 * This software is available to you under a choice of one of two
   7 * licenses.  You may choose to be licensed under the terms of the GNU
   8 * General Public License (GPL) Version 2, available from the file
   9 * COPYING in the main directory of this source tree, or the
  10 * OpenIB.org BSD license below:
  11 *
  12 *     Redistribution and use in source and binary forms, with or
  13 *     without modification, are permitted provided that the following
  14 *     conditions are met:
  15 *
  16 *      - Redistributions of source code must retain the above
  17 *        copyright notice, this list of conditions and the following
  18 *        disclaimer.
  19 *
  20 *      - Redistributions in binary form must reproduce the above
  21 *        copyright notice, this list of conditions and the following
  22 *        disclaimer in the documentation and/or other materials
  23 *        provided with the distribution.
  24 *
  25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32 * SOFTWARE.
  33 */
  34
  35#ifndef __T4_HW_H
  36#define __T4_HW_H
  37
  38#include <linux/types.h>
  39
  40enum {
  41        NCHAN          = 4,     /* # of HW channels */
  42        MAX_MTU        = 9600,  /* max MAC MTU, excluding header + FCS */
  43        EEPROMSIZE     = 17408, /* Serial EEPROM physical size */
  44        EEPROMVSIZE    = 32768, /* Serial EEPROM virtual address space size */
  45        EEPROMPFSIZE   = 1024,  /* EEPROM writable area size for PFn, n>0 */
  46        RSS_NENTRIES   = 2048,  /* # of entries in RSS mapping table */
  47        TCB_SIZE       = 128,   /* TCB size */
  48        NMTUS          = 16,    /* size of MTU table */
  49        NCCTRL_WIN     = 32,    /* # of congestion control windows */
  50        PM_NSTATS      = 5,     /* # of PM stats */
  51        T6_PM_NSTATS   = 7,     /* # of PM stats in T6 */
  52        MBOX_LEN       = 64,    /* mailbox size in bytes */
  53        TRACE_LEN      = 112,   /* length of trace data and mask */
  54        FILTER_OPT_LEN = 36,    /* filter tuple width for optional components */
  55};
  56
  57enum {
  58        CIM_NUM_IBQ    = 6,     /* # of CIM IBQs */
  59        CIM_NUM_OBQ    = 6,     /* # of CIM OBQs */
  60        CIM_NUM_OBQ_T5 = 8,     /* # of CIM OBQs for T5 adapter */
  61        CIMLA_SIZE     = 2048,  /* # of 32-bit words in CIM LA */
  62        CIM_PIFLA_SIZE = 64,    /* # of 192-bit words in CIM PIF LA */
  63        CIM_MALA_SIZE  = 64,    /* # of 160-bit words in CIM MA LA */
  64        CIM_IBQ_SIZE   = 128,   /* # of 128-bit words in a CIM IBQ */
  65        CIM_OBQ_SIZE   = 128,   /* # of 128-bit words in a CIM OBQ */
  66        TPLA_SIZE      = 128,   /* # of 64-bit words in TP LA */
  67        ULPRX_LA_SIZE  = 512,   /* # of 256-bit words in ULP_RX LA */
  68};
  69
  70enum {
  71        SF_PAGE_SIZE = 256,           /* serial flash page size */
  72        SF_SEC_SIZE = 64 * 1024,      /* serial flash sector size */
  73};
  74
  75enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */
  76
  77enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV };    /* mailbox owners */
  78
  79enum {
  80        SGE_MAX_WR_LEN = 512,     /* max WR size in bytes */
  81        SGE_NTIMERS = 6,          /* # of interrupt holdoff timer values */
  82        SGE_NCOUNTERS = 4,        /* # of interrupt packet counter values */
  83        SGE_MAX_IQ_SIZE = 65520,
  84
  85        SGE_TIMER_RSTRT_CNTR = 6, /* restart RX packet threshold counter */
  86        SGE_TIMER_UPD_CIDX = 7,   /* update cidx only */
  87
  88        SGE_EQ_IDXSIZE = 64,      /* egress queue pidx/cidx unit size */
  89
  90        SGE_INTRDST_PCI = 0,      /* interrupt destination is PCI-E */
  91        SGE_INTRDST_IQ = 1,       /*   destination is an ingress queue */
  92
  93        SGE_UPDATEDEL_NONE = 0,   /* ingress queue pidx update delivery */
  94        SGE_UPDATEDEL_INTR = 1,   /*   interrupt */
  95        SGE_UPDATEDEL_STPG = 2,   /*   status page */
  96        SGE_UPDATEDEL_BOTH = 3,   /*   interrupt and status page */
  97
  98        SGE_HOSTFCMODE_NONE = 0,  /* egress queue cidx updates */
  99        SGE_HOSTFCMODE_IQ = 1,    /*   sent to ingress queue */
 100        SGE_HOSTFCMODE_STPG = 2,  /*   sent to status page */
 101        SGE_HOSTFCMODE_BOTH = 3,  /*   ingress queue and status page */
 102
 103        SGE_FETCHBURSTMIN_16B = 0,/* egress queue descriptor fetch minimum */
 104        SGE_FETCHBURSTMIN_32B = 1,
 105        SGE_FETCHBURSTMIN_64B = 2,
 106        SGE_FETCHBURSTMIN_128B = 3,
 107
 108        SGE_FETCHBURSTMAX_64B = 0,/* egress queue descriptor fetch maximum */
 109        SGE_FETCHBURSTMAX_128B = 1,
 110        SGE_FETCHBURSTMAX_256B = 2,
 111        SGE_FETCHBURSTMAX_512B = 3,
 112
 113        SGE_CIDXFLUSHTHRESH_1 = 0,/* egress queue cidx flush threshold */
 114        SGE_CIDXFLUSHTHRESH_2 = 1,
 115        SGE_CIDXFLUSHTHRESH_4 = 2,
 116        SGE_CIDXFLUSHTHRESH_8 = 3,
 117        SGE_CIDXFLUSHTHRESH_16 = 4,
 118        SGE_CIDXFLUSHTHRESH_32 = 5,
 119        SGE_CIDXFLUSHTHRESH_64 = 6,
 120        SGE_CIDXFLUSHTHRESH_128 = 7,
 121
 122        SGE_INGPADBOUNDARY_SHIFT = 5,/* ingress queue pad boundary */
 123};
 124
 125/* PCI-e memory window access */
 126enum pcie_memwin {
 127        MEMWIN_NIC      = 0,
 128        MEMWIN_RSVD1    = 1,
 129        MEMWIN_RSVD2    = 2,
 130        MEMWIN_RDMA     = 3,
 131        MEMWIN_RSVD4    = 4,
 132        MEMWIN_FOISCSI  = 5,
 133        MEMWIN_CSIOSTOR = 6,
 134        MEMWIN_RSVD7    = 7,
 135};
 136
 137struct sge_qstat {                /* data written to SGE queue status entries */
 138        __be32 qid;
 139        __be16 cidx;
 140        __be16 pidx;
 141};
 142
 143/*
 144 * Structure for last 128 bits of response descriptors
 145 */
 146struct rsp_ctrl {
 147        __be32 hdrbuflen_pidx;
 148        __be32 pldbuflen_qid;
 149        union {
 150                u8 type_gen;
 151                __be64 last_flit;
 152        };
 153};
 154
 155#define RSPD_NEWBUF_S    31
 156#define RSPD_NEWBUF_V(x) ((x) << RSPD_NEWBUF_S)
 157#define RSPD_NEWBUF_F    RSPD_NEWBUF_V(1U)
 158
 159#define RSPD_LEN_S    0
 160#define RSPD_LEN_M    0x7fffffff
 161#define RSPD_LEN_G(x) (((x) >> RSPD_LEN_S) & RSPD_LEN_M)
 162
 163#define RSPD_QID_S    RSPD_LEN_S
 164#define RSPD_QID_M    RSPD_LEN_M
 165#define RSPD_QID_G(x) RSPD_LEN_G(x)
 166
 167#define RSPD_GEN_S    7
 168
 169#define RSPD_TYPE_S    4
 170#define RSPD_TYPE_M    0x3
 171#define RSPD_TYPE_G(x) (((x) >> RSPD_TYPE_S) & RSPD_TYPE_M)
 172
 173/* Rx queue interrupt deferral fields: counter enable and timer index */
 174#define QINTR_CNT_EN_S    0
 175#define QINTR_CNT_EN_V(x) ((x) << QINTR_CNT_EN_S)
 176#define QINTR_CNT_EN_F    QINTR_CNT_EN_V(1U)
 177
 178#define QINTR_TIMER_IDX_S    1
 179#define QINTR_TIMER_IDX_M    0x7
 180#define QINTR_TIMER_IDX_V(x) ((x) << QINTR_TIMER_IDX_S)
 181#define QINTR_TIMER_IDX_G(x) (((x) >> QINTR_TIMER_IDX_S) & QINTR_TIMER_IDX_M)
 182
 183/*
 184 * Flash layout.
 185 */
 186#define FLASH_START(start)      ((start) * SF_SEC_SIZE)
 187#define FLASH_MAX_SIZE(nsecs)   ((nsecs) * SF_SEC_SIZE)
 188
 189enum {
 190        /*
 191         * Various Expansion-ROM boot images, etc.
 192         */
 193        FLASH_EXP_ROM_START_SEC = 0,
 194        FLASH_EXP_ROM_NSECS = 6,
 195        FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
 196        FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),
 197
 198        /*
 199         * iSCSI Boot Firmware Table (iBFT) and other driver-related
 200         * parameters ...
 201         */
 202        FLASH_IBFT_START_SEC = 6,
 203        FLASH_IBFT_NSECS = 1,
 204        FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC),
 205        FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS),
 206
 207        /*
 208         * Boot configuration data.
 209         */
 210        FLASH_BOOTCFG_START_SEC = 7,
 211        FLASH_BOOTCFG_NSECS = 1,
 212        FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC),
 213        FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS),
 214
 215        /*
 216         * Location of firmware image in FLASH.
 217         */
 218        FLASH_FW_START_SEC = 8,
 219        FLASH_FW_NSECS = 16,
 220        FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
 221        FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
 222
 223        /* Location of bootstrap firmware image in FLASH.
 224         */
 225        FLASH_FWBOOTSTRAP_START_SEC = 27,
 226        FLASH_FWBOOTSTRAP_NSECS = 1,
 227        FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC),
 228        FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS),
 229
 230        /*
 231         * iSCSI persistent/crash information.
 232         */
 233        FLASH_ISCSI_CRASH_START_SEC = 29,
 234        FLASH_ISCSI_CRASH_NSECS = 1,
 235        FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC),
 236        FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS),
 237
 238        /*
 239         * FCoE persistent/crash information.
 240         */
 241        FLASH_FCOE_CRASH_START_SEC = 30,
 242        FLASH_FCOE_CRASH_NSECS = 1,
 243        FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
 244        FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
 245
 246        /*
 247         * Location of Firmware Configuration File in FLASH.  Since the FPGA
 248         * "FLASH" is smaller we need to store the Configuration File in a
 249         * different location -- which will overlap the end of the firmware
 250         * image if firmware ever gets that large ...
 251         */
 252        FLASH_CFG_START_SEC = 31,
 253        FLASH_CFG_NSECS = 1,
 254        FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
 255        FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
 256
 257        /* We don't support FLASH devices which can't support the full
 258         * standard set of sections which we need for normal
 259         * operations.
 260         */
 261        FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
 262
 263        FLASH_FPGA_CFG_START_SEC = 15,
 264        FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC),
 265
 266        /*
 267         * Sectors 32-63 are reserved for FLASH failover.
 268         */
 269};
 270
 271#undef FLASH_START
 272#undef FLASH_MAX_SIZE
 273
 274#define SGE_TIMESTAMP_S 0
 275#define SGE_TIMESTAMP_M 0xfffffffffffffffULL
 276#define SGE_TIMESTAMP_V(x) ((__u64)(x) << SGE_TIMESTAMP_S)
 277#define SGE_TIMESTAMP_G(x) (((__u64)(x) >> SGE_TIMESTAMP_S) & SGE_TIMESTAMP_M)
 278
 279#endif /* __T4_HW_H */
 280