1/* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35#ifndef __T4_VALUES_H__ 36#define __T4_VALUES_H__ 37 38/* This file contains definitions for various T4 register value hardware 39 * constants. The types of values encoded here are predominantly those for 40 * register fields which control "modal" behavior. For the most part, we do 41 * not include definitions for register fields which are simple numeric 42 * metrics, etc. 43 */ 44 45/* SGE register field values. 46 */ 47 48/* CONTROL1 register */ 49#define RXPKTCPLMODE_SPLIT_X 1 50 51#define INGPCIEBOUNDARY_SHIFT_X 5 52#define INGPCIEBOUNDARY_32B_X 0 53 54#define INGPADBOUNDARY_SHIFT_X 5 55 56#define T6_INGPADBOUNDARY_SHIFT_X 3 57#define T6_INGPADBOUNDARY_32B_X 2 58 59/* CONTROL2 register */ 60#define INGPACKBOUNDARY_SHIFT_X 5 61#define INGPACKBOUNDARY_16B_X 0 62 63/* GTS register */ 64#define SGE_TIMERREGS 6 65#define TIMERREG_COUNTER0_X 0 66 67#define FETCHBURSTMIN_64B_X 2 68#define FETCHBURSTMIN_128B_X 3 69 70#define FETCHBURSTMAX_256B_X 2 71#define FETCHBURSTMAX_512B_X 3 72 73#define HOSTFCMODE_STATUS_PAGE_X 2 74 75#define CIDXFLUSHTHRESH_32_X 5 76 77#define UPDATEDELIVERY_INTERRUPT_X 1 78 79#define RSPD_TYPE_FLBUF_X 0 80#define RSPD_TYPE_CPL_X 1 81#define RSPD_TYPE_INTR_X 2 82 83/* Congestion Manager Definitions. 84 */ 85#define CONMCTXT_CNGTPMODE_S 19 86#define CONMCTXT_CNGTPMODE_V(x) ((x) << CONMCTXT_CNGTPMODE_S) 87#define CONMCTXT_CNGCHMAP_S 0 88#define CONMCTXT_CNGCHMAP_V(x) ((x) << CONMCTXT_CNGCHMAP_S) 89#define CONMCTXT_CNGTPMODE_CHANNEL_X 2 90#define CONMCTXT_CNGTPMODE_QUEUE_X 1 91 92/* T5 and later support a new BAR2-based doorbell mechanism for Egress Queues. 93 * The User Doorbells are each 128 bytes in length with a Simple Doorbell at 94 * offsets 8x and a Write Combining single 64-byte Egress Queue Unit 95 * (IDXSIZE_UNIT_X) Gather Buffer interface at offset 64. For Ingress Queues, 96 * we have a Going To Sleep register at offsets 8x+4. 97 * 98 * As noted above, we have many instances of the Simple Doorbell and Going To 99 * Sleep registers at offsets 8x and 8x+4, respectively. We want to use a 100 * non-64-byte aligned offset for the Simple Doorbell in order to attempt to 101 * avoid buffering of the writes to the Simple Doorbell and we want to use a 102 * non-contiguous offset for the Going To Sleep writes in order to avoid 103 * possible combining between them. 104 */ 105#define SGE_UDB_SIZE 128 106#define SGE_UDB_KDOORBELL 8 107#define SGE_UDB_GTS 20 108#define SGE_UDB_WCDOORBELL 64 109 110/* CIM register field values. 111 */ 112#define X_MBOWNER_FW 1 113#define X_MBOWNER_PL 2 114 115/* PCI-E definitions */ 116#define WINDOW_SHIFT_X 10 117#define PCIEOFST_SHIFT_X 10 118 119/* TP_VLAN_PRI_MAP controls which subset of fields will be present in the 120 * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP 121 * selects for a particular field being present. These fields, when present 122 * in the Compressed Filter Tuple, have the following widths in bits. 123 */ 124#define FT_FCOE_W 1 125#define FT_PORT_W 3 126#define FT_VNIC_ID_W 17 127#define FT_VLAN_W 17 128#define FT_TOS_W 8 129#define FT_PROTOCOL_W 8 130#define FT_ETHERTYPE_W 16 131#define FT_MACMATCH_W 9 132#define FT_MPSHITTYPE_W 3 133#define FT_FRAGMENTATION_W 1 134 135/* Some of the Compressed Filter Tuple fields have internal structure. These 136 * bit shifts/masks describe those structures. All shifts are relative to the 137 * base position of the fields within the Compressed Filter Tuple 138 */ 139#define FT_VLAN_VLD_S 16 140#define FT_VLAN_VLD_V(x) ((x) << FT_VLAN_VLD_S) 141#define FT_VLAN_VLD_F FT_VLAN_VLD_V(1U) 142 143#define FT_VNID_ID_VF_S 0 144#define FT_VNID_ID_VF_V(x) ((x) << FT_VNID_ID_VF_S) 145 146#define FT_VNID_ID_PF_S 7 147#define FT_VNID_ID_PF_V(x) ((x) << FT_VNID_ID_PF_S) 148 149#define FT_VNID_ID_VLD_S 16 150#define FT_VNID_ID_VLD_V(x) ((x) << FT_VNID_ID_VLD_S) 151 152#endif /* __T4_VALUES_H__ */ 153