linux/drivers/net/ethernet/fealnx.c
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   1/*
   2        Written 1998-2000 by Donald Becker.
   3
   4        This software may be used and distributed according to the terms of
   5        the GNU General Public License (GPL), incorporated herein by reference.
   6        Drivers based on or derived from this code fall under the GPL and must
   7        retain the authorship, copyright and license notice.  This file is not
   8        a complete program and may only be used when the entire operating
   9        system is licensed under the GPL.
  10
  11        The author may be reached as becker@scyld.com, or C/O
  12        Scyld Computing Corporation
  13        410 Severn Ave., Suite 210
  14        Annapolis MD 21403
  15
  16        Support information and updates available at
  17        http://www.scyld.com/network/pci-skeleton.html
  18
  19        Linux kernel updates:
  20
  21        Version 2.51, Nov 17, 2001 (jgarzik):
  22        - Add ethtool support
  23        - Replace some MII-related magic numbers with constants
  24
  25*/
  26
  27#define DRV_NAME        "fealnx"
  28#define DRV_VERSION     "2.52"
  29#define DRV_RELDATE     "Sep-11-2006"
  30
  31static int debug;               /* 1-> print debug message */
  32static int max_interrupt_work = 20;
  33
  34/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
  35static int multicast_filter_limit = 32;
  36
  37/* Set the copy breakpoint for the copy-only-tiny-frames scheme. */
  38/* Setting to > 1518 effectively disables this feature.          */
  39static int rx_copybreak;
  40
  41/* Used to pass the media type, etc.                            */
  42/* Both 'options[]' and 'full_duplex[]' should exist for driver */
  43/* interoperability.                                            */
  44/* The media type is usually passed in 'options[]'.             */
  45#define MAX_UNITS 8             /* More are supported, limit only on options */
  46static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
  47static int full_duplex[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
  48
  49/* Operational parameters that are set at compile time.                 */
  50/* Keep the ring sizes a power of two for compile efficiency.           */
  51/* The compiler will convert <unsigned>'%'<2^N> into a bit mask.        */
  52/* Making the Tx ring too large decreases the effectiveness of channel  */
  53/* bonding and packet priority.                                         */
  54/* There are no ill effects from too-large receive rings.               */
  55// 88-12-9 modify,
  56// #define TX_RING_SIZE    16
  57// #define RX_RING_SIZE    32
  58#define TX_RING_SIZE    6
  59#define RX_RING_SIZE    12
  60#define TX_TOTAL_SIZE   TX_RING_SIZE*sizeof(struct fealnx_desc)
  61#define RX_TOTAL_SIZE   RX_RING_SIZE*sizeof(struct fealnx_desc)
  62
  63/* Operational parameters that usually are not changed. */
  64/* Time in jiffies before concluding the transmitter is hung. */
  65#define TX_TIMEOUT      (2*HZ)
  66
  67#define PKT_BUF_SZ      1536    /* Size of each temporary Rx buffer. */
  68
  69
  70/* Include files, designed to support most kernel versions 2.0.0 and later. */
  71#include <linux/module.h>
  72#include <linux/kernel.h>
  73#include <linux/string.h>
  74#include <linux/timer.h>
  75#include <linux/errno.h>
  76#include <linux/ioport.h>
  77#include <linux/interrupt.h>
  78#include <linux/pci.h>
  79#include <linux/netdevice.h>
  80#include <linux/etherdevice.h>
  81#include <linux/skbuff.h>
  82#include <linux/init.h>
  83#include <linux/mii.h>
  84#include <linux/ethtool.h>
  85#include <linux/crc32.h>
  86#include <linux/delay.h>
  87#include <linux/bitops.h>
  88
  89#include <asm/processor.h>      /* Processor type for cache alignment. */
  90#include <asm/io.h>
  91#include <asm/uaccess.h>
  92#include <asm/byteorder.h>
  93
  94/* These identify the driver base version and may not be removed. */
  95static const char version[] =
  96        KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE "\n";
  97
  98
  99/* This driver was written to use PCI memory space, however some x86 systems
 100   work only with I/O space accesses. */
 101#ifndef __alpha__
 102#define USE_IO_OPS
 103#endif
 104
 105/* Kernel compatibility defines, some common to David Hinds' PCMCIA package. */
 106/* This is only in the support-all-kernels source code. */
 107
 108#define RUN_AT(x) (jiffies + (x))
 109
 110MODULE_AUTHOR("Myson or whoever");
 111MODULE_DESCRIPTION("Myson MTD-8xx 100/10M Ethernet PCI Adapter Driver");
 112MODULE_LICENSE("GPL");
 113module_param(max_interrupt_work, int, 0);
 114module_param(debug, int, 0);
 115module_param(rx_copybreak, int, 0);
 116module_param(multicast_filter_limit, int, 0);
 117module_param_array(options, int, NULL, 0);
 118module_param_array(full_duplex, int, NULL, 0);
 119MODULE_PARM_DESC(max_interrupt_work, "fealnx maximum events handled per interrupt");
 120MODULE_PARM_DESC(debug, "fealnx enable debugging (0-1)");
 121MODULE_PARM_DESC(rx_copybreak, "fealnx copy breakpoint for copy-only-tiny-frames");
 122MODULE_PARM_DESC(multicast_filter_limit, "fealnx maximum number of filtered multicast addresses");
 123MODULE_PARM_DESC(options, "fealnx: Bits 0-3: media type, bit 17: full duplex");
 124MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)");
 125
 126enum {
 127        MIN_REGION_SIZE         = 136,
 128};
 129
 130/* A chip capabilities table, matching the entries in pci_tbl[] above. */
 131enum chip_capability_flags {
 132        HAS_MII_XCVR,
 133        HAS_CHIP_XCVR,
 134};
 135
 136/* 89/6/13 add, */
 137/* for different PHY */
 138enum phy_type_flags {
 139        MysonPHY = 1,
 140        AhdocPHY = 2,
 141        SeeqPHY = 3,
 142        MarvellPHY = 4,
 143        Myson981 = 5,
 144        LevelOnePHY = 6,
 145        OtherPHY = 10,
 146};
 147
 148struct chip_info {
 149        char *chip_name;
 150        int flags;
 151};
 152
 153static const struct chip_info skel_netdrv_tbl[] = {
 154        { "100/10M Ethernet PCI Adapter",       HAS_MII_XCVR },
 155        { "100/10M Ethernet PCI Adapter",       HAS_CHIP_XCVR },
 156        { "1000/100/10M Ethernet PCI Adapter",  HAS_MII_XCVR },
 157};
 158
 159/* Offsets to the Command and Status Registers. */
 160enum fealnx_offsets {
 161        PAR0 = 0x0,             /* physical address 0-3 */
 162        PAR1 = 0x04,            /* physical address 4-5 */
 163        MAR0 = 0x08,            /* multicast address 0-3 */
 164        MAR1 = 0x0C,            /* multicast address 4-7 */
 165        FAR0 = 0x10,            /* flow-control address 0-3 */
 166        FAR1 = 0x14,            /* flow-control address 4-5 */
 167        TCRRCR = 0x18,          /* receive & transmit configuration */
 168        BCR = 0x1C,             /* bus command */
 169        TXPDR = 0x20,           /* transmit polling demand */
 170        RXPDR = 0x24,           /* receive polling demand */
 171        RXCWP = 0x28,           /* receive current word pointer */
 172        TXLBA = 0x2C,           /* transmit list base address */
 173        RXLBA = 0x30,           /* receive list base address */
 174        ISR = 0x34,             /* interrupt status */
 175        IMR = 0x38,             /* interrupt mask */
 176        FTH = 0x3C,             /* flow control high/low threshold */
 177        MANAGEMENT = 0x40,      /* bootrom/eeprom and mii management */
 178        TALLY = 0x44,           /* tally counters for crc and mpa */
 179        TSR = 0x48,             /* tally counter for transmit status */
 180        BMCRSR = 0x4c,          /* basic mode control and status */
 181        PHYIDENTIFIER = 0x50,   /* phy identifier */
 182        ANARANLPAR = 0x54,      /* auto-negotiation advertisement and link
 183                                   partner ability */
 184        ANEROCR = 0x58,         /* auto-negotiation expansion and pci conf. */
 185        BPREMRPSR = 0x5c,       /* bypass & receive error mask and phy status */
 186};
 187
 188/* Bits in the interrupt status/enable registers. */
 189/* The bits in the Intr Status/Enable registers, mostly interrupt sources. */
 190enum intr_status_bits {
 191        RFCON = 0x00020000,     /* receive flow control xon packet */
 192        RFCOFF = 0x00010000,    /* receive flow control xoff packet */
 193        LSCStatus = 0x00008000, /* link status change */
 194        ANCStatus = 0x00004000, /* autonegotiation completed */
 195        FBE = 0x00002000,       /* fatal bus error */
 196        FBEMask = 0x00001800,   /* mask bit12-11 */
 197        ParityErr = 0x00000000, /* parity error */
 198        TargetErr = 0x00001000, /* target abort */
 199        MasterErr = 0x00000800, /* master error */
 200        TUNF = 0x00000400,      /* transmit underflow */
 201        ROVF = 0x00000200,      /* receive overflow */
 202        ETI = 0x00000100,       /* transmit early int */
 203        ERI = 0x00000080,       /* receive early int */
 204        CNTOVF = 0x00000040,    /* counter overflow */
 205        RBU = 0x00000020,       /* receive buffer unavailable */
 206        TBU = 0x00000010,       /* transmit buffer unavilable */
 207        TI = 0x00000008,        /* transmit interrupt */
 208        RI = 0x00000004,        /* receive interrupt */
 209        RxErr = 0x00000002,     /* receive error */
 210};
 211
 212/* Bits in the NetworkConfig register, W for writing, R for reading */
 213/* FIXME: some names are invented by me. Marked with (name?) */
 214/* If you have docs and know bit names, please fix 'em */
 215enum rx_mode_bits {
 216        CR_W_ENH        = 0x02000000,   /* enhanced mode (name?) */
 217        CR_W_FD         = 0x00100000,   /* full duplex */
 218        CR_W_PS10       = 0x00080000,   /* 10 mbit */
 219        CR_W_TXEN       = 0x00040000,   /* tx enable (name?) */
 220        CR_W_PS1000     = 0x00010000,   /* 1000 mbit */
 221     /* CR_W_RXBURSTMASK= 0x00000e00, Im unsure about this */
 222        CR_W_RXMODEMASK = 0x000000e0,
 223        CR_W_PROM       = 0x00000080,   /* promiscuous mode */
 224        CR_W_AB         = 0x00000040,   /* accept broadcast */
 225        CR_W_AM         = 0x00000020,   /* accept mutlicast */
 226        CR_W_ARP        = 0x00000008,   /* receive runt pkt */
 227        CR_W_ALP        = 0x00000004,   /* receive long pkt */
 228        CR_W_SEP        = 0x00000002,   /* receive error pkt */
 229        CR_W_RXEN       = 0x00000001,   /* rx enable (unicast?) (name?) */
 230
 231        CR_R_TXSTOP     = 0x04000000,   /* tx stopped (name?) */
 232        CR_R_FD         = 0x00100000,   /* full duplex detected */
 233        CR_R_PS10       = 0x00080000,   /* 10 mbit detected */
 234        CR_R_RXSTOP     = 0x00008000,   /* rx stopped (name?) */
 235};
 236
 237/* The Tulip Rx and Tx buffer descriptors. */
 238struct fealnx_desc {
 239        s32 status;
 240        s32 control;
 241        u32 buffer;
 242        u32 next_desc;
 243        struct fealnx_desc *next_desc_logical;
 244        struct sk_buff *skbuff;
 245        u32 reserved1;
 246        u32 reserved2;
 247};
 248
 249/* Bits in network_desc.status */
 250enum rx_desc_status_bits {
 251        RXOWN = 0x80000000,     /* own bit */
 252        FLNGMASK = 0x0fff0000,  /* frame length */
 253        FLNGShift = 16,
 254        MARSTATUS = 0x00004000, /* multicast address received */
 255        BARSTATUS = 0x00002000, /* broadcast address received */
 256        PHYSTATUS = 0x00001000, /* physical address received */
 257        RXFSD = 0x00000800,     /* first descriptor */
 258        RXLSD = 0x00000400,     /* last descriptor */
 259        ErrorSummary = 0x80,    /* error summary */
 260        RUNT = 0x40,            /* runt packet received */
 261        LONG = 0x20,            /* long packet received */
 262        FAE = 0x10,             /* frame align error */
 263        CRC = 0x08,             /* crc error */
 264        RXER = 0x04,            /* receive error */
 265};
 266
 267enum rx_desc_control_bits {
 268        RXIC = 0x00800000,      /* interrupt control */
 269        RBSShift = 0,
 270};
 271
 272enum tx_desc_status_bits {
 273        TXOWN = 0x80000000,     /* own bit */
 274        JABTO = 0x00004000,     /* jabber timeout */
 275        CSL = 0x00002000,       /* carrier sense lost */
 276        LC = 0x00001000,        /* late collision */
 277        EC = 0x00000800,        /* excessive collision */
 278        UDF = 0x00000400,       /* fifo underflow */
 279        DFR = 0x00000200,       /* deferred */
 280        HF = 0x00000100,        /* heartbeat fail */
 281        NCRMask = 0x000000ff,   /* collision retry count */
 282        NCRShift = 0,
 283};
 284
 285enum tx_desc_control_bits {
 286        TXIC = 0x80000000,      /* interrupt control */
 287        ETIControl = 0x40000000,        /* early transmit interrupt */
 288        TXLD = 0x20000000,      /* last descriptor */
 289        TXFD = 0x10000000,      /* first descriptor */
 290        CRCEnable = 0x08000000, /* crc control */
 291        PADEnable = 0x04000000, /* padding control */
 292        RetryTxLC = 0x02000000, /* retry late collision */
 293        PKTSMask = 0x3ff800,    /* packet size bit21-11 */
 294        PKTSShift = 11,
 295        TBSMask = 0x000007ff,   /* transmit buffer bit 10-0 */
 296        TBSShift = 0,
 297};
 298
 299/* BootROM/EEPROM/MII Management Register */
 300#define MASK_MIIR_MII_READ       0x00000000
 301#define MASK_MIIR_MII_WRITE      0x00000008
 302#define MASK_MIIR_MII_MDO        0x00000004
 303#define MASK_MIIR_MII_MDI        0x00000002
 304#define MASK_MIIR_MII_MDC        0x00000001
 305
 306/* ST+OP+PHYAD+REGAD+TA */
 307#define OP_READ             0x6000      /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */
 308#define OP_WRITE            0x5002      /* ST:01+OP:01+PHYAD+REGAD+TA:10 */
 309
 310/* ------------------------------------------------------------------------- */
 311/*      Constants for Myson PHY                                              */
 312/* ------------------------------------------------------------------------- */
 313#define MysonPHYID      0xd0000302
 314/* 89-7-27 add, (begin) */
 315#define MysonPHYID0     0x0302
 316#define StatusRegister  18
 317#define SPEED100        0x0400  // bit10
 318#define FULLMODE        0x0800  // bit11
 319/* 89-7-27 add, (end) */
 320
 321/* ------------------------------------------------------------------------- */
 322/*      Constants for Seeq 80225 PHY                                         */
 323/* ------------------------------------------------------------------------- */
 324#define SeeqPHYID0      0x0016
 325
 326#define MIIRegister18   18
 327#define SPD_DET_100     0x80
 328#define DPLX_DET_FULL   0x40
 329
 330/* ------------------------------------------------------------------------- */
 331/*      Constants for Ahdoc 101 PHY                                          */
 332/* ------------------------------------------------------------------------- */
 333#define AhdocPHYID0     0x0022
 334
 335#define DiagnosticReg   18
 336#define DPLX_FULL       0x0800
 337#define Speed_100       0x0400
 338
 339/* 89/6/13 add, */
 340/* -------------------------------------------------------------------------- */
 341/*      Constants                                                             */
 342/* -------------------------------------------------------------------------- */
 343#define MarvellPHYID0           0x0141
 344#define LevelOnePHYID0          0x0013
 345
 346#define MII1000BaseTControlReg  9
 347#define MII1000BaseTStatusReg   10
 348#define SpecificReg             17
 349
 350/* for 1000BaseT Control Register */
 351#define PHYAbletoPerform1000FullDuplex  0x0200
 352#define PHYAbletoPerform1000HalfDuplex  0x0100
 353#define PHY1000AbilityMask              0x300
 354
 355// for phy specific status register, marvell phy.
 356#define SpeedMask       0x0c000
 357#define Speed_1000M     0x08000
 358#define Speed_100M      0x4000
 359#define Speed_10M       0
 360#define Full_Duplex     0x2000
 361
 362// 89/12/29 add, for phy specific status register, levelone phy, (begin)
 363#define LXT1000_100M    0x08000
 364#define LXT1000_1000M   0x0c000
 365#define LXT1000_Full    0x200
 366// 89/12/29 add, for phy specific status register, levelone phy, (end)
 367
 368/* for 3-in-1 case, BMCRSR register */
 369#define LinkIsUp2       0x00040000
 370
 371/* for PHY */
 372#define LinkIsUp        0x0004
 373
 374
 375struct netdev_private {
 376        /* Descriptor rings first for alignment. */
 377        struct fealnx_desc *rx_ring;
 378        struct fealnx_desc *tx_ring;
 379
 380        dma_addr_t rx_ring_dma;
 381        dma_addr_t tx_ring_dma;
 382
 383        spinlock_t lock;
 384
 385        /* Media monitoring timer. */
 386        struct timer_list timer;
 387
 388        /* Reset timer */
 389        struct timer_list reset_timer;
 390        int reset_timer_armed;
 391        unsigned long crvalue_sv;
 392        unsigned long imrvalue_sv;
 393
 394        /* Frequently used values: keep some adjacent for cache effect. */
 395        int flags;
 396        struct pci_dev *pci_dev;
 397        unsigned long crvalue;
 398        unsigned long bcrvalue;
 399        unsigned long imrvalue;
 400        struct fealnx_desc *cur_rx;
 401        struct fealnx_desc *lack_rxbuf;
 402        int really_rx_count;
 403        struct fealnx_desc *cur_tx;
 404        struct fealnx_desc *cur_tx_copy;
 405        int really_tx_count;
 406        int free_tx_count;
 407        unsigned int rx_buf_sz; /* Based on MTU+slack. */
 408
 409        /* These values are keep track of the transceiver/media in use. */
 410        unsigned int linkok;
 411        unsigned int line_speed;
 412        unsigned int duplexmode;
 413        unsigned int default_port:4;    /* Last dev->if_port value. */
 414        unsigned int PHYType;
 415
 416        /* MII transceiver section. */
 417        int mii_cnt;            /* MII device addresses. */
 418        unsigned char phys[2];  /* MII device addresses. */
 419        struct mii_if_info mii;
 420        void __iomem *mem;
 421};
 422
 423
 424static int mdio_read(struct net_device *dev, int phy_id, int location);
 425static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
 426static int netdev_open(struct net_device *dev);
 427static void getlinktype(struct net_device *dev);
 428static void getlinkstatus(struct net_device *dev);
 429static void netdev_timer(unsigned long data);
 430static void reset_timer(unsigned long data);
 431static void fealnx_tx_timeout(struct net_device *dev);
 432static void init_ring(struct net_device *dev);
 433static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
 434static irqreturn_t intr_handler(int irq, void *dev_instance);
 435static int netdev_rx(struct net_device *dev);
 436static void set_rx_mode(struct net_device *dev);
 437static void __set_rx_mode(struct net_device *dev);
 438static struct net_device_stats *get_stats(struct net_device *dev);
 439static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 440static const struct ethtool_ops netdev_ethtool_ops;
 441static int netdev_close(struct net_device *dev);
 442static void reset_rx_descriptors(struct net_device *dev);
 443static void reset_tx_descriptors(struct net_device *dev);
 444
 445static void stop_nic_rx(void __iomem *ioaddr, long crvalue)
 446{
 447        int delay = 0x1000;
 448        iowrite32(crvalue & ~(CR_W_RXEN), ioaddr + TCRRCR);
 449        while (--delay) {
 450                if ( (ioread32(ioaddr + TCRRCR) & CR_R_RXSTOP) == CR_R_RXSTOP)
 451                        break;
 452        }
 453}
 454
 455
 456static void stop_nic_rxtx(void __iomem *ioaddr, long crvalue)
 457{
 458        int delay = 0x1000;
 459        iowrite32(crvalue & ~(CR_W_RXEN+CR_W_TXEN), ioaddr + TCRRCR);
 460        while (--delay) {
 461                if ( (ioread32(ioaddr + TCRRCR) & (CR_R_RXSTOP+CR_R_TXSTOP))
 462                                            == (CR_R_RXSTOP+CR_R_TXSTOP) )
 463                        break;
 464        }
 465}
 466
 467static const struct net_device_ops netdev_ops = {
 468        .ndo_open               = netdev_open,
 469        .ndo_stop               = netdev_close,
 470        .ndo_start_xmit         = start_tx,
 471        .ndo_get_stats          = get_stats,
 472        .ndo_set_rx_mode        = set_rx_mode,
 473        .ndo_do_ioctl           = mii_ioctl,
 474        .ndo_tx_timeout         = fealnx_tx_timeout,
 475        .ndo_change_mtu         = eth_change_mtu,
 476        .ndo_set_mac_address    = eth_mac_addr,
 477        .ndo_validate_addr      = eth_validate_addr,
 478};
 479
 480static int fealnx_init_one(struct pci_dev *pdev,
 481                           const struct pci_device_id *ent)
 482{
 483        struct netdev_private *np;
 484        int i, option, err, irq;
 485        static int card_idx = -1;
 486        char boardname[12];
 487        void __iomem *ioaddr;
 488        unsigned long len;
 489        unsigned int chip_id = ent->driver_data;
 490        struct net_device *dev;
 491        void *ring_space;
 492        dma_addr_t ring_dma;
 493#ifdef USE_IO_OPS
 494        int bar = 0;
 495#else
 496        int bar = 1;
 497#endif
 498
 499/* when built into the kernel, we only print version if device is found */
 500#ifndef MODULE
 501        static int printed_version;
 502        if (!printed_version++)
 503                printk(version);
 504#endif
 505
 506        card_idx++;
 507        sprintf(boardname, "fealnx%d", card_idx);
 508
 509        option = card_idx < MAX_UNITS ? options[card_idx] : 0;
 510
 511        i = pci_enable_device(pdev);
 512        if (i) return i;
 513        pci_set_master(pdev);
 514
 515        len = pci_resource_len(pdev, bar);
 516        if (len < MIN_REGION_SIZE) {
 517                dev_err(&pdev->dev,
 518                           "region size %ld too small, aborting\n", len);
 519                return -ENODEV;
 520        }
 521
 522        i = pci_request_regions(pdev, boardname);
 523        if (i)
 524                return i;
 525
 526        irq = pdev->irq;
 527
 528        ioaddr = pci_iomap(pdev, bar, len);
 529        if (!ioaddr) {
 530                err = -ENOMEM;
 531                goto err_out_res;
 532        }
 533
 534        dev = alloc_etherdev(sizeof(struct netdev_private));
 535        if (!dev) {
 536                err = -ENOMEM;
 537                goto err_out_unmap;
 538        }
 539        SET_NETDEV_DEV(dev, &pdev->dev);
 540
 541        /* read ethernet id */
 542        for (i = 0; i < 6; ++i)
 543                dev->dev_addr[i] = ioread8(ioaddr + PAR0 + i);
 544
 545        /* Reset the chip to erase previous misconfiguration. */
 546        iowrite32(0x00000001, ioaddr + BCR);
 547
 548        /* Make certain the descriptor lists are aligned. */
 549        np = netdev_priv(dev);
 550        np->mem = ioaddr;
 551        spin_lock_init(&np->lock);
 552        np->pci_dev = pdev;
 553        np->flags = skel_netdrv_tbl[chip_id].flags;
 554        pci_set_drvdata(pdev, dev);
 555        np->mii.dev = dev;
 556        np->mii.mdio_read = mdio_read;
 557        np->mii.mdio_write = mdio_write;
 558        np->mii.phy_id_mask = 0x1f;
 559        np->mii.reg_num_mask = 0x1f;
 560
 561        ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
 562        if (!ring_space) {
 563                err = -ENOMEM;
 564                goto err_out_free_dev;
 565        }
 566        np->rx_ring = ring_space;
 567        np->rx_ring_dma = ring_dma;
 568
 569        ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
 570        if (!ring_space) {
 571                err = -ENOMEM;
 572                goto err_out_free_rx;
 573        }
 574        np->tx_ring = ring_space;
 575        np->tx_ring_dma = ring_dma;
 576
 577        /* find the connected MII xcvrs */
 578        if (np->flags == HAS_MII_XCVR) {
 579                int phy, phy_idx = 0;
 580
 581                for (phy = 1; phy < 32 && phy_idx < ARRAY_SIZE(np->phys);
 582                               phy++) {
 583                        int mii_status = mdio_read(dev, phy, 1);
 584
 585                        if (mii_status != 0xffff && mii_status != 0x0000) {
 586                                np->phys[phy_idx++] = phy;
 587                                dev_info(&pdev->dev,
 588                                       "MII PHY found at address %d, status "
 589                                       "0x%4.4x.\n", phy, mii_status);
 590                                /* get phy type */
 591                                {
 592                                        unsigned int data;
 593
 594                                        data = mdio_read(dev, np->phys[0], 2);
 595                                        if (data == SeeqPHYID0)
 596                                                np->PHYType = SeeqPHY;
 597                                        else if (data == AhdocPHYID0)
 598                                                np->PHYType = AhdocPHY;
 599                                        else if (data == MarvellPHYID0)
 600                                                np->PHYType = MarvellPHY;
 601                                        else if (data == MysonPHYID0)
 602                                                np->PHYType = Myson981;
 603                                        else if (data == LevelOnePHYID0)
 604                                                np->PHYType = LevelOnePHY;
 605                                        else
 606                                                np->PHYType = OtherPHY;
 607                                }
 608                        }
 609                }
 610
 611                np->mii_cnt = phy_idx;
 612                if (phy_idx == 0)
 613                        dev_warn(&pdev->dev,
 614                                "MII PHY not found -- this device may "
 615                               "not operate correctly.\n");
 616        } else {
 617                np->phys[0] = 32;
 618/* 89/6/23 add, (begin) */
 619                /* get phy type */
 620                if (ioread32(ioaddr + PHYIDENTIFIER) == MysonPHYID)
 621                        np->PHYType = MysonPHY;
 622                else
 623                        np->PHYType = OtherPHY;
 624        }
 625        np->mii.phy_id = np->phys[0];
 626
 627        if (dev->mem_start)
 628                option = dev->mem_start;
 629
 630        /* The lower four bits are the media type. */
 631        if (option > 0) {
 632                if (option & 0x200)
 633                        np->mii.full_duplex = 1;
 634                np->default_port = option & 15;
 635        }
 636
 637        if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
 638                np->mii.full_duplex = full_duplex[card_idx];
 639
 640        if (np->mii.full_duplex) {
 641                dev_info(&pdev->dev, "Media type forced to Full Duplex.\n");
 642/* 89/6/13 add, (begin) */
 643//      if (np->PHYType==MarvellPHY)
 644                if ((np->PHYType == MarvellPHY) || (np->PHYType == LevelOnePHY)) {
 645                        unsigned int data;
 646
 647                        data = mdio_read(dev, np->phys[0], 9);
 648                        data = (data & 0xfcff) | 0x0200;
 649                        mdio_write(dev, np->phys[0], 9, data);
 650                }
 651/* 89/6/13 add, (end) */
 652                if (np->flags == HAS_MII_XCVR)
 653                        mdio_write(dev, np->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
 654                else
 655                        iowrite32(ADVERTISE_FULL, ioaddr + ANARANLPAR);
 656                np->mii.force_media = 1;
 657        }
 658
 659        dev->netdev_ops = &netdev_ops;
 660        dev->ethtool_ops = &netdev_ethtool_ops;
 661        dev->watchdog_timeo = TX_TIMEOUT;
 662
 663        err = register_netdev(dev);
 664        if (err)
 665                goto err_out_free_tx;
 666
 667        printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
 668               dev->name, skel_netdrv_tbl[chip_id].chip_name, ioaddr,
 669               dev->dev_addr, irq);
 670
 671        return 0;
 672
 673err_out_free_tx:
 674        pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
 675err_out_free_rx:
 676        pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
 677err_out_free_dev:
 678        free_netdev(dev);
 679err_out_unmap:
 680        pci_iounmap(pdev, ioaddr);
 681err_out_res:
 682        pci_release_regions(pdev);
 683        return err;
 684}
 685
 686
 687static void fealnx_remove_one(struct pci_dev *pdev)
 688{
 689        struct net_device *dev = pci_get_drvdata(pdev);
 690
 691        if (dev) {
 692                struct netdev_private *np = netdev_priv(dev);
 693
 694                pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
 695                        np->tx_ring_dma);
 696                pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
 697                        np->rx_ring_dma);
 698                unregister_netdev(dev);
 699                pci_iounmap(pdev, np->mem);
 700                free_netdev(dev);
 701                pci_release_regions(pdev);
 702        } else
 703                printk(KERN_ERR "fealnx: remove for unknown device\n");
 704}
 705
 706
 707static ulong m80x_send_cmd_to_phy(void __iomem *miiport, int opcode, int phyad, int regad)
 708{
 709        ulong miir;
 710        int i;
 711        unsigned int mask, data;
 712
 713        /* enable MII output */
 714        miir = (ulong) ioread32(miiport);
 715        miir &= 0xfffffff0;
 716
 717        miir |= MASK_MIIR_MII_WRITE + MASK_MIIR_MII_MDO;
 718
 719        /* send 32 1's preamble */
 720        for (i = 0; i < 32; i++) {
 721                /* low MDC; MDO is already high (miir) */
 722                miir &= ~MASK_MIIR_MII_MDC;
 723                iowrite32(miir, miiport);
 724
 725                /* high MDC */
 726                miir |= MASK_MIIR_MII_MDC;
 727                iowrite32(miir, miiport);
 728        }
 729
 730        /* calculate ST+OP+PHYAD+REGAD+TA */
 731        data = opcode | (phyad << 7) | (regad << 2);
 732
 733        /* sent out */
 734        mask = 0x8000;
 735        while (mask) {
 736                /* low MDC, prepare MDO */
 737                miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
 738                if (mask & data)
 739                        miir |= MASK_MIIR_MII_MDO;
 740
 741                iowrite32(miir, miiport);
 742                /* high MDC */
 743                miir |= MASK_MIIR_MII_MDC;
 744                iowrite32(miir, miiport);
 745                udelay(30);
 746
 747                /* next */
 748                mask >>= 1;
 749                if (mask == 0x2 && opcode == OP_READ)
 750                        miir &= ~MASK_MIIR_MII_WRITE;
 751        }
 752        return miir;
 753}
 754
 755
 756static int mdio_read(struct net_device *dev, int phyad, int regad)
 757{
 758        struct netdev_private *np = netdev_priv(dev);
 759        void __iomem *miiport = np->mem + MANAGEMENT;
 760        ulong miir;
 761        unsigned int mask, data;
 762
 763        miir = m80x_send_cmd_to_phy(miiport, OP_READ, phyad, regad);
 764
 765        /* read data */
 766        mask = 0x8000;
 767        data = 0;
 768        while (mask) {
 769                /* low MDC */
 770                miir &= ~MASK_MIIR_MII_MDC;
 771                iowrite32(miir, miiport);
 772
 773                /* read MDI */
 774                miir = ioread32(miiport);
 775                if (miir & MASK_MIIR_MII_MDI)
 776                        data |= mask;
 777
 778                /* high MDC, and wait */
 779                miir |= MASK_MIIR_MII_MDC;
 780                iowrite32(miir, miiport);
 781                udelay(30);
 782
 783                /* next */
 784                mask >>= 1;
 785        }
 786
 787        /* low MDC */
 788        miir &= ~MASK_MIIR_MII_MDC;
 789        iowrite32(miir, miiport);
 790
 791        return data & 0xffff;
 792}
 793
 794
 795static void mdio_write(struct net_device *dev, int phyad, int regad, int data)
 796{
 797        struct netdev_private *np = netdev_priv(dev);
 798        void __iomem *miiport = np->mem + MANAGEMENT;
 799        ulong miir;
 800        unsigned int mask;
 801
 802        miir = m80x_send_cmd_to_phy(miiport, OP_WRITE, phyad, regad);
 803
 804        /* write data */
 805        mask = 0x8000;
 806        while (mask) {
 807                /* low MDC, prepare MDO */
 808                miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
 809                if (mask & data)
 810                        miir |= MASK_MIIR_MII_MDO;
 811                iowrite32(miir, miiport);
 812
 813                /* high MDC */
 814                miir |= MASK_MIIR_MII_MDC;
 815                iowrite32(miir, miiport);
 816
 817                /* next */
 818                mask >>= 1;
 819        }
 820
 821        /* low MDC */
 822        miir &= ~MASK_MIIR_MII_MDC;
 823        iowrite32(miir, miiport);
 824}
 825
 826
 827static int netdev_open(struct net_device *dev)
 828{
 829        struct netdev_private *np = netdev_priv(dev);
 830        void __iomem *ioaddr = np->mem;
 831        const int irq = np->pci_dev->irq;
 832        int rc, i;
 833
 834        iowrite32(0x00000001, ioaddr + BCR);    /* Reset */
 835
 836        rc = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev);
 837        if (rc)
 838                return -EAGAIN;
 839
 840        for (i = 0; i < 3; i++)
 841                iowrite16(((unsigned short*)dev->dev_addr)[i],
 842                                ioaddr + PAR0 + i*2);
 843
 844        init_ring(dev);
 845
 846        iowrite32(np->rx_ring_dma, ioaddr + RXLBA);
 847        iowrite32(np->tx_ring_dma, ioaddr + TXLBA);
 848
 849        /* Initialize other registers. */
 850        /* Configure the PCI bus bursts and FIFO thresholds.
 851           486: Set 8 longword burst.
 852           586: no burst limit.
 853           Burst length 5:3
 854           0 0 0   1
 855           0 0 1   4
 856           0 1 0   8
 857           0 1 1   16
 858           1 0 0   32
 859           1 0 1   64
 860           1 1 0   128
 861           1 1 1   256
 862           Wait the specified 50 PCI cycles after a reset by initializing
 863           Tx and Rx queues and the address filter list.
 864           FIXME (Ueimor): optimistic for alpha + posted writes ? */
 865
 866        np->bcrvalue = 0x10;    /* little-endian, 8 burst length */
 867#ifdef __BIG_ENDIAN
 868        np->bcrvalue |= 0x04;   /* big-endian */
 869#endif
 870
 871#if defined(__i386__) && !defined(MODULE)
 872        if (boot_cpu_data.x86 <= 4)
 873                np->crvalue = 0xa00;
 874        else
 875#endif
 876                np->crvalue = 0xe00;    /* rx 128 burst length */
 877
 878
 879// 89/12/29 add,
 880// 90/1/16 modify,
 881//   np->imrvalue=FBE|TUNF|CNTOVF|RBU|TI|RI;
 882        np->imrvalue = TUNF | CNTOVF | RBU | TI | RI;
 883        if (np->pci_dev->device == 0x891) {
 884                np->bcrvalue |= 0x200;  /* set PROG bit */
 885                np->crvalue |= CR_W_ENH;        /* set enhanced bit */
 886                np->imrvalue |= ETI;
 887        }
 888        iowrite32(np->bcrvalue, ioaddr + BCR);
 889
 890        if (dev->if_port == 0)
 891                dev->if_port = np->default_port;
 892
 893        iowrite32(0, ioaddr + RXPDR);
 894// 89/9/1 modify,
 895//   np->crvalue = 0x00e40001;    /* tx store and forward, tx/rx enable */
 896        np->crvalue |= 0x00e40001;      /* tx store and forward, tx/rx enable */
 897        np->mii.full_duplex = np->mii.force_media;
 898        getlinkstatus(dev);
 899        if (np->linkok)
 900                getlinktype(dev);
 901        __set_rx_mode(dev);
 902
 903        netif_start_queue(dev);
 904
 905        /* Clear and Enable interrupts by setting the interrupt mask. */
 906        iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
 907        iowrite32(np->imrvalue, ioaddr + IMR);
 908
 909        if (debug)
 910                printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name);
 911
 912        /* Set the timer to check for link beat. */
 913        init_timer(&np->timer);
 914        np->timer.expires = RUN_AT(3 * HZ);
 915        np->timer.data = (unsigned long) dev;
 916        np->timer.function = netdev_timer;
 917
 918        /* timer handler */
 919        add_timer(&np->timer);
 920
 921        init_timer(&np->reset_timer);
 922        np->reset_timer.data = (unsigned long) dev;
 923        np->reset_timer.function = reset_timer;
 924        np->reset_timer_armed = 0;
 925        return rc;
 926}
 927
 928
 929static void getlinkstatus(struct net_device *dev)
 930/* function: Routine will read MII Status Register to get link status.       */
 931/* input   : dev... pointer to the adapter block.                            */
 932/* output  : none.                                                           */
 933{
 934        struct netdev_private *np = netdev_priv(dev);
 935        unsigned int i, DelayTime = 0x1000;
 936
 937        np->linkok = 0;
 938
 939        if (np->PHYType == MysonPHY) {
 940                for (i = 0; i < DelayTime; ++i) {
 941                        if (ioread32(np->mem + BMCRSR) & LinkIsUp2) {
 942                                np->linkok = 1;
 943                                return;
 944                        }
 945                        udelay(100);
 946                }
 947        } else {
 948                for (i = 0; i < DelayTime; ++i) {
 949                        if (mdio_read(dev, np->phys[0], MII_BMSR) & BMSR_LSTATUS) {
 950                                np->linkok = 1;
 951                                return;
 952                        }
 953                        udelay(100);
 954                }
 955        }
 956}
 957
 958
 959static void getlinktype(struct net_device *dev)
 960{
 961        struct netdev_private *np = netdev_priv(dev);
 962
 963        if (np->PHYType == MysonPHY) {  /* 3-in-1 case */
 964                if (ioread32(np->mem + TCRRCR) & CR_R_FD)
 965                        np->duplexmode = 2;     /* full duplex */
 966                else
 967                        np->duplexmode = 1;     /* half duplex */
 968                if (ioread32(np->mem + TCRRCR) & CR_R_PS10)
 969                        np->line_speed = 1;     /* 10M */
 970                else
 971                        np->line_speed = 2;     /* 100M */
 972        } else {
 973                if (np->PHYType == SeeqPHY) {   /* this PHY is SEEQ 80225 */
 974                        unsigned int data;
 975
 976                        data = mdio_read(dev, np->phys[0], MIIRegister18);
 977                        if (data & SPD_DET_100)
 978                                np->line_speed = 2;     /* 100M */
 979                        else
 980                                np->line_speed = 1;     /* 10M */
 981                        if (data & DPLX_DET_FULL)
 982                                np->duplexmode = 2;     /* full duplex mode */
 983                        else
 984                                np->duplexmode = 1;     /* half duplex mode */
 985                } else if (np->PHYType == AhdocPHY) {
 986                        unsigned int data;
 987
 988                        data = mdio_read(dev, np->phys[0], DiagnosticReg);
 989                        if (data & Speed_100)
 990                                np->line_speed = 2;     /* 100M */
 991                        else
 992                                np->line_speed = 1;     /* 10M */
 993                        if (data & DPLX_FULL)
 994                                np->duplexmode = 2;     /* full duplex mode */
 995                        else
 996                                np->duplexmode = 1;     /* half duplex mode */
 997                }
 998/* 89/6/13 add, (begin) */
 999                else if (np->PHYType == MarvellPHY) {
1000                        unsigned int data;
1001
1002                        data = mdio_read(dev, np->phys[0], SpecificReg);
1003                        if (data & Full_Duplex)
1004                                np->duplexmode = 2;     /* full duplex mode */
1005                        else
1006                                np->duplexmode = 1;     /* half duplex mode */
1007                        data &= SpeedMask;
1008                        if (data == Speed_1000M)
1009                                np->line_speed = 3;     /* 1000M */
1010                        else if (data == Speed_100M)
1011                                np->line_speed = 2;     /* 100M */
1012                        else
1013                                np->line_speed = 1;     /* 10M */
1014                }
1015/* 89/6/13 add, (end) */
1016/* 89/7/27 add, (begin) */
1017                else if (np->PHYType == Myson981) {
1018                        unsigned int data;
1019
1020                        data = mdio_read(dev, np->phys[0], StatusRegister);
1021
1022                        if (data & SPEED100)
1023                                np->line_speed = 2;
1024                        else
1025                                np->line_speed = 1;
1026
1027                        if (data & FULLMODE)
1028                                np->duplexmode = 2;
1029                        else
1030                                np->duplexmode = 1;
1031                }
1032/* 89/7/27 add, (end) */
1033/* 89/12/29 add */
1034                else if (np->PHYType == LevelOnePHY) {
1035                        unsigned int data;
1036
1037                        data = mdio_read(dev, np->phys[0], SpecificReg);
1038                        if (data & LXT1000_Full)
1039                                np->duplexmode = 2;     /* full duplex mode */
1040                        else
1041                                np->duplexmode = 1;     /* half duplex mode */
1042                        data &= SpeedMask;
1043                        if (data == LXT1000_1000M)
1044                                np->line_speed = 3;     /* 1000M */
1045                        else if (data == LXT1000_100M)
1046                                np->line_speed = 2;     /* 100M */
1047                        else
1048                                np->line_speed = 1;     /* 10M */
1049                }
1050                np->crvalue &= (~CR_W_PS10) & (~CR_W_FD) & (~CR_W_PS1000);
1051                if (np->line_speed == 1)
1052                        np->crvalue |= CR_W_PS10;
1053                else if (np->line_speed == 3)
1054                        np->crvalue |= CR_W_PS1000;
1055                if (np->duplexmode == 2)
1056                        np->crvalue |= CR_W_FD;
1057        }
1058}
1059
1060
1061/* Take lock before calling this */
1062static void allocate_rx_buffers(struct net_device *dev)
1063{
1064        struct netdev_private *np = netdev_priv(dev);
1065
1066        /*  allocate skb for rx buffers */
1067        while (np->really_rx_count != RX_RING_SIZE) {
1068                struct sk_buff *skb;
1069
1070                skb = netdev_alloc_skb(dev, np->rx_buf_sz);
1071                if (skb == NULL)
1072                        break;  /* Better luck next round. */
1073
1074                while (np->lack_rxbuf->skbuff)
1075                        np->lack_rxbuf = np->lack_rxbuf->next_desc_logical;
1076
1077                np->lack_rxbuf->skbuff = skb;
1078                np->lack_rxbuf->buffer = pci_map_single(np->pci_dev, skb->data,
1079                        np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1080                np->lack_rxbuf->status = RXOWN;
1081                ++np->really_rx_count;
1082        }
1083}
1084
1085
1086static void netdev_timer(unsigned long data)
1087{
1088        struct net_device *dev = (struct net_device *) data;
1089        struct netdev_private *np = netdev_priv(dev);
1090        void __iomem *ioaddr = np->mem;
1091        int old_crvalue = np->crvalue;
1092        unsigned int old_linkok = np->linkok;
1093        unsigned long flags;
1094
1095        if (debug)
1096                printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x "
1097                       "config %8.8x.\n", dev->name, ioread32(ioaddr + ISR),
1098                       ioread32(ioaddr + TCRRCR));
1099
1100        spin_lock_irqsave(&np->lock, flags);
1101
1102        if (np->flags == HAS_MII_XCVR) {
1103                getlinkstatus(dev);
1104                if ((old_linkok == 0) && (np->linkok == 1)) {   /* we need to detect the media type again */
1105                        getlinktype(dev);
1106                        if (np->crvalue != old_crvalue) {
1107                                stop_nic_rxtx(ioaddr, np->crvalue);
1108                                iowrite32(np->crvalue, ioaddr + TCRRCR);
1109                        }
1110                }
1111        }
1112
1113        allocate_rx_buffers(dev);
1114
1115        spin_unlock_irqrestore(&np->lock, flags);
1116
1117        np->timer.expires = RUN_AT(10 * HZ);
1118        add_timer(&np->timer);
1119}
1120
1121
1122/* Take lock before calling */
1123/* Reset chip and disable rx, tx and interrupts */
1124static void reset_and_disable_rxtx(struct net_device *dev)
1125{
1126        struct netdev_private *np = netdev_priv(dev);
1127        void __iomem *ioaddr = np->mem;
1128        int delay=51;
1129
1130        /* Reset the chip's Tx and Rx processes. */
1131        stop_nic_rxtx(ioaddr, 0);
1132
1133        /* Disable interrupts by clearing the interrupt mask. */
1134        iowrite32(0, ioaddr + IMR);
1135
1136        /* Reset the chip to erase previous misconfiguration. */
1137        iowrite32(0x00000001, ioaddr + BCR);
1138
1139        /* Ueimor: wait for 50 PCI cycles (and flush posted writes btw).
1140           We surely wait too long (address+data phase). Who cares? */
1141        while (--delay) {
1142                ioread32(ioaddr + BCR);
1143                rmb();
1144        }
1145}
1146
1147
1148/* Take lock before calling */
1149/* Restore chip after reset */
1150static void enable_rxtx(struct net_device *dev)
1151{
1152        struct netdev_private *np = netdev_priv(dev);
1153        void __iomem *ioaddr = np->mem;
1154
1155        reset_rx_descriptors(dev);
1156
1157        iowrite32(np->tx_ring_dma + ((char*)np->cur_tx - (char*)np->tx_ring),
1158                ioaddr + TXLBA);
1159        iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1160                ioaddr + RXLBA);
1161
1162        iowrite32(np->bcrvalue, ioaddr + BCR);
1163
1164        iowrite32(0, ioaddr + RXPDR);
1165        __set_rx_mode(dev); /* changes np->crvalue, writes it into TCRRCR */
1166
1167        /* Clear and Enable interrupts by setting the interrupt mask. */
1168        iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
1169        iowrite32(np->imrvalue, ioaddr + IMR);
1170
1171        iowrite32(0, ioaddr + TXPDR);
1172}
1173
1174
1175static void reset_timer(unsigned long data)
1176{
1177        struct net_device *dev = (struct net_device *) data;
1178        struct netdev_private *np = netdev_priv(dev);
1179        unsigned long flags;
1180
1181        printk(KERN_WARNING "%s: resetting tx and rx machinery\n", dev->name);
1182
1183        spin_lock_irqsave(&np->lock, flags);
1184        np->crvalue = np->crvalue_sv;
1185        np->imrvalue = np->imrvalue_sv;
1186
1187        reset_and_disable_rxtx(dev);
1188        /* works for me without this:
1189        reset_tx_descriptors(dev); */
1190        enable_rxtx(dev);
1191        netif_start_queue(dev); /* FIXME: or netif_wake_queue(dev); ? */
1192
1193        np->reset_timer_armed = 0;
1194
1195        spin_unlock_irqrestore(&np->lock, flags);
1196}
1197
1198
1199static void fealnx_tx_timeout(struct net_device *dev)
1200{
1201        struct netdev_private *np = netdev_priv(dev);
1202        void __iomem *ioaddr = np->mem;
1203        unsigned long flags;
1204        int i;
1205
1206        printk(KERN_WARNING
1207               "%s: Transmit timed out, status %8.8x, resetting...\n",
1208               dev->name, ioread32(ioaddr + ISR));
1209
1210        {
1211                printk(KERN_DEBUG "  Rx ring %p: ", np->rx_ring);
1212                for (i = 0; i < RX_RING_SIZE; i++)
1213                        printk(KERN_CONT " %8.8x",
1214                               (unsigned int) np->rx_ring[i].status);
1215                printk(KERN_CONT "\n");
1216                printk(KERN_DEBUG "  Tx ring %p: ", np->tx_ring);
1217                for (i = 0; i < TX_RING_SIZE; i++)
1218                        printk(KERN_CONT " %4.4x", np->tx_ring[i].status);
1219                printk(KERN_CONT "\n");
1220        }
1221
1222        spin_lock_irqsave(&np->lock, flags);
1223
1224        reset_and_disable_rxtx(dev);
1225        reset_tx_descriptors(dev);
1226        enable_rxtx(dev);
1227
1228        spin_unlock_irqrestore(&np->lock, flags);
1229
1230        netif_trans_update(dev); /* prevent tx timeout */
1231        dev->stats.tx_errors++;
1232        netif_wake_queue(dev); /* or .._start_.. ?? */
1233}
1234
1235
1236/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1237static void init_ring(struct net_device *dev)
1238{
1239        struct netdev_private *np = netdev_priv(dev);
1240        int i;
1241
1242        /* initialize rx variables */
1243        np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1244        np->cur_rx = &np->rx_ring[0];
1245        np->lack_rxbuf = np->rx_ring;
1246        np->really_rx_count = 0;
1247
1248        /* initial rx descriptors. */
1249        for (i = 0; i < RX_RING_SIZE; i++) {
1250                np->rx_ring[i].status = 0;
1251                np->rx_ring[i].control = np->rx_buf_sz << RBSShift;
1252                np->rx_ring[i].next_desc = np->rx_ring_dma +
1253                        (i + 1)*sizeof(struct fealnx_desc);
1254                np->rx_ring[i].next_desc_logical = &np->rx_ring[i + 1];
1255                np->rx_ring[i].skbuff = NULL;
1256        }
1257
1258        /* for the last rx descriptor */
1259        np->rx_ring[i - 1].next_desc = np->rx_ring_dma;
1260        np->rx_ring[i - 1].next_desc_logical = np->rx_ring;
1261
1262        /* allocate skb for rx buffers */
1263        for (i = 0; i < RX_RING_SIZE; i++) {
1264                struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz);
1265
1266                if (skb == NULL) {
1267                        np->lack_rxbuf = &np->rx_ring[i];
1268                        break;
1269                }
1270
1271                ++np->really_rx_count;
1272                np->rx_ring[i].skbuff = skb;
1273                np->rx_ring[i].buffer = pci_map_single(np->pci_dev, skb->data,
1274                        np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1275                np->rx_ring[i].status = RXOWN;
1276                np->rx_ring[i].control |= RXIC;
1277        }
1278
1279        /* initialize tx variables */
1280        np->cur_tx = &np->tx_ring[0];
1281        np->cur_tx_copy = &np->tx_ring[0];
1282        np->really_tx_count = 0;
1283        np->free_tx_count = TX_RING_SIZE;
1284
1285        for (i = 0; i < TX_RING_SIZE; i++) {
1286                np->tx_ring[i].status = 0;
1287                /* do we need np->tx_ring[i].control = XXX; ?? */
1288                np->tx_ring[i].next_desc = np->tx_ring_dma +
1289                        (i + 1)*sizeof(struct fealnx_desc);
1290                np->tx_ring[i].next_desc_logical = &np->tx_ring[i + 1];
1291                np->tx_ring[i].skbuff = NULL;
1292        }
1293
1294        /* for the last tx descriptor */
1295        np->tx_ring[i - 1].next_desc = np->tx_ring_dma;
1296        np->tx_ring[i - 1].next_desc_logical = &np->tx_ring[0];
1297}
1298
1299
1300static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
1301{
1302        struct netdev_private *np = netdev_priv(dev);
1303        unsigned long flags;
1304
1305        spin_lock_irqsave(&np->lock, flags);
1306
1307        np->cur_tx_copy->skbuff = skb;
1308
1309#define one_buffer
1310#define BPT 1022
1311#if defined(one_buffer)
1312        np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1313                skb->len, PCI_DMA_TODEVICE);
1314        np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1315        np->cur_tx_copy->control |= (skb->len << PKTSShift);    /* pkt size */
1316        np->cur_tx_copy->control |= (skb->len << TBSShift);     /* buffer size */
1317// 89/12/29 add,
1318        if (np->pci_dev->device == 0x891)
1319                np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1320        np->cur_tx_copy->status = TXOWN;
1321        np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1322        --np->free_tx_count;
1323#elif defined(two_buffer)
1324        if (skb->len > BPT) {
1325                struct fealnx_desc *next;
1326
1327                /* for the first descriptor */
1328                np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1329                        BPT, PCI_DMA_TODEVICE);
1330                np->cur_tx_copy->control = TXIC | TXFD | CRCEnable | PADEnable;
1331                np->cur_tx_copy->control |= (skb->len << PKTSShift);    /* pkt size */
1332                np->cur_tx_copy->control |= (BPT << TBSShift);  /* buffer size */
1333
1334                /* for the last descriptor */
1335                next = np->cur_tx_copy->next_desc_logical;
1336                next->skbuff = skb;
1337                next->control = TXIC | TXLD | CRCEnable | PADEnable;
1338                next->control |= (skb->len << PKTSShift);       /* pkt size */
1339                next->control |= ((skb->len - BPT) << TBSShift);        /* buf size */
1340// 89/12/29 add,
1341                if (np->pci_dev->device == 0x891)
1342                        np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1343                next->buffer = pci_map_single(ep->pci_dev, skb->data + BPT,
1344                                skb->len - BPT, PCI_DMA_TODEVICE);
1345
1346                next->status = TXOWN;
1347                np->cur_tx_copy->status = TXOWN;
1348
1349                np->cur_tx_copy = next->next_desc_logical;
1350                np->free_tx_count -= 2;
1351        } else {
1352                np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1353                        skb->len, PCI_DMA_TODEVICE);
1354                np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1355                np->cur_tx_copy->control |= (skb->len << PKTSShift);    /* pkt size */
1356                np->cur_tx_copy->control |= (skb->len << TBSShift);     /* buffer size */
1357// 89/12/29 add,
1358                if (np->pci_dev->device == 0x891)
1359                        np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1360                np->cur_tx_copy->status = TXOWN;
1361                np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1362                --np->free_tx_count;
1363        }
1364#endif
1365
1366        if (np->free_tx_count < 2)
1367                netif_stop_queue(dev);
1368        ++np->really_tx_count;
1369        iowrite32(0, np->mem + TXPDR);
1370
1371        spin_unlock_irqrestore(&np->lock, flags);
1372        return NETDEV_TX_OK;
1373}
1374
1375
1376/* Take lock before calling */
1377/* Chip probably hosed tx ring. Clean up. */
1378static void reset_tx_descriptors(struct net_device *dev)
1379{
1380        struct netdev_private *np = netdev_priv(dev);
1381        struct fealnx_desc *cur;
1382        int i;
1383
1384        /* initialize tx variables */
1385        np->cur_tx = &np->tx_ring[0];
1386        np->cur_tx_copy = &np->tx_ring[0];
1387        np->really_tx_count = 0;
1388        np->free_tx_count = TX_RING_SIZE;
1389
1390        for (i = 0; i < TX_RING_SIZE; i++) {
1391                cur = &np->tx_ring[i];
1392                if (cur->skbuff) {
1393                        pci_unmap_single(np->pci_dev, cur->buffer,
1394                                cur->skbuff->len, PCI_DMA_TODEVICE);
1395                        dev_kfree_skb_any(cur->skbuff);
1396                        cur->skbuff = NULL;
1397                }
1398                cur->status = 0;
1399                cur->control = 0;       /* needed? */
1400                /* probably not needed. We do it for purely paranoid reasons */
1401                cur->next_desc = np->tx_ring_dma +
1402                        (i + 1)*sizeof(struct fealnx_desc);
1403                cur->next_desc_logical = &np->tx_ring[i + 1];
1404        }
1405        /* for the last tx descriptor */
1406        np->tx_ring[TX_RING_SIZE - 1].next_desc = np->tx_ring_dma;
1407        np->tx_ring[TX_RING_SIZE - 1].next_desc_logical = &np->tx_ring[0];
1408}
1409
1410
1411/* Take lock and stop rx before calling this */
1412static void reset_rx_descriptors(struct net_device *dev)
1413{
1414        struct netdev_private *np = netdev_priv(dev);
1415        struct fealnx_desc *cur = np->cur_rx;
1416        int i;
1417
1418        allocate_rx_buffers(dev);
1419
1420        for (i = 0; i < RX_RING_SIZE; i++) {
1421                if (cur->skbuff)
1422                        cur->status = RXOWN;
1423                cur = cur->next_desc_logical;
1424        }
1425
1426        iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1427                np->mem + RXLBA);
1428}
1429
1430
1431/* The interrupt handler does all of the Rx thread work and cleans up
1432   after the Tx thread. */
1433static irqreturn_t intr_handler(int irq, void *dev_instance)
1434{
1435        struct net_device *dev = (struct net_device *) dev_instance;
1436        struct netdev_private *np = netdev_priv(dev);
1437        void __iomem *ioaddr = np->mem;
1438        long boguscnt = max_interrupt_work;
1439        unsigned int num_tx = 0;
1440        int handled = 0;
1441
1442        spin_lock(&np->lock);
1443
1444        iowrite32(0, ioaddr + IMR);
1445
1446        do {
1447                u32 intr_status = ioread32(ioaddr + ISR);
1448
1449                /* Acknowledge all of the current interrupt sources ASAP. */
1450                iowrite32(intr_status, ioaddr + ISR);
1451
1452                if (debug)
1453                        printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", dev->name,
1454                               intr_status);
1455
1456                if (!(intr_status & np->imrvalue))
1457                        break;
1458
1459                handled = 1;
1460
1461// 90/1/16 delete,
1462//
1463//      if (intr_status & FBE)
1464//      {   /* fatal error */
1465//          stop_nic_tx(ioaddr, 0);
1466//          stop_nic_rx(ioaddr, 0);
1467//          break;
1468//      };
1469
1470                if (intr_status & TUNF)
1471                        iowrite32(0, ioaddr + TXPDR);
1472
1473                if (intr_status & CNTOVF) {
1474                        /* missed pkts */
1475                        dev->stats.rx_missed_errors +=
1476                                ioread32(ioaddr + TALLY) & 0x7fff;
1477
1478                        /* crc error */
1479                        dev->stats.rx_crc_errors +=
1480                            (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1481                }
1482
1483                if (intr_status & (RI | RBU)) {
1484                        if (intr_status & RI)
1485                                netdev_rx(dev);
1486                        else {
1487                                stop_nic_rx(ioaddr, np->crvalue);
1488                                reset_rx_descriptors(dev);
1489                                iowrite32(np->crvalue, ioaddr + TCRRCR);
1490                        }
1491                }
1492
1493                while (np->really_tx_count) {
1494                        long tx_status = np->cur_tx->status;
1495                        long tx_control = np->cur_tx->control;
1496
1497                        if (!(tx_control & TXLD)) {     /* this pkt is combined by two tx descriptors */
1498                                struct fealnx_desc *next;
1499
1500                                next = np->cur_tx->next_desc_logical;
1501                                tx_status = next->status;
1502                                tx_control = next->control;
1503                        }
1504
1505                        if (tx_status & TXOWN)
1506                                break;
1507
1508                        if (!(np->crvalue & CR_W_ENH)) {
1509                                if (tx_status & (CSL | LC | EC | UDF | HF)) {
1510                                        dev->stats.tx_errors++;
1511                                        if (tx_status & EC)
1512                                                dev->stats.tx_aborted_errors++;
1513                                        if (tx_status & CSL)
1514                                                dev->stats.tx_carrier_errors++;
1515                                        if (tx_status & LC)
1516                                                dev->stats.tx_window_errors++;
1517                                        if (tx_status & UDF)
1518                                                dev->stats.tx_fifo_errors++;
1519                                        if ((tx_status & HF) && np->mii.full_duplex == 0)
1520                                                dev->stats.tx_heartbeat_errors++;
1521
1522                                } else {
1523                                        dev->stats.tx_bytes +=
1524                                            ((tx_control & PKTSMask) >> PKTSShift);
1525
1526                                        dev->stats.collisions +=
1527                                            ((tx_status & NCRMask) >> NCRShift);
1528                                        dev->stats.tx_packets++;
1529                                }
1530                        } else {
1531                                dev->stats.tx_bytes +=
1532                                    ((tx_control & PKTSMask) >> PKTSShift);
1533                                dev->stats.tx_packets++;
1534                        }
1535
1536                        /* Free the original skb. */
1537                        pci_unmap_single(np->pci_dev, np->cur_tx->buffer,
1538                                np->cur_tx->skbuff->len, PCI_DMA_TODEVICE);
1539                        dev_kfree_skb_irq(np->cur_tx->skbuff);
1540                        np->cur_tx->skbuff = NULL;
1541                        --np->really_tx_count;
1542                        if (np->cur_tx->control & TXLD) {
1543                                np->cur_tx = np->cur_tx->next_desc_logical;
1544                                ++np->free_tx_count;
1545                        } else {
1546                                np->cur_tx = np->cur_tx->next_desc_logical;
1547                                np->cur_tx = np->cur_tx->next_desc_logical;
1548                                np->free_tx_count += 2;
1549                        }
1550                        num_tx++;
1551                }               /* end of for loop */
1552
1553                if (num_tx && np->free_tx_count >= 2)
1554                        netif_wake_queue(dev);
1555
1556                /* read transmit status for enhanced mode only */
1557                if (np->crvalue & CR_W_ENH) {
1558                        long data;
1559
1560                        data = ioread32(ioaddr + TSR);
1561                        dev->stats.tx_errors += (data & 0xff000000) >> 24;
1562                        dev->stats.tx_aborted_errors +=
1563                                (data & 0xff000000) >> 24;
1564                        dev->stats.tx_window_errors +=
1565                                (data & 0x00ff0000) >> 16;
1566                        dev->stats.collisions += (data & 0x0000ffff);
1567                }
1568
1569                if (--boguscnt < 0) {
1570                        printk(KERN_WARNING "%s: Too much work at interrupt, "
1571                               "status=0x%4.4x.\n", dev->name, intr_status);
1572                        if (!np->reset_timer_armed) {
1573                                np->reset_timer_armed = 1;
1574                                np->reset_timer.expires = RUN_AT(HZ/2);
1575                                add_timer(&np->reset_timer);
1576                                stop_nic_rxtx(ioaddr, 0);
1577                                netif_stop_queue(dev);
1578                                /* or netif_tx_disable(dev); ?? */
1579                                /* Prevent other paths from enabling tx,rx,intrs */
1580                                np->crvalue_sv = np->crvalue;
1581                                np->imrvalue_sv = np->imrvalue;
1582                                np->crvalue &= ~(CR_W_TXEN | CR_W_RXEN); /* or simply = 0? */
1583                                np->imrvalue = 0;
1584                        }
1585
1586                        break;
1587                }
1588        } while (1);
1589
1590        /* read the tally counters */
1591        /* missed pkts */
1592        dev->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1593
1594        /* crc error */
1595        dev->stats.rx_crc_errors +=
1596                (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1597
1598        if (debug)
1599                printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1600                       dev->name, ioread32(ioaddr + ISR));
1601
1602        iowrite32(np->imrvalue, ioaddr + IMR);
1603
1604        spin_unlock(&np->lock);
1605
1606        return IRQ_RETVAL(handled);
1607}
1608
1609
1610/* This routine is logically part of the interrupt handler, but separated
1611   for clarity and better register allocation. */
1612static int netdev_rx(struct net_device *dev)
1613{
1614        struct netdev_private *np = netdev_priv(dev);
1615        void __iomem *ioaddr = np->mem;
1616
1617        /* If EOP is set on the next entry, it's a new packet. Send it up. */
1618        while (!(np->cur_rx->status & RXOWN) && np->cur_rx->skbuff) {
1619                s32 rx_status = np->cur_rx->status;
1620
1621                if (np->really_rx_count == 0)
1622                        break;
1623
1624                if (debug)
1625                        printk(KERN_DEBUG "  netdev_rx() status was %8.8x.\n", rx_status);
1626
1627                if ((!((rx_status & RXFSD) && (rx_status & RXLSD))) ||
1628                    (rx_status & ErrorSummary)) {
1629                        if (rx_status & ErrorSummary) { /* there was a fatal error */
1630                                if (debug)
1631                                        printk(KERN_DEBUG
1632                                               "%s: Receive error, Rx status %8.8x.\n",
1633                                               dev->name, rx_status);
1634
1635                                dev->stats.rx_errors++; /* end of a packet. */
1636                                if (rx_status & (LONG | RUNT))
1637                                        dev->stats.rx_length_errors++;
1638                                if (rx_status & RXER)
1639                                        dev->stats.rx_frame_errors++;
1640                                if (rx_status & CRC)
1641                                        dev->stats.rx_crc_errors++;
1642                        } else {
1643                                int need_to_reset = 0;
1644                                int desno = 0;
1645
1646                                if (rx_status & RXFSD) {        /* this pkt is too long, over one rx buffer */
1647                                        struct fealnx_desc *cur;
1648
1649                                        /* check this packet is received completely? */
1650                                        cur = np->cur_rx;
1651                                        while (desno <= np->really_rx_count) {
1652                                                ++desno;
1653                                                if ((!(cur->status & RXOWN)) &&
1654                                                    (cur->status & RXLSD))
1655                                                        break;
1656                                                /* goto next rx descriptor */
1657                                                cur = cur->next_desc_logical;
1658                                        }
1659                                        if (desno > np->really_rx_count)
1660                                                need_to_reset = 1;
1661                                } else  /* RXLSD did not find, something error */
1662                                        need_to_reset = 1;
1663
1664                                if (need_to_reset == 0) {
1665                                        int i;
1666
1667                                        dev->stats.rx_length_errors++;
1668
1669                                        /* free all rx descriptors related this long pkt */
1670                                        for (i = 0; i < desno; ++i) {
1671                                                if (!np->cur_rx->skbuff) {
1672                                                        printk(KERN_DEBUG
1673                                                                "%s: I'm scared\n", dev->name);
1674                                                        break;
1675                                                }
1676                                                np->cur_rx->status = RXOWN;
1677                                                np->cur_rx = np->cur_rx->next_desc_logical;
1678                                        }
1679                                        continue;
1680                                } else {        /* rx error, need to reset this chip */
1681                                        stop_nic_rx(ioaddr, np->crvalue);
1682                                        reset_rx_descriptors(dev);
1683                                        iowrite32(np->crvalue, ioaddr + TCRRCR);
1684                                }
1685                                break;  /* exit the while loop */
1686                        }
1687                } else {        /* this received pkt is ok */
1688
1689                        struct sk_buff *skb;
1690                        /* Omit the four octet CRC from the length. */
1691                        short pkt_len = ((rx_status & FLNGMASK) >> FLNGShift) - 4;
1692
1693#ifndef final_version
1694                        if (debug)
1695                                printk(KERN_DEBUG "  netdev_rx() normal Rx pkt length %d"
1696                                       " status %x.\n", pkt_len, rx_status);
1697#endif
1698
1699                        /* Check if the packet is long enough to accept without copying
1700                           to a minimally-sized skbuff. */
1701                        if (pkt_len < rx_copybreak &&
1702                            (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
1703                                skb_reserve(skb, 2);    /* 16 byte align the IP header */
1704                                pci_dma_sync_single_for_cpu(np->pci_dev,
1705                                                            np->cur_rx->buffer,
1706                                                            np->rx_buf_sz,
1707                                                            PCI_DMA_FROMDEVICE);
1708                                /* Call copy + cksum if available. */
1709
1710#if ! defined(__alpha__)
1711                                skb_copy_to_linear_data(skb,
1712                                        np->cur_rx->skbuff->data, pkt_len);
1713                                skb_put(skb, pkt_len);
1714#else
1715                                memcpy(skb_put(skb, pkt_len),
1716                                        np->cur_rx->skbuff->data, pkt_len);
1717#endif
1718                                pci_dma_sync_single_for_device(np->pci_dev,
1719                                                               np->cur_rx->buffer,
1720                                                               np->rx_buf_sz,
1721                                                               PCI_DMA_FROMDEVICE);
1722                        } else {
1723                                pci_unmap_single(np->pci_dev,
1724                                                 np->cur_rx->buffer,
1725                                                 np->rx_buf_sz,
1726                                                 PCI_DMA_FROMDEVICE);
1727                                skb_put(skb = np->cur_rx->skbuff, pkt_len);
1728                                np->cur_rx->skbuff = NULL;
1729                                --np->really_rx_count;
1730                        }
1731                        skb->protocol = eth_type_trans(skb, dev);
1732                        netif_rx(skb);
1733                        dev->stats.rx_packets++;
1734                        dev->stats.rx_bytes += pkt_len;
1735                }
1736
1737                np->cur_rx = np->cur_rx->next_desc_logical;
1738        }                       /* end of while loop */
1739
1740        /*  allocate skb for rx buffers */
1741        allocate_rx_buffers(dev);
1742
1743        return 0;
1744}
1745
1746
1747static struct net_device_stats *get_stats(struct net_device *dev)
1748{
1749        struct netdev_private *np = netdev_priv(dev);
1750        void __iomem *ioaddr = np->mem;
1751
1752        /* The chip only need report frame silently dropped. */
1753        if (netif_running(dev)) {
1754                dev->stats.rx_missed_errors +=
1755                        ioread32(ioaddr + TALLY) & 0x7fff;
1756                dev->stats.rx_crc_errors +=
1757                        (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1758        }
1759
1760        return &dev->stats;
1761}
1762
1763
1764/* for dev->set_multicast_list */
1765static void set_rx_mode(struct net_device *dev)
1766{
1767        spinlock_t *lp = &((struct netdev_private *)netdev_priv(dev))->lock;
1768        unsigned long flags;
1769        spin_lock_irqsave(lp, flags);
1770        __set_rx_mode(dev);
1771        spin_unlock_irqrestore(lp, flags);
1772}
1773
1774
1775/* Take lock before calling */
1776static void __set_rx_mode(struct net_device *dev)
1777{
1778        struct netdev_private *np = netdev_priv(dev);
1779        void __iomem *ioaddr = np->mem;
1780        u32 mc_filter[2];       /* Multicast hash filter */
1781        u32 rx_mode;
1782
1783        if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1784                memset(mc_filter, 0xff, sizeof(mc_filter));
1785                rx_mode = CR_W_PROM | CR_W_AB | CR_W_AM;
1786        } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
1787                   (dev->flags & IFF_ALLMULTI)) {
1788                /* Too many to match, or accept all multicasts. */
1789                memset(mc_filter, 0xff, sizeof(mc_filter));
1790                rx_mode = CR_W_AB | CR_W_AM;
1791        } else {
1792                struct netdev_hw_addr *ha;
1793
1794                memset(mc_filter, 0, sizeof(mc_filter));
1795                netdev_for_each_mc_addr(ha, dev) {
1796                        unsigned int bit;
1797                        bit = (ether_crc(ETH_ALEN, ha->addr) >> 26) ^ 0x3F;
1798                        mc_filter[bit >> 5] |= (1 << bit);
1799                }
1800                rx_mode = CR_W_AB | CR_W_AM;
1801        }
1802
1803        stop_nic_rxtx(ioaddr, np->crvalue);
1804
1805        iowrite32(mc_filter[0], ioaddr + MAR0);
1806        iowrite32(mc_filter[1], ioaddr + MAR1);
1807        np->crvalue &= ~CR_W_RXMODEMASK;
1808        np->crvalue |= rx_mode;
1809        iowrite32(np->crvalue, ioaddr + TCRRCR);
1810}
1811
1812static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1813{
1814        struct netdev_private *np = netdev_priv(dev);
1815
1816        strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1817        strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1818        strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
1819}
1820
1821static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1822{
1823        struct netdev_private *np = netdev_priv(dev);
1824        int rc;
1825
1826        spin_lock_irq(&np->lock);
1827        rc = mii_ethtool_gset(&np->mii, cmd);
1828        spin_unlock_irq(&np->lock);
1829
1830        return rc;
1831}
1832
1833static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1834{
1835        struct netdev_private *np = netdev_priv(dev);
1836        int rc;
1837
1838        spin_lock_irq(&np->lock);
1839        rc = mii_ethtool_sset(&np->mii, cmd);
1840        spin_unlock_irq(&np->lock);
1841
1842        return rc;
1843}
1844
1845static int netdev_nway_reset(struct net_device *dev)
1846{
1847        struct netdev_private *np = netdev_priv(dev);
1848        return mii_nway_restart(&np->mii);
1849}
1850
1851static u32 netdev_get_link(struct net_device *dev)
1852{
1853        struct netdev_private *np = netdev_priv(dev);
1854        return mii_link_ok(&np->mii);
1855}
1856
1857static u32 netdev_get_msglevel(struct net_device *dev)
1858{
1859        return debug;
1860}
1861
1862static void netdev_set_msglevel(struct net_device *dev, u32 value)
1863{
1864        debug = value;
1865}
1866
1867static const struct ethtool_ops netdev_ethtool_ops = {
1868        .get_drvinfo            = netdev_get_drvinfo,
1869        .get_settings           = netdev_get_settings,
1870        .set_settings           = netdev_set_settings,
1871        .nway_reset             = netdev_nway_reset,
1872        .get_link               = netdev_get_link,
1873        .get_msglevel           = netdev_get_msglevel,
1874        .set_msglevel           = netdev_set_msglevel,
1875};
1876
1877static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1878{
1879        struct netdev_private *np = netdev_priv(dev);
1880        int rc;
1881
1882        if (!netif_running(dev))
1883                return -EINVAL;
1884
1885        spin_lock_irq(&np->lock);
1886        rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
1887        spin_unlock_irq(&np->lock);
1888
1889        return rc;
1890}
1891
1892
1893static int netdev_close(struct net_device *dev)
1894{
1895        struct netdev_private *np = netdev_priv(dev);
1896        void __iomem *ioaddr = np->mem;
1897        int i;
1898
1899        netif_stop_queue(dev);
1900
1901        /* Disable interrupts by clearing the interrupt mask. */
1902        iowrite32(0x0000, ioaddr + IMR);
1903
1904        /* Stop the chip's Tx and Rx processes. */
1905        stop_nic_rxtx(ioaddr, 0);
1906
1907        del_timer_sync(&np->timer);
1908        del_timer_sync(&np->reset_timer);
1909
1910        free_irq(np->pci_dev->irq, dev);
1911
1912        /* Free all the skbuffs in the Rx queue. */
1913        for (i = 0; i < RX_RING_SIZE; i++) {
1914                struct sk_buff *skb = np->rx_ring[i].skbuff;
1915
1916                np->rx_ring[i].status = 0;
1917                if (skb) {
1918                        pci_unmap_single(np->pci_dev, np->rx_ring[i].buffer,
1919                                np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1920                        dev_kfree_skb(skb);
1921                        np->rx_ring[i].skbuff = NULL;
1922                }
1923        }
1924
1925        for (i = 0; i < TX_RING_SIZE; i++) {
1926                struct sk_buff *skb = np->tx_ring[i].skbuff;
1927
1928                if (skb) {
1929                        pci_unmap_single(np->pci_dev, np->tx_ring[i].buffer,
1930                                skb->len, PCI_DMA_TODEVICE);
1931                        dev_kfree_skb(skb);
1932                        np->tx_ring[i].skbuff = NULL;
1933                }
1934        }
1935
1936        return 0;
1937}
1938
1939static const struct pci_device_id fealnx_pci_tbl[] = {
1940        {0x1516, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1941        {0x1516, 0x0803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1942        {0x1516, 0x0891, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1943        {} /* terminate list */
1944};
1945MODULE_DEVICE_TABLE(pci, fealnx_pci_tbl);
1946
1947
1948static struct pci_driver fealnx_driver = {
1949        .name           = "fealnx",
1950        .id_table       = fealnx_pci_tbl,
1951        .probe          = fealnx_init_one,
1952        .remove         = fealnx_remove_one,
1953};
1954
1955static int __init fealnx_init(void)
1956{
1957/* when a module, this is printed whether or not devices are found in probe */
1958#ifdef MODULE
1959        printk(version);
1960#endif
1961
1962        return pci_register_driver(&fealnx_driver);
1963}
1964
1965static void __exit fealnx_exit(void)
1966{
1967        pci_unregister_driver(&fealnx_driver);
1968}
1969
1970module_init(fealnx_init);
1971module_exit(fealnx_exit);
1972