linux/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h
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   1/*******************************************************************************
   2 *
   3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4 * Copyright(c) 2013 - 2016 Intel Corporation.
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public License,
   8 * version 2, as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope it will be useful, but WITHOUT
  11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13 * more details.
  14 *
  15 * You should have received a copy of the GNU General Public License along
  16 * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17 *
  18 * The full GNU General Public License is included in this distribution in
  19 * the file called "COPYING".
  20 *
  21 * Contact Information:
  22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24 *
  25 ******************************************************************************/
  26
  27#ifndef _I40E_ADMINQ_CMD_H_
  28#define _I40E_ADMINQ_CMD_H_
  29
  30/* This header file defines the i40e Admin Queue commands and is shared between
  31 * i40e Firmware and Software.
  32 *
  33 * This file needs to comply with the Linux Kernel coding style.
  34 */
  35
  36#define I40E_FW_API_VERSION_MAJOR       0x0001
  37#define I40E_FW_API_VERSION_MINOR       0x0005
  38
  39struct i40e_aq_desc {
  40        __le16 flags;
  41        __le16 opcode;
  42        __le16 datalen;
  43        __le16 retval;
  44        __le32 cookie_high;
  45        __le32 cookie_low;
  46        union {
  47                struct {
  48                        __le32 param0;
  49                        __le32 param1;
  50                        __le32 param2;
  51                        __le32 param3;
  52                } internal;
  53                struct {
  54                        __le32 param0;
  55                        __le32 param1;
  56                        __le32 addr_high;
  57                        __le32 addr_low;
  58                } external;
  59                u8 raw[16];
  60        } params;
  61};
  62
  63/* Flags sub-structure
  64 * |0  |1  |2  |3  |4  |5  |6  |7  |8  |9  |10 |11 |12 |13 |14 |15 |
  65 * |DD |CMP|ERR|VFE| * *  RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
  66 */
  67
  68/* command flags and offsets*/
  69#define I40E_AQ_FLAG_DD_SHIFT   0
  70#define I40E_AQ_FLAG_CMP_SHIFT  1
  71#define I40E_AQ_FLAG_ERR_SHIFT  2
  72#define I40E_AQ_FLAG_VFE_SHIFT  3
  73#define I40E_AQ_FLAG_LB_SHIFT   9
  74#define I40E_AQ_FLAG_RD_SHIFT   10
  75#define I40E_AQ_FLAG_VFC_SHIFT  11
  76#define I40E_AQ_FLAG_BUF_SHIFT  12
  77#define I40E_AQ_FLAG_SI_SHIFT   13
  78#define I40E_AQ_FLAG_EI_SHIFT   14
  79#define I40E_AQ_FLAG_FE_SHIFT   15
  80
  81#define I40E_AQ_FLAG_DD         BIT(I40E_AQ_FLAG_DD_SHIFT)  /* 0x1    */
  82#define I40E_AQ_FLAG_CMP        BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2    */
  83#define I40E_AQ_FLAG_ERR        BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4    */
  84#define I40E_AQ_FLAG_VFE        BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8    */
  85#define I40E_AQ_FLAG_LB         BIT(I40E_AQ_FLAG_LB_SHIFT)  /* 0x200  */
  86#define I40E_AQ_FLAG_RD         BIT(I40E_AQ_FLAG_RD_SHIFT)  /* 0x400  */
  87#define I40E_AQ_FLAG_VFC        BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800  */
  88#define I40E_AQ_FLAG_BUF        BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
  89#define I40E_AQ_FLAG_SI         BIT(I40E_AQ_FLAG_SI_SHIFT)  /* 0x2000 */
  90#define I40E_AQ_FLAG_EI         BIT(I40E_AQ_FLAG_EI_SHIFT)  /* 0x4000 */
  91#define I40E_AQ_FLAG_FE         BIT(I40E_AQ_FLAG_FE_SHIFT)  /* 0x8000 */
  92
  93/* error codes */
  94enum i40e_admin_queue_err {
  95        I40E_AQ_RC_OK           = 0,  /* success */
  96        I40E_AQ_RC_EPERM        = 1,  /* Operation not permitted */
  97        I40E_AQ_RC_ENOENT       = 2,  /* No such element */
  98        I40E_AQ_RC_ESRCH        = 3,  /* Bad opcode */
  99        I40E_AQ_RC_EINTR        = 4,  /* operation interrupted */
 100        I40E_AQ_RC_EIO          = 5,  /* I/O error */
 101        I40E_AQ_RC_ENXIO        = 6,  /* No such resource */
 102        I40E_AQ_RC_E2BIG        = 7,  /* Arg too long */
 103        I40E_AQ_RC_EAGAIN       = 8,  /* Try again */
 104        I40E_AQ_RC_ENOMEM       = 9,  /* Out of memory */
 105        I40E_AQ_RC_EACCES       = 10, /* Permission denied */
 106        I40E_AQ_RC_EFAULT       = 11, /* Bad address */
 107        I40E_AQ_RC_EBUSY        = 12, /* Device or resource busy */
 108        I40E_AQ_RC_EEXIST       = 13, /* object already exists */
 109        I40E_AQ_RC_EINVAL       = 14, /* Invalid argument */
 110        I40E_AQ_RC_ENOTTY       = 15, /* Not a typewriter */
 111        I40E_AQ_RC_ENOSPC       = 16, /* No space left or alloc failure */
 112        I40E_AQ_RC_ENOSYS       = 17, /* Function not implemented */
 113        I40E_AQ_RC_ERANGE       = 18, /* Parameter out of range */
 114        I40E_AQ_RC_EFLUSHED     = 19, /* Cmd flushed due to prev cmd error */
 115        I40E_AQ_RC_BAD_ADDR     = 20, /* Descriptor contains a bad pointer */
 116        I40E_AQ_RC_EMODE        = 21, /* Op not allowed in current dev mode */
 117        I40E_AQ_RC_EFBIG        = 22, /* File too large */
 118};
 119
 120/* Admin Queue command opcodes */
 121enum i40e_admin_queue_opc {
 122        /* aq commands */
 123        i40e_aqc_opc_get_version        = 0x0001,
 124        i40e_aqc_opc_driver_version     = 0x0002,
 125        i40e_aqc_opc_queue_shutdown     = 0x0003,
 126        i40e_aqc_opc_set_pf_context     = 0x0004,
 127
 128        /* resource ownership */
 129        i40e_aqc_opc_request_resource   = 0x0008,
 130        i40e_aqc_opc_release_resource   = 0x0009,
 131
 132        i40e_aqc_opc_list_func_capabilities     = 0x000A,
 133        i40e_aqc_opc_list_dev_capabilities      = 0x000B,
 134
 135        /* LAA */
 136        i40e_aqc_opc_mac_address_read   = 0x0107,
 137        i40e_aqc_opc_mac_address_write  = 0x0108,
 138
 139        /* PXE */
 140        i40e_aqc_opc_clear_pxe_mode     = 0x0110,
 141
 142        /* internal switch commands */
 143        i40e_aqc_opc_get_switch_config          = 0x0200,
 144        i40e_aqc_opc_add_statistics             = 0x0201,
 145        i40e_aqc_opc_remove_statistics          = 0x0202,
 146        i40e_aqc_opc_set_port_parameters        = 0x0203,
 147        i40e_aqc_opc_get_switch_resource_alloc  = 0x0204,
 148        i40e_aqc_opc_set_switch_config          = 0x0205,
 149        i40e_aqc_opc_rx_ctl_reg_read            = 0x0206,
 150        i40e_aqc_opc_rx_ctl_reg_write           = 0x0207,
 151
 152        i40e_aqc_opc_add_vsi                    = 0x0210,
 153        i40e_aqc_opc_update_vsi_parameters      = 0x0211,
 154        i40e_aqc_opc_get_vsi_parameters         = 0x0212,
 155
 156        i40e_aqc_opc_add_pv                     = 0x0220,
 157        i40e_aqc_opc_update_pv_parameters       = 0x0221,
 158        i40e_aqc_opc_get_pv_parameters          = 0x0222,
 159
 160        i40e_aqc_opc_add_veb                    = 0x0230,
 161        i40e_aqc_opc_update_veb_parameters      = 0x0231,
 162        i40e_aqc_opc_get_veb_parameters         = 0x0232,
 163
 164        i40e_aqc_opc_delete_element             = 0x0243,
 165
 166        i40e_aqc_opc_add_macvlan                = 0x0250,
 167        i40e_aqc_opc_remove_macvlan             = 0x0251,
 168        i40e_aqc_opc_add_vlan                   = 0x0252,
 169        i40e_aqc_opc_remove_vlan                = 0x0253,
 170        i40e_aqc_opc_set_vsi_promiscuous_modes  = 0x0254,
 171        i40e_aqc_opc_add_tag                    = 0x0255,
 172        i40e_aqc_opc_remove_tag                 = 0x0256,
 173        i40e_aqc_opc_add_multicast_etag         = 0x0257,
 174        i40e_aqc_opc_remove_multicast_etag      = 0x0258,
 175        i40e_aqc_opc_update_tag                 = 0x0259,
 176        i40e_aqc_opc_add_control_packet_filter  = 0x025A,
 177        i40e_aqc_opc_remove_control_packet_filter       = 0x025B,
 178        i40e_aqc_opc_add_cloud_filters          = 0x025C,
 179        i40e_aqc_opc_remove_cloud_filters       = 0x025D,
 180
 181        i40e_aqc_opc_add_mirror_rule    = 0x0260,
 182        i40e_aqc_opc_delete_mirror_rule = 0x0261,
 183
 184        /* DCB commands */
 185        i40e_aqc_opc_dcb_ignore_pfc     = 0x0301,
 186        i40e_aqc_opc_dcb_updated        = 0x0302,
 187
 188        /* TX scheduler */
 189        i40e_aqc_opc_configure_vsi_bw_limit             = 0x0400,
 190        i40e_aqc_opc_configure_vsi_ets_sla_bw_limit     = 0x0406,
 191        i40e_aqc_opc_configure_vsi_tc_bw                = 0x0407,
 192        i40e_aqc_opc_query_vsi_bw_config                = 0x0408,
 193        i40e_aqc_opc_query_vsi_ets_sla_config           = 0x040A,
 194        i40e_aqc_opc_configure_switching_comp_bw_limit  = 0x0410,
 195
 196        i40e_aqc_opc_enable_switching_comp_ets                  = 0x0413,
 197        i40e_aqc_opc_modify_switching_comp_ets                  = 0x0414,
 198        i40e_aqc_opc_disable_switching_comp_ets                 = 0x0415,
 199        i40e_aqc_opc_configure_switching_comp_ets_bw_limit      = 0x0416,
 200        i40e_aqc_opc_configure_switching_comp_bw_config         = 0x0417,
 201        i40e_aqc_opc_query_switching_comp_ets_config            = 0x0418,
 202        i40e_aqc_opc_query_port_ets_config                      = 0x0419,
 203        i40e_aqc_opc_query_switching_comp_bw_config             = 0x041A,
 204        i40e_aqc_opc_suspend_port_tx                            = 0x041B,
 205        i40e_aqc_opc_resume_port_tx                             = 0x041C,
 206        i40e_aqc_opc_configure_partition_bw                     = 0x041D,
 207        /* hmc */
 208        i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
 209        i40e_aqc_opc_set_hmc_resource_profile   = 0x0501,
 210
 211        /* phy commands*/
 212        i40e_aqc_opc_get_phy_abilities          = 0x0600,
 213        i40e_aqc_opc_set_phy_config             = 0x0601,
 214        i40e_aqc_opc_set_mac_config             = 0x0603,
 215        i40e_aqc_opc_set_link_restart_an        = 0x0605,
 216        i40e_aqc_opc_get_link_status            = 0x0607,
 217        i40e_aqc_opc_set_phy_int_mask           = 0x0613,
 218        i40e_aqc_opc_get_local_advt_reg         = 0x0614,
 219        i40e_aqc_opc_set_local_advt_reg         = 0x0615,
 220        i40e_aqc_opc_get_partner_advt           = 0x0616,
 221        i40e_aqc_opc_set_lb_modes               = 0x0618,
 222        i40e_aqc_opc_get_phy_wol_caps           = 0x0621,
 223        i40e_aqc_opc_set_phy_debug              = 0x0622,
 224        i40e_aqc_opc_upload_ext_phy_fm          = 0x0625,
 225        i40e_aqc_opc_run_phy_activity           = 0x0626,
 226
 227        /* NVM commands */
 228        i40e_aqc_opc_nvm_read                   = 0x0701,
 229        i40e_aqc_opc_nvm_erase                  = 0x0702,
 230        i40e_aqc_opc_nvm_update                 = 0x0703,
 231        i40e_aqc_opc_nvm_config_read            = 0x0704,
 232        i40e_aqc_opc_nvm_config_write           = 0x0705,
 233        i40e_aqc_opc_oem_post_update            = 0x0720,
 234        i40e_aqc_opc_thermal_sensor             = 0x0721,
 235
 236        /* virtualization commands */
 237        i40e_aqc_opc_send_msg_to_pf             = 0x0801,
 238        i40e_aqc_opc_send_msg_to_vf             = 0x0802,
 239        i40e_aqc_opc_send_msg_to_peer           = 0x0803,
 240
 241        /* alternate structure */
 242        i40e_aqc_opc_alternate_write            = 0x0900,
 243        i40e_aqc_opc_alternate_write_indirect   = 0x0901,
 244        i40e_aqc_opc_alternate_read             = 0x0902,
 245        i40e_aqc_opc_alternate_read_indirect    = 0x0903,
 246        i40e_aqc_opc_alternate_write_done       = 0x0904,
 247        i40e_aqc_opc_alternate_set_mode         = 0x0905,
 248        i40e_aqc_opc_alternate_clear_port       = 0x0906,
 249
 250        /* LLDP commands */
 251        i40e_aqc_opc_lldp_get_mib       = 0x0A00,
 252        i40e_aqc_opc_lldp_update_mib    = 0x0A01,
 253        i40e_aqc_opc_lldp_add_tlv       = 0x0A02,
 254        i40e_aqc_opc_lldp_update_tlv    = 0x0A03,
 255        i40e_aqc_opc_lldp_delete_tlv    = 0x0A04,
 256        i40e_aqc_opc_lldp_stop          = 0x0A05,
 257        i40e_aqc_opc_lldp_start         = 0x0A06,
 258
 259        /* Tunnel commands */
 260        i40e_aqc_opc_add_udp_tunnel     = 0x0B00,
 261        i40e_aqc_opc_del_udp_tunnel     = 0x0B01,
 262        i40e_aqc_opc_set_rss_key        = 0x0B02,
 263        i40e_aqc_opc_set_rss_lut        = 0x0B03,
 264        i40e_aqc_opc_get_rss_key        = 0x0B04,
 265        i40e_aqc_opc_get_rss_lut        = 0x0B05,
 266
 267        /* Async Events */
 268        i40e_aqc_opc_event_lan_overflow         = 0x1001,
 269
 270        /* OEM commands */
 271        i40e_aqc_opc_oem_parameter_change       = 0xFE00,
 272        i40e_aqc_opc_oem_device_status_change   = 0xFE01,
 273        i40e_aqc_opc_oem_ocsd_initialize        = 0xFE02,
 274        i40e_aqc_opc_oem_ocbb_initialize        = 0xFE03,
 275
 276        /* debug commands */
 277        i40e_aqc_opc_debug_read_reg             = 0xFF03,
 278        i40e_aqc_opc_debug_write_reg            = 0xFF04,
 279        i40e_aqc_opc_debug_modify_reg           = 0xFF07,
 280        i40e_aqc_opc_debug_dump_internals       = 0xFF08,
 281};
 282
 283/* command structures and indirect data structures */
 284
 285/* Structure naming conventions:
 286 * - no suffix for direct command descriptor structures
 287 * - _data for indirect sent data
 288 * - _resp for indirect return data (data which is both will use _data)
 289 * - _completion for direct return data
 290 * - _element_ for repeated elements (may also be _data or _resp)
 291 *
 292 * Command structures are expected to overlay the params.raw member of the basic
 293 * descriptor, and as such cannot exceed 16 bytes in length.
 294 */
 295
 296/* This macro is used to generate a compilation error if a structure
 297 * is not exactly the correct length. It gives a divide by zero error if the
 298 * structure is not of the correct size, otherwise it creates an enum that is
 299 * never used.
 300 */
 301#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
 302        { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
 303
 304/* This macro is used extensively to ensure that command structures are 16
 305 * bytes in length as they have to map to the raw array of that size.
 306 */
 307#define I40E_CHECK_CMD_LENGTH(X)        I40E_CHECK_STRUCT_LEN(16, X)
 308
 309/* internal (0x00XX) commands */
 310
 311/* Get version (direct 0x0001) */
 312struct i40e_aqc_get_version {
 313        __le32 rom_ver;
 314        __le32 fw_build;
 315        __le16 fw_major;
 316        __le16 fw_minor;
 317        __le16 api_major;
 318        __le16 api_minor;
 319};
 320
 321I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
 322
 323/* Send driver version (indirect 0x0002) */
 324struct i40e_aqc_driver_version {
 325        u8      driver_major_ver;
 326        u8      driver_minor_ver;
 327        u8      driver_build_ver;
 328        u8      driver_subbuild_ver;
 329        u8      reserved[4];
 330        __le32  address_high;
 331        __le32  address_low;
 332};
 333
 334I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
 335
 336/* Queue Shutdown (direct 0x0003) */
 337struct i40e_aqc_queue_shutdown {
 338        __le32  driver_unloading;
 339#define I40E_AQ_DRIVER_UNLOADING        0x1
 340        u8      reserved[12];
 341};
 342
 343I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
 344
 345/* Set PF context (0x0004, direct) */
 346struct i40e_aqc_set_pf_context {
 347        u8      pf_id;
 348        u8      reserved[15];
 349};
 350
 351I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
 352
 353/* Request resource ownership (direct 0x0008)
 354 * Release resource ownership (direct 0x0009)
 355 */
 356#define I40E_AQ_RESOURCE_NVM                    1
 357#define I40E_AQ_RESOURCE_SDP                    2
 358#define I40E_AQ_RESOURCE_ACCESS_READ            1
 359#define I40E_AQ_RESOURCE_ACCESS_WRITE           2
 360#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT       3000
 361#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT      180000
 362
 363struct i40e_aqc_request_resource {
 364        __le16  resource_id;
 365        __le16  access_type;
 366        __le32  timeout;
 367        __le32  resource_number;
 368        u8      reserved[4];
 369};
 370
 371I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
 372
 373/* Get function capabilities (indirect 0x000A)
 374 * Get device capabilities (indirect 0x000B)
 375 */
 376struct i40e_aqc_list_capabilites {
 377        u8 command_flags;
 378#define I40E_AQ_LIST_CAP_PF_INDEX_EN    1
 379        u8 pf_index;
 380        u8 reserved[2];
 381        __le32 count;
 382        __le32 addr_high;
 383        __le32 addr_low;
 384};
 385
 386I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
 387
 388struct i40e_aqc_list_capabilities_element_resp {
 389        __le16  id;
 390        u8      major_rev;
 391        u8      minor_rev;
 392        __le32  number;
 393        __le32  logical_id;
 394        __le32  phys_id;
 395        u8      reserved[16];
 396};
 397
 398/* list of caps */
 399
 400#define I40E_AQ_CAP_ID_SWITCH_MODE      0x0001
 401#define I40E_AQ_CAP_ID_MNG_MODE         0x0002
 402#define I40E_AQ_CAP_ID_NPAR_ACTIVE      0x0003
 403#define I40E_AQ_CAP_ID_OS2BMC_CAP       0x0004
 404#define I40E_AQ_CAP_ID_FUNCTIONS_VALID  0x0005
 405#define I40E_AQ_CAP_ID_ALTERNATE_RAM    0x0006
 406#define I40E_AQ_CAP_ID_WOL_AND_PROXY    0x0008
 407#define I40E_AQ_CAP_ID_SRIOV            0x0012
 408#define I40E_AQ_CAP_ID_VF               0x0013
 409#define I40E_AQ_CAP_ID_VMDQ             0x0014
 410#define I40E_AQ_CAP_ID_8021QBG          0x0015
 411#define I40E_AQ_CAP_ID_8021QBR          0x0016
 412#define I40E_AQ_CAP_ID_VSI              0x0017
 413#define I40E_AQ_CAP_ID_DCB              0x0018
 414#define I40E_AQ_CAP_ID_FCOE             0x0021
 415#define I40E_AQ_CAP_ID_ISCSI            0x0022
 416#define I40E_AQ_CAP_ID_RSS              0x0040
 417#define I40E_AQ_CAP_ID_RXQ              0x0041
 418#define I40E_AQ_CAP_ID_TXQ              0x0042
 419#define I40E_AQ_CAP_ID_MSIX             0x0043
 420#define I40E_AQ_CAP_ID_VF_MSIX          0x0044
 421#define I40E_AQ_CAP_ID_FLOW_DIRECTOR    0x0045
 422#define I40E_AQ_CAP_ID_1588             0x0046
 423#define I40E_AQ_CAP_ID_IWARP            0x0051
 424#define I40E_AQ_CAP_ID_LED              0x0061
 425#define I40E_AQ_CAP_ID_SDP              0x0062
 426#define I40E_AQ_CAP_ID_MDIO             0x0063
 427#define I40E_AQ_CAP_ID_WSR_PROT         0x0064
 428#define I40E_AQ_CAP_ID_NVM_MGMT         0x0080
 429#define I40E_AQ_CAP_ID_FLEX10           0x00F1
 430#define I40E_AQ_CAP_ID_CEM              0x00F2
 431
 432/* Set CPPM Configuration (direct 0x0103) */
 433struct i40e_aqc_cppm_configuration {
 434        __le16  command_flags;
 435#define I40E_AQ_CPPM_EN_LTRC    0x0800
 436#define I40E_AQ_CPPM_EN_DMCTH   0x1000
 437#define I40E_AQ_CPPM_EN_DMCTLX  0x2000
 438#define I40E_AQ_CPPM_EN_HPTC    0x4000
 439#define I40E_AQ_CPPM_EN_DMARC   0x8000
 440        __le16  ttlx;
 441        __le32  dmacr;
 442        __le16  dmcth;
 443        u8      hptc;
 444        u8      reserved;
 445        __le32  pfltrc;
 446};
 447
 448I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
 449
 450/* Set ARP Proxy command / response (indirect 0x0104) */
 451struct i40e_aqc_arp_proxy_data {
 452        __le16  command_flags;
 453#define I40E_AQ_ARP_INIT_IPV4   0x0800
 454#define I40E_AQ_ARP_UNSUP_CTL   0x1000
 455#define I40E_AQ_ARP_ENA         0x2000
 456#define I40E_AQ_ARP_ADD_IPV4    0x4000
 457#define I40E_AQ_ARP_DEL_IPV4    0x8000
 458        __le16  table_id;
 459        __le32  enabled_offloads;
 460#define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE     0x00000020
 461#define I40E_AQ_ARP_OFFLOAD_ENABLE              0x00000800
 462        __le32  ip_addr;
 463        u8      mac_addr[6];
 464        u8      reserved[2];
 465};
 466
 467I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
 468
 469/* Set NS Proxy Table Entry Command (indirect 0x0105) */
 470struct i40e_aqc_ns_proxy_data {
 471        __le16  table_idx_mac_addr_0;
 472        __le16  table_idx_mac_addr_1;
 473        __le16  table_idx_ipv6_0;
 474        __le16  table_idx_ipv6_1;
 475        __le16  control;
 476#define I40E_AQ_NS_PROXY_ADD_0          0x0001
 477#define I40E_AQ_NS_PROXY_DEL_0          0x0002
 478#define I40E_AQ_NS_PROXY_ADD_1          0x0004
 479#define I40E_AQ_NS_PROXY_DEL_1          0x0008
 480#define I40E_AQ_NS_PROXY_ADD_IPV6_0     0x0010
 481#define I40E_AQ_NS_PROXY_DEL_IPV6_0     0x0020
 482#define I40E_AQ_NS_PROXY_ADD_IPV6_1     0x0040
 483#define I40E_AQ_NS_PROXY_DEL_IPV6_1     0x0080
 484#define I40E_AQ_NS_PROXY_COMMAND_SEQ    0x0100
 485#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL  0x0200
 486#define I40E_AQ_NS_PROXY_INIT_MAC_TBL   0x0400
 487#define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
 488#define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE        0x1000
 489        u8      mac_addr_0[6];
 490        u8      mac_addr_1[6];
 491        u8      local_mac_addr[6];
 492        u8      ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
 493        u8      ipv6_addr_1[16];
 494};
 495
 496I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
 497
 498/* Manage LAA Command (0x0106) - obsolete */
 499struct i40e_aqc_mng_laa {
 500        __le16  command_flags;
 501#define I40E_AQ_LAA_FLAG_WR     0x8000
 502        u8      reserved[2];
 503        __le32  sal;
 504        __le16  sah;
 505        u8      reserved2[6];
 506};
 507
 508I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
 509
 510/* Manage MAC Address Read Command (indirect 0x0107) */
 511struct i40e_aqc_mac_address_read {
 512        __le16  command_flags;
 513#define I40E_AQC_LAN_ADDR_VALID         0x10
 514#define I40E_AQC_SAN_ADDR_VALID         0x20
 515#define I40E_AQC_PORT_ADDR_VALID        0x40
 516#define I40E_AQC_WOL_ADDR_VALID         0x80
 517#define I40E_AQC_MC_MAG_EN_VALID        0x100
 518#define I40E_AQC_ADDR_VALID_MASK        0x1F0
 519        u8      reserved[6];
 520        __le32  addr_high;
 521        __le32  addr_low;
 522};
 523
 524I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
 525
 526struct i40e_aqc_mac_address_read_data {
 527        u8 pf_lan_mac[6];
 528        u8 pf_san_mac[6];
 529        u8 port_mac[6];
 530        u8 pf_wol_mac[6];
 531};
 532
 533I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
 534
 535/* Manage MAC Address Write Command (0x0108) */
 536struct i40e_aqc_mac_address_write {
 537        __le16  command_flags;
 538#define I40E_AQC_WRITE_TYPE_LAA_ONLY    0x0000
 539#define I40E_AQC_WRITE_TYPE_LAA_WOL     0x4000
 540#define I40E_AQC_WRITE_TYPE_PORT        0x8000
 541#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG       0xC000
 542#define I40E_AQC_WRITE_TYPE_MASK        0xC000
 543
 544        __le16  mac_sah;
 545        __le32  mac_sal;
 546        u8      reserved[8];
 547};
 548
 549I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
 550
 551/* PXE commands (0x011x) */
 552
 553/* Clear PXE Command and response  (direct 0x0110) */
 554struct i40e_aqc_clear_pxe {
 555        u8      rx_cnt;
 556        u8      reserved[15];
 557};
 558
 559I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
 560
 561/* Switch configuration commands (0x02xx) */
 562
 563/* Used by many indirect commands that only pass an seid and a buffer in the
 564 * command
 565 */
 566struct i40e_aqc_switch_seid {
 567        __le16  seid;
 568        u8      reserved[6];
 569        __le32  addr_high;
 570        __le32  addr_low;
 571};
 572
 573I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
 574
 575/* Get Switch Configuration command (indirect 0x0200)
 576 * uses i40e_aqc_switch_seid for the descriptor
 577 */
 578struct i40e_aqc_get_switch_config_header_resp {
 579        __le16  num_reported;
 580        __le16  num_total;
 581        u8      reserved[12];
 582};
 583
 584I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
 585
 586struct i40e_aqc_switch_config_element_resp {
 587        u8      element_type;
 588#define I40E_AQ_SW_ELEM_TYPE_MAC        1
 589#define I40E_AQ_SW_ELEM_TYPE_PF         2
 590#define I40E_AQ_SW_ELEM_TYPE_VF         3
 591#define I40E_AQ_SW_ELEM_TYPE_EMP        4
 592#define I40E_AQ_SW_ELEM_TYPE_BMC        5
 593#define I40E_AQ_SW_ELEM_TYPE_PV         16
 594#define I40E_AQ_SW_ELEM_TYPE_VEB        17
 595#define I40E_AQ_SW_ELEM_TYPE_PA         18
 596#define I40E_AQ_SW_ELEM_TYPE_VSI        19
 597        u8      revision;
 598#define I40E_AQ_SW_ELEM_REV_1           1
 599        __le16  seid;
 600        __le16  uplink_seid;
 601        __le16  downlink_seid;
 602        u8      reserved[3];
 603        u8      connection_type;
 604#define I40E_AQ_CONN_TYPE_REGULAR       0x1
 605#define I40E_AQ_CONN_TYPE_DEFAULT       0x2
 606#define I40E_AQ_CONN_TYPE_CASCADED      0x3
 607        __le16  scheduler_id;
 608        __le16  element_info;
 609};
 610
 611I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
 612
 613/* Get Switch Configuration (indirect 0x0200)
 614 *    an array of elements are returned in the response buffer
 615 *    the first in the array is the header, remainder are elements
 616 */
 617struct i40e_aqc_get_switch_config_resp {
 618        struct i40e_aqc_get_switch_config_header_resp   header;
 619        struct i40e_aqc_switch_config_element_resp      element[1];
 620};
 621
 622I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
 623
 624/* Add Statistics (direct 0x0201)
 625 * Remove Statistics (direct 0x0202)
 626 */
 627struct i40e_aqc_add_remove_statistics {
 628        __le16  seid;
 629        __le16  vlan;
 630        __le16  stat_index;
 631        u8      reserved[10];
 632};
 633
 634I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
 635
 636/* Set Port Parameters command (direct 0x0203) */
 637struct i40e_aqc_set_port_parameters {
 638        __le16  command_flags;
 639#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS   1
 640#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS  2 /* must set! */
 641#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA    4
 642        __le16  bad_frame_vsi;
 643        __le16  default_seid;        /* reserved for command */
 644        u8      reserved[10];
 645};
 646
 647I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
 648
 649/* Get Switch Resource Allocation (indirect 0x0204) */
 650struct i40e_aqc_get_switch_resource_alloc {
 651        u8      num_entries;         /* reserved for command */
 652        u8      reserved[7];
 653        __le32  addr_high;
 654        __le32  addr_low;
 655};
 656
 657I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
 658
 659/* expect an array of these structs in the response buffer */
 660struct i40e_aqc_switch_resource_alloc_element_resp {
 661        u8      resource_type;
 662#define I40E_AQ_RESOURCE_TYPE_VEB               0x0
 663#define I40E_AQ_RESOURCE_TYPE_VSI               0x1
 664#define I40E_AQ_RESOURCE_TYPE_MACADDR           0x2
 665#define I40E_AQ_RESOURCE_TYPE_STAG              0x3
 666#define I40E_AQ_RESOURCE_TYPE_ETAG              0x4
 667#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH    0x5
 668#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH      0x6
 669#define I40E_AQ_RESOURCE_TYPE_VLAN              0x7
 670#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY    0x8
 671#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY   0x9
 672#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL    0xA
 673#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE       0xB
 674#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS        0xC
 675#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS      0xD
 676#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
 677#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS        0x10
 678#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS       0x11
 679#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS          0x12
 680#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS      0x13
 681        u8      reserved1;
 682        __le16  guaranteed;
 683        __le16  total;
 684        __le16  used;
 685        __le16  total_unalloced;
 686        u8      reserved2[6];
 687};
 688
 689I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
 690
 691/* Set Switch Configuration (direct 0x0205) */
 692struct i40e_aqc_set_switch_config {
 693        __le16  flags;
 694#define I40E_AQ_SET_SWITCH_CFG_PROMISC          0x0001
 695#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER        0x0002
 696        __le16  valid_flags;
 697        u8      reserved[12];
 698};
 699
 700I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
 701
 702/* Read Receive control registers  (direct 0x0206)
 703 * Write Receive control registers (direct 0x0207)
 704 *     used for accessing Rx control registers that can be
 705 *     slow and need special handling when under high Rx load
 706 */
 707struct i40e_aqc_rx_ctl_reg_read_write {
 708        __le32 reserved1;
 709        __le32 address;
 710        __le32 reserved2;
 711        __le32 value;
 712};
 713
 714I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
 715
 716/* Add VSI (indirect 0x0210)
 717 *    this indirect command uses struct i40e_aqc_vsi_properties_data
 718 *    as the indirect buffer (128 bytes)
 719 *
 720 * Update VSI (indirect 0x211)
 721 *     uses the same data structure as Add VSI
 722 *
 723 * Get VSI (indirect 0x0212)
 724 *     uses the same completion and data structure as Add VSI
 725 */
 726struct i40e_aqc_add_get_update_vsi {
 727        __le16  uplink_seid;
 728        u8      connection_type;
 729#define I40E_AQ_VSI_CONN_TYPE_NORMAL    0x1
 730#define I40E_AQ_VSI_CONN_TYPE_DEFAULT   0x2
 731#define I40E_AQ_VSI_CONN_TYPE_CASCADED  0x3
 732        u8      reserved1;
 733        u8      vf_id;
 734        u8      reserved2;
 735        __le16  vsi_flags;
 736#define I40E_AQ_VSI_TYPE_SHIFT          0x0
 737#define I40E_AQ_VSI_TYPE_MASK           (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
 738#define I40E_AQ_VSI_TYPE_VF             0x0
 739#define I40E_AQ_VSI_TYPE_VMDQ2          0x1
 740#define I40E_AQ_VSI_TYPE_PF             0x2
 741#define I40E_AQ_VSI_TYPE_EMP_MNG        0x3
 742#define I40E_AQ_VSI_FLAG_CASCADED_PV    0x4
 743        __le32  addr_high;
 744        __le32  addr_low;
 745};
 746
 747I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
 748
 749struct i40e_aqc_add_get_update_vsi_completion {
 750        __le16 seid;
 751        __le16 vsi_number;
 752        __le16 vsi_used;
 753        __le16 vsi_free;
 754        __le32 addr_high;
 755        __le32 addr_low;
 756};
 757
 758I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
 759
 760struct i40e_aqc_vsi_properties_data {
 761        /* first 96 byte are written by SW */
 762        __le16  valid_sections;
 763#define I40E_AQ_VSI_PROP_SWITCH_VALID           0x0001
 764#define I40E_AQ_VSI_PROP_SECURITY_VALID         0x0002
 765#define I40E_AQ_VSI_PROP_VLAN_VALID             0x0004
 766#define I40E_AQ_VSI_PROP_CAS_PV_VALID           0x0008
 767#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID       0x0010
 768#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID        0x0020
 769#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID        0x0040
 770#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID        0x0080
 771#define I40E_AQ_VSI_PROP_OUTER_UP_VALID         0x0100
 772#define I40E_AQ_VSI_PROP_SCHED_VALID            0x0200
 773        /* switch section */
 774        __le16  switch_id; /* 12bit id combined with flags below */
 775#define I40E_AQ_VSI_SW_ID_SHIFT         0x0000
 776#define I40E_AQ_VSI_SW_ID_MASK          (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
 777#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
 778#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
 779#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
 780        u8      sw_reserved[2];
 781        /* security section */
 782        u8      sec_flags;
 783#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD    0x01
 784#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK    0x02
 785#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK     0x04
 786        u8      sec_reserved;
 787        /* VLAN section */
 788        __le16  pvid; /* VLANS include priority bits */
 789        __le16  fcoe_pvid;
 790        u8      port_vlan_flags;
 791#define I40E_AQ_VSI_PVLAN_MODE_SHIFT    0x00
 792#define I40E_AQ_VSI_PVLAN_MODE_MASK     (0x03 << \
 793                                         I40E_AQ_VSI_PVLAN_MODE_SHIFT)
 794#define I40E_AQ_VSI_PVLAN_MODE_TAGGED   0x01
 795#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
 796#define I40E_AQ_VSI_PVLAN_MODE_ALL      0x03
 797#define I40E_AQ_VSI_PVLAN_INSERT_PVID   0x04
 798#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT    0x03
 799#define I40E_AQ_VSI_PVLAN_EMOD_MASK     (0x3 << \
 800                                         I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
 801#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
 802#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP   0x08
 803#define I40E_AQ_VSI_PVLAN_EMOD_STR      0x10
 804#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING  0x18
 805        u8      pvlan_reserved[3];
 806        /* ingress egress up sections */
 807        __le32  ingress_table; /* bitmap, 3 bits per up */
 808#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT  0
 809#define I40E_AQ_VSI_UP_TABLE_UP0_MASK   (0x7 << \
 810                                         I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
 811#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT  3
 812#define I40E_AQ_VSI_UP_TABLE_UP1_MASK   (0x7 << \
 813                                         I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
 814#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT  6
 815#define I40E_AQ_VSI_UP_TABLE_UP2_MASK   (0x7 << \
 816                                         I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
 817#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT  9
 818#define I40E_AQ_VSI_UP_TABLE_UP3_MASK   (0x7 << \
 819                                         I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
 820#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT  12
 821#define I40E_AQ_VSI_UP_TABLE_UP4_MASK   (0x7 << \
 822                                         I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
 823#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT  15
 824#define I40E_AQ_VSI_UP_TABLE_UP5_MASK   (0x7 << \
 825                                         I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
 826#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT  18
 827#define I40E_AQ_VSI_UP_TABLE_UP6_MASK   (0x7 << \
 828                                         I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
 829#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT  21
 830#define I40E_AQ_VSI_UP_TABLE_UP7_MASK   (0x7 << \
 831                                         I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
 832        __le32  egress_table;   /* same defines as for ingress table */
 833        /* cascaded PV section */
 834        __le16  cas_pv_tag;
 835        u8      cas_pv_flags;
 836#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT           0x00
 837#define I40E_AQ_VSI_CAS_PV_TAGX_MASK            (0x03 << \
 838                                                 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
 839#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE           0x00
 840#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE          0x01
 841#define I40E_AQ_VSI_CAS_PV_TAGX_COPY            0x02
 842#define I40E_AQ_VSI_CAS_PV_INSERT_TAG           0x10
 843#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE           0x20
 844#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG      0x40
 845        u8      cas_pv_reserved;
 846        /* queue mapping section */
 847        __le16  mapping_flags;
 848#define I40E_AQ_VSI_QUE_MAP_CONTIG      0x0
 849#define I40E_AQ_VSI_QUE_MAP_NONCONTIG   0x1
 850        __le16  queue_mapping[16];
 851#define I40E_AQ_VSI_QUEUE_SHIFT         0x0
 852#define I40E_AQ_VSI_QUEUE_MASK          (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
 853        __le16  tc_mapping[8];
 854#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
 855#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK  (0x1FF << \
 856                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
 857#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
 858#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK  (0x7 << \
 859                                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
 860        /* queueing option section */
 861        u8      queueing_opt_flags;
 862#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA   0x04
 863#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA     0x08
 864#define I40E_AQ_VSI_QUE_OPT_TCP_ENA     0x10
 865#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA    0x20
 866#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF  0x00
 867#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
 868        u8      queueing_opt_reserved[3];
 869        /* scheduler section */
 870        u8      up_enable_bits;
 871        u8      sched_reserved;
 872        /* outer up section */
 873        __le32  outer_up_table; /* same structure and defines as ingress tbl */
 874        u8      cmd_reserved[8];
 875        /* last 32 bytes are written by FW */
 876        __le16  qs_handle[8];
 877#define I40E_AQ_VSI_QS_HANDLE_INVALID   0xFFFF
 878        __le16  stat_counter_idx;
 879        __le16  sched_id;
 880        u8      resp_reserved[12];
 881};
 882
 883I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
 884
 885/* Add Port Virtualizer (direct 0x0220)
 886 * also used for update PV (direct 0x0221) but only flags are used
 887 * (IS_CTRL_PORT only works on add PV)
 888 */
 889struct i40e_aqc_add_update_pv {
 890        __le16  command_flags;
 891#define I40E_AQC_PV_FLAG_PV_TYPE                0x1
 892#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN    0x2
 893#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN    0x4
 894#define I40E_AQC_PV_FLAG_IS_CTRL_PORT           0x8
 895        __le16  uplink_seid;
 896        __le16  connected_seid;
 897        u8      reserved[10];
 898};
 899
 900I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
 901
 902struct i40e_aqc_add_update_pv_completion {
 903        /* reserved for update; for add also encodes error if rc == ENOSPC */
 904        __le16  pv_seid;
 905#define I40E_AQC_PV_ERR_FLAG_NO_PV      0x1
 906#define I40E_AQC_PV_ERR_FLAG_NO_SCHED   0x2
 907#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
 908#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY   0x8
 909        u8      reserved[14];
 910};
 911
 912I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
 913
 914/* Get PV Params (direct 0x0222)
 915 * uses i40e_aqc_switch_seid for the descriptor
 916 */
 917
 918struct i40e_aqc_get_pv_params_completion {
 919        __le16  seid;
 920        __le16  default_stag;
 921        __le16  pv_flags; /* same flags as add_pv */
 922#define I40E_AQC_GET_PV_PV_TYPE                 0x1
 923#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG       0x2
 924#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG       0x4
 925        u8      reserved[8];
 926        __le16  default_port_seid;
 927};
 928
 929I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
 930
 931/* Add VEB (direct 0x0230) */
 932struct i40e_aqc_add_veb {
 933        __le16  uplink_seid;
 934        __le16  downlink_seid;
 935        __le16  veb_flags;
 936#define I40E_AQC_ADD_VEB_FLOATING               0x1
 937#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT        1
 938#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK         (0x3 << \
 939                                        I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
 940#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT      0x2
 941#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA         0x4
 942#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER       0x8     /* deprecated */
 943#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS   0x10
 944        u8      enable_tcs;
 945        u8      reserved[9];
 946};
 947
 948I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
 949
 950struct i40e_aqc_add_veb_completion {
 951        u8      reserved[6];
 952        __le16  switch_seid;
 953        /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
 954        __le16  veb_seid;
 955#define I40E_AQC_VEB_ERR_FLAG_NO_VEB            0x1
 956#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED          0x2
 957#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER        0x4
 958#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY          0x8
 959        __le16  statistic_index;
 960        __le16  vebs_used;
 961        __le16  vebs_free;
 962};
 963
 964I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
 965
 966/* Get VEB Parameters (direct 0x0232)
 967 * uses i40e_aqc_switch_seid for the descriptor
 968 */
 969struct i40e_aqc_get_veb_parameters_completion {
 970        __le16  seid;
 971        __le16  switch_id;
 972        __le16  veb_flags; /* only the first/last flags from 0x0230 is valid */
 973        __le16  statistic_index;
 974        __le16  vebs_used;
 975        __le16  vebs_free;
 976        u8      reserved[4];
 977};
 978
 979I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
 980
 981/* Delete Element (direct 0x0243)
 982 * uses the generic i40e_aqc_switch_seid
 983 */
 984
 985/* Add MAC-VLAN (indirect 0x0250) */
 986
 987/* used for the command for most vlan commands */
 988struct i40e_aqc_macvlan {
 989        __le16  num_addresses;
 990        __le16  seid[3];
 991#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT     0
 992#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK      (0x3FF << \
 993                                        I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
 994#define I40E_AQC_MACVLAN_CMD_SEID_VALID         0x8000
 995        __le32  addr_high;
 996        __le32  addr_low;
 997};
 998
 999I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1000

1001/* indirect data for command and response */
1002struct i40e_aqc_add_macvlan_element_data {
1003        u8      mac_addr[6];
1004        __le16  vlan_tag;
1005        __le16  flags;
1006#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH      0x0001
1007#define I40E_AQC_MACVLAN_ADD_HASH_MATCH         0x0002
1008#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN        0x0004
1009#define I40E_AQC_MACVLAN_ADD_TO_QUEUE           0x0008
1010#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC     0x0010
1011        __le16  queue_number;
1012#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT        0
1013#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK         (0x7FF << \
1014                                        I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1015        /* response section */
1016        u8      match_method;
1017#define I40E_AQC_MM_PERFECT_MATCH       0x01
1018#define I40E_AQC_MM_HASH_MATCH          0x02
1019#define I40E_AQC_MM_ERR_NO_RES          0xFF
1020        u8      reserved1[3];
1021};
1022
1023struct i40e_aqc_add_remove_macvlan_completion {
1024        __le16 perfect_mac_used;
1025        __le16 perfect_mac_free;
1026        __le16 unicast_hash_free;
1027        __le16 multicast_hash_free;
1028        __le32 addr_high;
1029        __le32 addr_low;
1030};
1031
1032I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1033
1034/* Remove MAC-VLAN (indirect 0x0251)
1035 * uses i40e_aqc_macvlan for the descriptor
1036 * data points to an array of num_addresses of elements
1037 */
1038
1039struct i40e_aqc_remove_macvlan_element_data {
1040        u8      mac_addr[6];
1041        __le16  vlan_tag;
1042        u8      flags;
1043#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH      0x01
1044#define I40E_AQC_MACVLAN_DEL_HASH_MATCH         0x02
1045#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN        0x08
1046#define I40E_AQC_MACVLAN_DEL_ALL_VSIS           0x10
1047        u8      reserved[3];
1048        /* reply section */
1049        u8      error_code;
1050#define I40E_AQC_REMOVE_MACVLAN_SUCCESS         0x0
1051#define I40E_AQC_REMOVE_MACVLAN_FAIL            0xFF
1052        u8      reply_reserved[3];
1053};
1054
1055/* Add VLAN (indirect 0x0252)
1056 * Remove VLAN (indirect 0x0253)
1057 * use the generic i40e_aqc_macvlan for the command
1058 */
1059struct i40e_aqc_add_remove_vlan_element_data {
1060        __le16  vlan_tag;
1061        u8      vlan_flags;
1062/* flags for add VLAN */
1063#define I40E_AQC_ADD_VLAN_LOCAL                 0x1
1064#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT           1
1065#define I40E_AQC_ADD_PVLAN_TYPE_MASK    (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1066#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR         0x0
1067#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY         0x2
1068#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY       0x4
1069#define I40E_AQC_VLAN_PTYPE_SHIFT               3
1070#define I40E_AQC_VLAN_PTYPE_MASK        (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1071#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI         0x0
1072#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI         0x8
1073#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI       0x10
1074#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI        0x18
1075/* flags for remove VLAN */
1076#define I40E_AQC_REMOVE_VLAN_ALL        0x1
1077        u8      reserved;
1078        u8      result;
1079/* flags for add VLAN */
1080#define I40E_AQC_ADD_VLAN_SUCCESS       0x0
1081#define I40E_AQC_ADD_VLAN_FAIL_REQUEST  0xFE
1082#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1083/* flags for remove VLAN */
1084#define I40E_AQC_REMOVE_VLAN_SUCCESS    0x0
1085#define I40E_AQC_REMOVE_VLAN_FAIL       0xFF
1086        u8      reserved1[3];
1087};
1088
1089struct i40e_aqc_add_remove_vlan_completion {
1090        u8      reserved[4];
1091        __le16  vlans_used;
1092        __le16  vlans_free;
1093        __le32  addr_high;
1094        __le32  addr_low;
1095};
1096
1097/* Set VSI Promiscuous Modes (direct 0x0254) */
1098struct i40e_aqc_set_vsi_promiscuous_modes {
1099        __le16  promiscuous_flags;
1100        __le16  valid_flags;
1101/* flags used for both fields above */
1102#define I40E_AQC_SET_VSI_PROMISC_UNICAST        0x01
1103#define I40E_AQC_SET_VSI_PROMISC_MULTICAST      0x02
1104#define I40E_AQC_SET_VSI_PROMISC_BROADCAST      0x04
1105#define I40E_AQC_SET_VSI_DEFAULT                0x08
1106#define I40E_AQC_SET_VSI_PROMISC_VLAN           0x10
1107#define I40E_AQC_SET_VSI_PROMISC_TX             0x8000
1108        __le16  seid;
1109#define I40E_AQC_VSI_PROM_CMD_SEID_MASK         0x3FF
1110        __le16  vlan_tag;
1111#define I40E_AQC_SET_VSI_VLAN_MASK              0x0FFF
1112#define I40E_AQC_SET_VSI_VLAN_VALID             0x8000
1113        u8      reserved[8];
1114};
1115
1116I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1117
1118/* Add S/E-tag command (direct 0x0255)
1119 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1120 */
1121struct i40e_aqc_add_tag {
1122        __le16  flags;
1123#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE          0x0001
1124        __le16  seid;
1125#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT     0
1126#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK      (0x3FF << \
1127                                        I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1128        __le16  tag;
1129        __le16  queue_number;
1130        u8      reserved[8];
1131};
1132
1133I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1134
1135struct i40e_aqc_add_remove_tag_completion {
1136        u8      reserved[12];
1137        __le16  tags_used;
1138        __le16  tags_free;
1139};
1140
1141I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1142
1143/* Remove S/E-tag command (direct 0x0256)
1144 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1145 */
1146struct i40e_aqc_remove_tag {
1147        __le16  seid;
1148#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT  0
1149#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK   (0x3FF << \
1150                                        I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1151        __le16  tag;
1152        u8      reserved[12];
1153};
1154
1155I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1156
1157/* Add multicast E-Tag (direct 0x0257)
1158 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1159 * and no external data
1160 */
1161struct i40e_aqc_add_remove_mcast_etag {
1162        __le16  pv_seid;
1163        __le16  etag;
1164        u8      num_unicast_etags;
1165        u8      reserved[3];
1166        __le32  addr_high;          /* address of array of 2-byte s-tags */
1167        __le32  addr_low;
1168};
1169
1170I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1171
1172struct i40e_aqc_add_remove_mcast_etag_completion {
1173        u8      reserved[4];
1174        __le16  mcast_etags_used;
1175        __le16  mcast_etags_free;
1176        __le32  addr_high;
1177        __le32  addr_low;
1178
1179};
1180
1181I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1182
1183/* Update S/E-Tag (direct 0x0259) */
1184struct i40e_aqc_update_tag {
1185        __le16  seid;
1186#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT  0
1187#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK   (0x3FF << \
1188                                        I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1189        __le16  old_tag;
1190        __le16  new_tag;
1191        u8      reserved[10];
1192};
1193
1194I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1195
1196struct i40e_aqc_update_tag_completion {
1197        u8      reserved[12];
1198        __le16  tags_used;
1199        __le16  tags_free;
1200};
1201
1202I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1203
1204/* Add Control Packet filter (direct 0x025A)
1205 * Remove Control Packet filter (direct 0x025B)
1206 * uses the i40e_aqc_add_oveb_cloud,
1207 * and the generic direct completion structure
1208 */
1209struct i40e_aqc_add_remove_control_packet_filter {
1210        u8      mac[6];
1211        __le16  etype;
1212        __le16  flags;
1213#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC    0x0001
1214#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP          0x0002
1215#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE      0x0004
1216#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX            0x0008
1217#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX            0x0000
1218        __le16  seid;
1219#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT  0
1220#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK   (0x3FF << \
1221                                I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1222        __le16  queue;
1223        u8      reserved[2];
1224};
1225
1226I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1227
1228struct i40e_aqc_add_remove_control_packet_filter_completion {
1229        __le16  mac_etype_used;
1230        __le16  etype_used;
1231        __le16  mac_etype_free;
1232        __le16  etype_free;
1233        u8      reserved[8];
1234};
1235
1236I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1237
1238/* Add Cloud filters (indirect 0x025C)
1239 * Remove Cloud filters (indirect 0x025D)
1240 * uses the i40e_aqc_add_remove_cloud_filters,
1241 * and the generic indirect completion structure
1242 */
1243struct i40e_aqc_add_remove_cloud_filters {
1244        u8      num_filters;
1245        u8      reserved;
1246        __le16  seid;
1247#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT   0
1248#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK    (0x3FF << \
1249                                        I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1250        u8      reserved2[4];
1251        __le32  addr_high;
1252        __le32  addr_low;
1253};
1254
1255I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1256
1257struct i40e_aqc_add_remove_cloud_filters_element_data {
1258        u8      outer_mac[6];
1259        u8      inner_mac[6];
1260        __le16  inner_vlan;
1261        union {
1262                struct {
1263                        u8 reserved[12];
1264                        u8 data[4];
1265                } v4;
1266                struct {
1267                        u8 data[16];
1268                } v6;
1269        } ipaddr;
1270        __le16  flags;
1271#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT                 0
1272#define I40E_AQC_ADD_CLOUD_FILTER_MASK  (0x3F << \
1273                                        I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1274/* 0x0000 reserved */
1275#define I40E_AQC_ADD_CLOUD_FILTER_OIP                   0x0001
1276/* 0x0002 reserved */
1277#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN            0x0003
1278#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID     0x0004
1279/* 0x0005 reserved */
1280#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID           0x0006
1281/* 0x0007 reserved */
1282/* 0x0008 reserved */
1283#define I40E_AQC_ADD_CLOUD_FILTER_OMAC                  0x0009
1284#define I40E_AQC_ADD_CLOUD_FILTER_IMAC                  0x000A
1285#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC      0x000B
1286#define I40E_AQC_ADD_CLOUD_FILTER_IIP                   0x000C
1287
1288#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE               0x0080
1289#define I40E_AQC_ADD_CLOUD_VNK_SHIFT                    6
1290#define I40E_AQC_ADD_CLOUD_VNK_MASK                     0x00C0
1291#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4                   0
1292#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6                   0x0100
1293
1294#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT               9
1295#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK                0x1E00
1296#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN               0
1297#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC          1
1298#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE              2
1299#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP                  3
1300#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED            4
1301#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE           5
1302
1303#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC       0x2000
1304#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC       0x4000
1305#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP        0x8000
1306
1307        __le32  tenant_id;
1308        u8      reserved[4];
1309        __le16  queue_number;
1310#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT          0
1311#define I40E_AQC_ADD_CLOUD_QUEUE_MASK           (0x7FF << \
1312                                                 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1313        u8      reserved2[14];
1314        /* response section */
1315        u8      allocation_result;
1316#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS       0x0
1317#define I40E_AQC_ADD_CLOUD_FILTER_FAIL          0xFF
1318        u8      response_reserved[7];
1319};
1320
1321struct i40e_aqc_remove_cloud_filters_completion {
1322        __le16 perfect_ovlan_used;
1323        __le16 perfect_ovlan_free;
1324        __le16 vlan_used;
1325        __le16 vlan_free;
1326        __le32 addr_high;
1327        __le32 addr_low;
1328};
1329
1330I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1331
1332/* Add Mirror Rule (indirect or direct 0x0260)
1333 * Delete Mirror Rule (indirect or direct 0x0261)
1334 * note: some rule types (4,5) do not use an external buffer.
1335 *       take care to set the flags correctly.
1336 */
1337struct i40e_aqc_add_delete_mirror_rule {
1338        __le16 seid;
1339        __le16 rule_type;
1340#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT         0
1341#define I40E_AQC_MIRROR_RULE_TYPE_MASK          (0x7 << \
1342                                                I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1343#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1344#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS  2
1345#define I40E_AQC_MIRROR_RULE_TYPE_VLAN          3
1346#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS   4
1347#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS    5
1348        __le16 num_entries;
1349        __le16 destination;  /* VSI for add, rule id for delete */
1350        __le32 addr_high;    /* address of array of 2-byte VSI or VLAN ids */
1351        __le32 addr_low;
1352};
1353
1354I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1355
1356struct i40e_aqc_add_delete_mirror_rule_completion {
1357        u8      reserved[2];
1358        __le16  rule_id;  /* only used on add */
1359        __le16  mirror_rules_used;
1360        __le16  mirror_rules_free;
1361        __le32  addr_high;
1362        __le32  addr_low;
1363};
1364
1365I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1366
1367/* DCB 0x03xx*/
1368
1369/* PFC Ignore (direct 0x0301)
1370 *    the command and response use the same descriptor structure
1371 */
1372struct i40e_aqc_pfc_ignore {
1373        u8      tc_bitmap;
1374        u8      command_flags; /* unused on response */
1375#define I40E_AQC_PFC_IGNORE_SET         0x80
1376#define I40E_AQC_PFC_IGNORE_CLEAR       0x0
1377        u8      reserved[14];
1378};
1379
1380I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1381
1382/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1383 * with no parameters
1384 */
1385
1386/* TX scheduler 0x04xx */
1387
1388/* Almost all the indirect commands use
1389 * this generic struct to pass the SEID in param0
1390 */
1391struct i40e_aqc_tx_sched_ind {
1392        __le16  vsi_seid;
1393        u8      reserved[6];
1394        __le32  addr_high;
1395        __le32  addr_low;
1396};
1397
1398I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1399
1400/* Several commands respond with a set of queue set handles */
1401struct i40e_aqc_qs_handles_resp {
1402        __le16 qs_handles[8];
1403};
1404
1405/* Configure VSI BW limits (direct 0x0400) */
1406struct i40e_aqc_configure_vsi_bw_limit {
1407        __le16  vsi_seid;
1408        u8      reserved[2];
1409        __le16  credit;
1410        u8      reserved1[2];
1411        u8      max_credit; /* 0-3, limit = 2^max */
1412        u8      reserved2[7];
1413};
1414
1415I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1416
1417/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1418 *    responds with i40e_aqc_qs_handles_resp
1419 */
1420struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1421        u8      tc_valid_bits;
1422        u8      reserved[15];
1423        __le16  tc_bw_credits[8]; /* FW writesback QS handles here */
1424
1425        /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1426        __le16  tc_bw_max[2];
1427        u8      reserved1[28];
1428};
1429
1430I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1431
1432/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1433 *    responds with i40e_aqc_qs_handles_resp
1434 */
1435struct i40e_aqc_configure_vsi_tc_bw_data {
1436        u8      tc_valid_bits;
1437        u8      reserved[3];
1438        u8      tc_bw_credits[8];
1439        u8      reserved1[4];
1440        __le16  qs_handles[8];
1441};
1442
1443I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1444
1445/* Query vsi bw configuration (indirect 0x0408) */
1446struct i40e_aqc_query_vsi_bw_config_resp {
1447        u8      tc_valid_bits;
1448        u8      tc_suspended_bits;
1449        u8      reserved[14];
1450        __le16  qs_handles[8];
1451        u8      reserved1[4];
1452        __le16  port_bw_limit;
1453        u8      reserved2[2];
1454        u8      max_bw; /* 0-3, limit = 2^max */
1455        u8      reserved3[23];
1456};
1457
1458I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1459
1460/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1461struct i40e_aqc_query_vsi_ets_sla_config_resp {
1462        u8      tc_valid_bits;
1463        u8      reserved[3];
1464        u8      share_credits[8];
1465        __le16  credits[8];
1466
1467        /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1468        __le16  tc_bw_max[2];
1469};
1470
1471I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1472
1473/* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1474struct i40e_aqc_configure_switching_comp_bw_limit {
1475        __le16  seid;
1476        u8      reserved[2];
1477        __le16  credit;
1478        u8      reserved1[2];
1479        u8      max_bw; /* 0-3, limit = 2^max */
1480        u8      reserved2[7];
1481};
1482
1483I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1484
1485/* Enable  Physical Port ETS (indirect 0x0413)
1486 * Modify  Physical Port ETS (indirect 0x0414)
1487 * Disable Physical Port ETS (indirect 0x0415)
1488 */
1489struct i40e_aqc_configure_switching_comp_ets_data {
1490        u8      reserved[4];
1491        u8      tc_valid_bits;
1492        u8      seepage;
1493#define I40E_AQ_ETS_SEEPAGE_EN_MASK     0x1
1494        u8      tc_strict_priority_flags;
1495        u8      reserved1[17];
1496        u8      tc_bw_share_credits[8];
1497        u8      reserved2[96];
1498};
1499
1500I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1501
1502/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1503struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1504        u8      tc_valid_bits;
1505        u8      reserved[15];
1506        __le16  tc_bw_credit[8];
1507
1508        /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1509        __le16  tc_bw_max[2];
1510        u8      reserved1[28];
1511};
1512
1513I40E_CHECK_STRUCT_LEN(0x40,
1514                      i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1515
1516/* Configure Switching Component Bandwidth Allocation per Tc
1517 * (indirect 0x0417)
1518 */
1519struct i40e_aqc_configure_switching_comp_bw_config_data {
1520        u8      tc_valid_bits;
1521        u8      reserved[2];
1522        u8      absolute_credits; /* bool */
1523        u8      tc_bw_share_credits[8];
1524        u8      reserved1[20];
1525};
1526
1527I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1528
1529/* Query Switching Component Configuration (indirect 0x0418) */
1530struct i40e_aqc_query_switching_comp_ets_config_resp {
1531        u8      tc_valid_bits;
1532        u8      reserved[35];
1533        __le16  port_bw_limit;
1534        u8      reserved1[2];
1535        u8      tc_bw_max; /* 0-3, limit = 2^max */
1536        u8      reserved2[23];
1537};
1538
1539I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1540
1541/* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1542struct i40e_aqc_query_port_ets_config_resp {
1543        u8      reserved[4];
1544        u8      tc_valid_bits;
1545        u8      reserved1;
1546        u8      tc_strict_priority_bits;
1547        u8      reserved2;
1548        u8      tc_bw_share_credits[8];
1549        __le16  tc_bw_limits[8];
1550
1551        /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1552        __le16  tc_bw_max[2];
1553        u8      reserved3[32];
1554};
1555
1556I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1557
1558/* Query Switching Component Bandwidth Allocation per Traffic Type
1559 * (indirect 0x041A)
1560 */
1561struct i40e_aqc_query_switching_comp_bw_config_resp {
1562        u8      tc_valid_bits;
1563        u8      reserved[2];
1564        u8      absolute_credits_enable; /* bool */
1565        u8      tc_bw_share_credits[8];
1566        __le16  tc_bw_limits[8];
1567
1568        /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1569        __le16  tc_bw_max[2];
1570};
1571
1572I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1573
1574/* Suspend/resume port TX traffic
1575 * (direct 0x041B and 0x041C) uses the generic SEID struct
1576 */
1577
1578/* Configure partition BW
1579 * (indirect 0x041D)
1580 */
1581struct i40e_aqc_configure_partition_bw_data {
1582        __le16  pf_valid_bits;
1583        u8      min_bw[16];      /* guaranteed bandwidth */
1584        u8      max_bw[16];      /* bandwidth limit */
1585};
1586
1587I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1588
1589/* Get and set the active HMC resource profile and status.
1590 * (direct 0x0500) and (direct 0x0501)
1591 */
1592struct i40e_aq_get_set_hmc_resource_profile {
1593        u8      pm_profile;
1594        u8      pe_vf_enabled;
1595        u8      reserved[14];
1596};
1597
1598I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1599
1600enum i40e_aq_hmc_profile {
1601        /* I40E_HMC_PROFILE_NO_CHANGE   = 0, reserved */
1602        I40E_HMC_PROFILE_DEFAULT        = 1,
1603        I40E_HMC_PROFILE_FAVOR_VF       = 2,
1604        I40E_HMC_PROFILE_EQUAL          = 3,
1605};
1606
1607/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1608
1609/* set in param0 for get phy abilities to report qualified modules */
1610#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES    0x0001
1611#define I40E_AQ_PHY_REPORT_INITIAL_VALUES       0x0002
1612
1613enum i40e_aq_phy_type {
1614        I40E_PHY_TYPE_SGMII                     = 0x0,
1615        I40E_PHY_TYPE_1000BASE_KX               = 0x1,
1616        I40E_PHY_TYPE_10GBASE_KX4               = 0x2,
1617        I40E_PHY_TYPE_10GBASE_KR                = 0x3,
1618        I40E_PHY_TYPE_40GBASE_KR4               = 0x4,
1619        I40E_PHY_TYPE_XAUI                      = 0x5,
1620        I40E_PHY_TYPE_XFI                       = 0x6,
1621        I40E_PHY_TYPE_SFI                       = 0x7,
1622        I40E_PHY_TYPE_XLAUI                     = 0x8,
1623        I40E_PHY_TYPE_XLPPI                     = 0x9,
1624        I40E_PHY_TYPE_40GBASE_CR4_CU            = 0xA,
1625        I40E_PHY_TYPE_10GBASE_CR1_CU            = 0xB,
1626        I40E_PHY_TYPE_10GBASE_AOC               = 0xC,
1627        I40E_PHY_TYPE_40GBASE_AOC               = 0xD,
1628        I40E_PHY_TYPE_100BASE_TX                = 0x11,
1629        I40E_PHY_TYPE_1000BASE_T                = 0x12,
1630        I40E_PHY_TYPE_10GBASE_T                 = 0x13,
1631        I40E_PHY_TYPE_10GBASE_SR                = 0x14,
1632        I40E_PHY_TYPE_10GBASE_LR                = 0x15,
1633        I40E_PHY_TYPE_10GBASE_SFPP_CU           = 0x16,
1634        I40E_PHY_TYPE_10GBASE_CR1               = 0x17,
1635        I40E_PHY_TYPE_40GBASE_CR4               = 0x18,
1636        I40E_PHY_TYPE_40GBASE_SR4               = 0x19,
1637        I40E_PHY_TYPE_40GBASE_LR4               = 0x1A,
1638        I40E_PHY_TYPE_1000BASE_SX               = 0x1B,
1639        I40E_PHY_TYPE_1000BASE_LX               = 0x1C,
1640        I40E_PHY_TYPE_1000BASE_T_OPTICAL        = 0x1D,
1641        I40E_PHY_TYPE_20GBASE_KR2               = 0x1E,
1642        I40E_PHY_TYPE_MAX
1643};
1644
1645#define I40E_LINK_SPEED_100MB_SHIFT     0x1
1646#define I40E_LINK_SPEED_1000MB_SHIFT    0x2
1647#define I40E_LINK_SPEED_10GB_SHIFT      0x3
1648#define I40E_LINK_SPEED_40GB_SHIFT      0x4
1649#define I40E_LINK_SPEED_20GB_SHIFT      0x5
1650
1651enum i40e_aq_link_speed {
1652        I40E_LINK_SPEED_UNKNOWN = 0,
1653        I40E_LINK_SPEED_100MB   = BIT(I40E_LINK_SPEED_100MB_SHIFT),
1654        I40E_LINK_SPEED_1GB     = BIT(I40E_LINK_SPEED_1000MB_SHIFT),
1655        I40E_LINK_SPEED_10GB    = BIT(I40E_LINK_SPEED_10GB_SHIFT),
1656        I40E_LINK_SPEED_40GB    = BIT(I40E_LINK_SPEED_40GB_SHIFT),
1657        I40E_LINK_SPEED_20GB    = BIT(I40E_LINK_SPEED_20GB_SHIFT)
1658};
1659
1660struct i40e_aqc_module_desc {
1661        u8 oui[3];
1662        u8 reserved1;
1663        u8 part_number[16];
1664        u8 revision[4];
1665        u8 reserved2[8];
1666};
1667
1668I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1669
1670struct i40e_aq_get_phy_abilities_resp {
1671        __le32  phy_type;       /* bitmap using the above enum for offsets */
1672        u8      link_speed;     /* bitmap using the above enum bit patterns */
1673        u8      abilities;
1674#define I40E_AQ_PHY_FLAG_PAUSE_TX       0x01
1675#define I40E_AQ_PHY_FLAG_PAUSE_RX       0x02
1676#define I40E_AQ_PHY_FLAG_LOW_POWER      0x04
1677#define I40E_AQ_PHY_LINK_ENABLED        0x08
1678#define I40E_AQ_PHY_AN_ENABLED          0x10
1679#define I40E_AQ_PHY_FLAG_MODULE_QUAL    0x20
1680        __le16  eee_capability;
1681#define I40E_AQ_EEE_100BASE_TX          0x0002
1682#define I40E_AQ_EEE_1000BASE_T          0x0004
1683#define I40E_AQ_EEE_10GBASE_T           0x0008
1684#define I40E_AQ_EEE_1000BASE_KX         0x0010
1685#define I40E_AQ_EEE_10GBASE_KX4         0x0020
1686#define I40E_AQ_EEE_10GBASE_KR          0x0040
1687        __le32  eeer_val;
1688        u8      d3_lpan;
1689#define I40E_AQ_SET_PHY_D3_LPAN_ENA     0x01
1690        u8      reserved[3];
1691        u8      phy_id[4];
1692        u8      module_type[3];
1693        u8      qualified_module_count;
1694#define I40E_AQ_PHY_MAX_QMS             16
1695        struct i40e_aqc_module_desc     qualified_module[I40E_AQ_PHY_MAX_QMS];
1696};
1697
1698I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1699
1700/* Set PHY Config (direct 0x0601) */
1701struct i40e_aq_set_phy_config { /* same bits as above in all */
1702        __le32  phy_type;
1703        u8      link_speed;
1704        u8      abilities;
1705/* bits 0-2 use the values from get_phy_abilities_resp */
1706#define I40E_AQ_PHY_ENABLE_LINK         0x08
1707#define I40E_AQ_PHY_ENABLE_AN           0x10
1708#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK  0x20
1709        __le16  eee_capability;
1710        __le32  eeer;
1711        u8      low_power_ctrl;
1712        u8      reserved[3];
1713};
1714
1715I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1716
1717/* Set MAC Config command data structure (direct 0x0603) */
1718struct i40e_aq_set_mac_config {
1719        __le16  max_frame_size;
1720        u8      params;
1721#define I40E_AQ_SET_MAC_CONFIG_CRC_EN           0x04
1722#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK      0x78
1723#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT     3
1724#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE      0x0
1725#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX   0xF
1726#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX   0x9
1727#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX   0x8
1728#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX   0x7
1729#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX   0x6
1730#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX   0x5
1731#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX   0x4
1732#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX   0x3
1733#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX   0x2
1734#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX   0x1
1735        u8      tx_timer_priority; /* bitmap */
1736        __le16  tx_timer_value;
1737        __le16  fc_refresh_threshold;
1738        u8      reserved[8];
1739};
1740
1741I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1742
1743/* Restart Auto-Negotiation (direct 0x605) */
1744struct i40e_aqc_set_link_restart_an {
1745        u8      command;
1746#define I40E_AQ_PHY_RESTART_AN  0x02
1747#define I40E_AQ_PHY_LINK_ENABLE 0x04
1748        u8      reserved[15];
1749};
1750
1751I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1752
1753/* Get Link Status cmd & response data structure (direct 0x0607) */
1754struct i40e_aqc_get_link_status {
1755        __le16  command_flags; /* only field set on command */
1756#define I40E_AQ_LSE_MASK                0x3
1757#define I40E_AQ_LSE_NOP                 0x0
1758#define I40E_AQ_LSE_DISABLE             0x2
1759#define I40E_AQ_LSE_ENABLE              0x3
1760/* only response uses this flag */
1761#define I40E_AQ_LSE_IS_ENABLED          0x1
1762        u8      phy_type;    /* i40e_aq_phy_type   */
1763        u8      link_speed;  /* i40e_aq_link_speed */
1764        u8      link_info;
1765#define I40E_AQ_LINK_UP                 0x01    /* obsolete */
1766#define I40E_AQ_LINK_UP_FUNCTION        0x01
1767#define I40E_AQ_LINK_FAULT              0x02
1768#define I40E_AQ_LINK_FAULT_TX           0x04
1769#define I40E_AQ_LINK_FAULT_RX           0x08
1770#define I40E_AQ_LINK_FAULT_REMOTE       0x10
1771#define I40E_AQ_LINK_UP_PORT            0x20
1772#define I40E_AQ_MEDIA_AVAILABLE         0x40
1773#define I40E_AQ_SIGNAL_DETECT           0x80
1774        u8      an_info;
1775#define I40E_AQ_AN_COMPLETED            0x01
1776#define I40E_AQ_LP_AN_ABILITY           0x02
1777#define I40E_AQ_PD_FAULT                0x04
1778#define I40E_AQ_FEC_EN                  0x08
1779#define I40E_AQ_PHY_LOW_POWER           0x10
1780#define I40E_AQ_LINK_PAUSE_TX           0x20
1781#define I40E_AQ_LINK_PAUSE_RX           0x40
1782#define I40E_AQ_QUALIFIED_MODULE        0x80
1783        u8      ext_info;
1784#define I40E_AQ_LINK_PHY_TEMP_ALARM     0x01
1785#define I40E_AQ_LINK_XCESSIVE_ERRORS    0x02
1786#define I40E_AQ_LINK_TX_SHIFT           0x02
1787#define I40E_AQ_LINK_TX_MASK            (0x03 << I40E_AQ_LINK_TX_SHIFT)
1788#define I40E_AQ_LINK_TX_ACTIVE          0x00
1789#define I40E_AQ_LINK_TX_DRAINED         0x01
1790#define I40E_AQ_LINK_TX_FLUSHED         0x03
1791#define I40E_AQ_LINK_FORCED_40G         0x10
1792        u8      loopback; /* use defines from i40e_aqc_set_lb_mode */
1793        __le16  max_frame_size;
1794        u8      config;
1795#define I40E_AQ_CONFIG_CRC_ENA          0x04
1796#define I40E_AQ_CONFIG_PACING_MASK      0x78
1797        u8      external_power_ability;
1798#define I40E_AQ_LINK_POWER_CLASS_1      0x00
1799#define I40E_AQ_LINK_POWER_CLASS_2      0x01
1800#define I40E_AQ_LINK_POWER_CLASS_3      0x02
1801#define I40E_AQ_LINK_POWER_CLASS_4      0x03
1802        u8      reserved[4];
1803};
1804
1805I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1806
1807/* Set event mask command (direct 0x613) */
1808struct i40e_aqc_set_phy_int_mask {
1809        u8      reserved[8];
1810        __le16  event_mask;
1811#define I40E_AQ_EVENT_LINK_UPDOWN       0x0002
1812#define I40E_AQ_EVENT_MEDIA_NA          0x0004
1813#define I40E_AQ_EVENT_LINK_FAULT        0x0008
1814#define I40E_AQ_EVENT_PHY_TEMP_ALARM    0x0010
1815#define I40E_AQ_EVENT_EXCESSIVE_ERRORS  0x0020
1816#define I40E_AQ_EVENT_SIGNAL_DETECT     0x0040
1817#define I40E_AQ_EVENT_AN_COMPLETED      0x0080
1818#define I40E_AQ_EVENT_MODULE_QUAL_FAIL  0x0100
1819#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1820        u8      reserved1[6];
1821};
1822
1823I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1824
1825/* Get Local AN advt register (direct 0x0614)
1826 * Set Local AN advt register (direct 0x0615)
1827 * Get Link Partner AN advt register (direct 0x0616)
1828 */
1829struct i40e_aqc_an_advt_reg {
1830        __le32  local_an_reg0;
1831        __le16  local_an_reg1;
1832        u8      reserved[10];
1833};
1834
1835I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1836
1837/* Set Loopback mode (0x0618) */
1838struct i40e_aqc_set_lb_mode {
1839        __le16  lb_mode;
1840#define I40E_AQ_LB_PHY_LOCAL    0x01
1841#define I40E_AQ_LB_PHY_REMOTE   0x02
1842#define I40E_AQ_LB_MAC_LOCAL    0x04
1843        u8      reserved[14];
1844};
1845
1846I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1847
1848/* Set PHY Debug command (0x0622) */
1849struct i40e_aqc_set_phy_debug {
1850        u8      command_flags;
1851#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL        0x02
1852#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT  2
1853#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK   (0x03 << \
1854                                        I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1855#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE   0x00
1856#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD   0x01
1857#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT   0x02
1858#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW       0x10
1859        u8      reserved[15];
1860};
1861
1862I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1863
1864enum i40e_aq_phy_reg_type {
1865        I40E_AQC_PHY_REG_INTERNAL       = 0x1,
1866        I40E_AQC_PHY_REG_EXERNAL_BASET  = 0x2,
1867        I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1868};
1869
1870/* Run PHY Activity (0x0626) */
1871struct i40e_aqc_run_phy_activity {
1872        __le16  activity_id;
1873        u8      flags;
1874        u8      reserved1;
1875        __le32  control;
1876        __le32  data;
1877        u8      reserved2[4];
1878};
1879
1880I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
1881
1882/* NVM Read command (indirect 0x0701)
1883 * NVM Erase commands (direct 0x0702)
1884 * NVM Update commands (indirect 0x0703)
1885 */
1886struct i40e_aqc_nvm_update {
1887        u8      command_flags;
1888#define I40E_AQ_NVM_LAST_CMD    0x01
1889#define I40E_AQ_NVM_FLASH_ONLY  0x80
1890        u8      module_pointer;
1891        __le16  length;
1892        __le32  offset;
1893        __le32  addr_high;
1894        __le32  addr_low;
1895};
1896
1897I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1898
1899/* NVM Config Read (indirect 0x0704) */
1900struct i40e_aqc_nvm_config_read {
1901        __le16  cmd_flags;
1902#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK   1
1903#define I40E_AQ_ANVM_READ_SINGLE_FEATURE                0
1904#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES             1
1905        __le16  element_count;
1906        __le16  element_id;     /* Feature/field ID */
1907        __le16  element_id_msw; /* MSWord of field ID */
1908        __le32  address_high;
1909        __le32  address_low;
1910};
1911
1912I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1913
1914/* NVM Config Write (indirect 0x0705) */
1915struct i40e_aqc_nvm_config_write {
1916        __le16  cmd_flags;
1917        __le16  element_count;
1918        u8      reserved[4];
1919        __le32  address_high;
1920        __le32  address_low;
1921};
1922
1923I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1924
1925/* Used for 0x0704 as well as for 0x0705 commands */
1926#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT         1
1927#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
1928                                BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
1929#define I40E_AQ_ANVM_FEATURE            0
1930#define I40E_AQ_ANVM_IMMEDIATE_FIELD    BIT(FEATURE_OR_IMMEDIATE_SHIFT)
1931struct i40e_aqc_nvm_config_data_feature {
1932        __le16 feature_id;
1933#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY            0x01
1934#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP           0x08
1935#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR             0x10
1936        __le16 feature_options;
1937        __le16 feature_selection;
1938};
1939
1940I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1941
1942struct i40e_aqc_nvm_config_data_immediate_field {
1943        __le32 field_id;
1944        __le32 field_value;
1945        __le16 field_options;
1946        __le16 reserved;
1947};
1948
1949I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1950
1951/* OEM Post Update (indirect 0x0720)
1952 * no command data struct used
1953 */
1954 struct i40e_aqc_nvm_oem_post_update {
1955#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA       0x01
1956        u8 sel_data;
1957        u8 reserved[7];
1958};
1959
1960I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1961
1962struct i40e_aqc_nvm_oem_post_update_buffer {
1963        u8 str_len;
1964        u8 dev_addr;
1965        __le16 eeprom_addr;
1966        u8 data[36];
1967};
1968
1969I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1970
1971/* Thermal Sensor (indirect 0x0721)
1972 *     read or set thermal sensor configs and values
1973 *     takes a sensor and command specific data buffer, not detailed here
1974 */
1975struct i40e_aqc_thermal_sensor {
1976        u8 sensor_action;
1977#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG      0
1978#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG       1
1979#define I40E_AQ_THERMAL_SENSOR_READ_TEMP        2
1980        u8 reserved[7];
1981        __le32  addr_high;
1982        __le32  addr_low;
1983};
1984
1985I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
1986
1987/* Send to PF command (indirect 0x0801) id is only used by PF
1988 * Send to VF command (indirect 0x0802) id is only used by PF
1989 * Send to Peer PF command (indirect 0x0803)
1990 */
1991struct i40e_aqc_pf_vf_message {
1992        __le32  id;
1993        u8      reserved[4];
1994        __le32  addr_high;
1995        __le32  addr_low;
1996};
1997
1998I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1999
2000/* Alternate structure */

2001
2002/* Direct write (direct 0x0900)
2003 * Direct read (direct 0x0902)
2004 */
2005struct i40e_aqc_alternate_write {
2006        __le32 address0;
2007        __le32 data0;
2008        __le32 address1;
2009        __le32 data1;
2010};
2011
2012I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2013
2014/* Indirect write (indirect 0x0901)
2015 * Indirect read (indirect 0x0903)
2016 */
2017
2018struct i40e_aqc_alternate_ind_write {
2019        __le32 address;
2020        __le32 length;
2021        __le32 addr_high;
2022        __le32 addr_low;
2023};
2024
2025I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2026
2027/* Done alternate write (direct 0x0904)
2028 * uses i40e_aq_desc
2029 */
2030struct i40e_aqc_alternate_write_done {
2031        __le16  cmd_flags;
2032#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK        1
2033#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY      0
2034#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI        1
2035#define I40E_AQ_ALTERNATE_RESET_NEEDED          2
2036        u8      reserved[14];
2037};
2038
2039I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2040
2041/* Set OEM mode (direct 0x0905) */
2042struct i40e_aqc_alternate_set_mode {
2043        __le32  mode;
2044#define I40E_AQ_ALTERNATE_MODE_NONE     0
2045#define I40E_AQ_ALTERNATE_MODE_OEM      1
2046        u8      reserved[12];
2047};
2048
2049I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2050
2051/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2052
2053/* async events 0x10xx */
2054
2055/* Lan Queue Overflow Event (direct, 0x1001) */
2056struct i40e_aqc_lan_overflow {
2057        __le32  prtdcb_rupto;
2058        __le32  otx_ctl;
2059        u8      reserved[8];
2060};
2061
2062I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2063
2064/* Get LLDP MIB (indirect 0x0A00) */
2065struct i40e_aqc_lldp_get_mib {
2066        u8      type;
2067        u8      reserved1;
2068#define I40E_AQ_LLDP_MIB_TYPE_MASK              0x3
2069#define I40E_AQ_LLDP_MIB_LOCAL                  0x0
2070#define I40E_AQ_LLDP_MIB_REMOTE                 0x1
2071#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE       0x2
2072#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK           0xC
2073#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT          0x2
2074#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2075#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR       0x1
2076#define I40E_AQ_LLDP_TX_SHIFT                   0x4
2077#define I40E_AQ_LLDP_TX_MASK                    (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2078/* TX pause flags use I40E_AQ_LINK_TX_* above */
2079        __le16  local_len;
2080        __le16  remote_len;
2081        u8      reserved2[2];
2082        __le32  addr_high;
2083        __le32  addr_low;
2084};
2085
2086I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2087
2088/* Configure LLDP MIB Change Event (direct 0x0A01)
2089 * also used for the event (with type in the command field)
2090 */
2091struct i40e_aqc_lldp_update_mib {
2092        u8      command;
2093#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE  0x0
2094#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2095        u8      reserved[7];
2096        __le32  addr_high;
2097        __le32  addr_low;
2098};
2099
2100I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2101
2102/* Add LLDP TLV (indirect 0x0A02)
2103 * Delete LLDP TLV (indirect 0x0A04)
2104 */
2105struct i40e_aqc_lldp_add_tlv {
2106        u8      type; /* only nearest bridge and non-TPMR from 0x0A00 */
2107        u8      reserved1[1];
2108        __le16  len;
2109        u8      reserved2[4];
2110        __le32  addr_high;
2111        __le32  addr_low;
2112};
2113
2114I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2115
2116/* Update LLDP TLV (indirect 0x0A03) */
2117struct i40e_aqc_lldp_update_tlv {
2118        u8      type; /* only nearest bridge and non-TPMR from 0x0A00 */
2119        u8      reserved;
2120        __le16  old_len;
2121        __le16  new_offset;
2122        __le16  new_len;
2123        __le32  addr_high;
2124        __le32  addr_low;
2125};
2126
2127I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2128
2129/* Stop LLDP (direct 0x0A05) */
2130struct i40e_aqc_lldp_stop {
2131        u8      command;
2132#define I40E_AQ_LLDP_AGENT_STOP         0x0
2133#define I40E_AQ_LLDP_AGENT_SHUTDOWN     0x1
2134        u8      reserved[15];
2135};
2136
2137I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2138
2139/* Start LLDP (direct 0x0A06) */
2140
2141struct i40e_aqc_lldp_start {
2142        u8      command;
2143#define I40E_AQ_LLDP_AGENT_START        0x1
2144        u8      reserved[15];
2145};
2146
2147I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2148
2149/* Apply MIB changes (0x0A07)
2150 * uses the generic struc as it contains no data
2151 */
2152
2153/* Add Udp Tunnel command and completion (direct 0x0B00) */
2154struct i40e_aqc_add_udp_tunnel {
2155        __le16  udp_port;
2156        u8      reserved0[3];
2157        u8      protocol_type;
2158#define I40E_AQC_TUNNEL_TYPE_VXLAN      0x00
2159#define I40E_AQC_TUNNEL_TYPE_NGE        0x01
2160#define I40E_AQC_TUNNEL_TYPE_TEREDO     0x10
2161#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE  0x11
2162        u8      reserved1[10];
2163};
2164
2165I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2166
2167struct i40e_aqc_add_udp_tunnel_completion {
2168        __le16 udp_port;
2169        u8      filter_entry_index;
2170        u8      multiple_pfs;
2171#define I40E_AQC_SINGLE_PF              0x0
2172#define I40E_AQC_MULTIPLE_PFS           0x1
2173        u8      total_filters;
2174        u8      reserved[11];
2175};
2176
2177I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2178
2179/* remove UDP Tunnel command (0x0B01) */
2180struct i40e_aqc_remove_udp_tunnel {
2181        u8      reserved[2];
2182        u8      index; /* 0 to 15 */
2183        u8      reserved2[13];
2184};
2185
2186I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2187
2188struct i40e_aqc_del_udp_tunnel_completion {
2189        __le16  udp_port;
2190        u8      index; /* 0 to 15 */
2191        u8      multiple_pfs;
2192        u8      total_filters_used;
2193        u8      reserved1[11];
2194};
2195
2196I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2197
2198struct i40e_aqc_get_set_rss_key {
2199#define I40E_AQC_SET_RSS_KEY_VSI_VALID          BIT(15)
2200#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT       0
2201#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK        (0x3FF << \
2202                                        I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2203        __le16  vsi_id;
2204        u8      reserved[6];
2205        __le32  addr_high;
2206        __le32  addr_low;
2207};
2208
2209I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2210
2211struct i40e_aqc_get_set_rss_key_data {
2212        u8 standard_rss_key[0x28];
2213        u8 extended_hash_key[0xc];
2214};
2215
2216I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2217
2218struct  i40e_aqc_get_set_rss_lut {
2219#define I40E_AQC_SET_RSS_LUT_VSI_VALID          BIT(15)
2220#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT       0
2221#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK        (0x3FF << \
2222                                        I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2223        __le16  vsi_id;
2224#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT   0
2225#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK \
2226                                BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2227
2228#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI     0
2229#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF      1
2230        __le16  flags;
2231        u8      reserved[4];
2232        __le32  addr_high;
2233        __le32  addr_low;
2234};
2235
2236I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2237
2238/* tunnel key structure 0x0B10 */
2239
2240struct i40e_aqc_tunnel_key_structure_A0 {
2241        __le16     key1_off;
2242        __le16     key1_len;
2243        __le16     key2_off;
2244        __le16     key2_len;
2245        __le16     flags;
2246#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2247/* response flags */
2248#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS    0x01
2249#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED   0x02
2250#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2251        u8         resreved[6];
2252};
2253
2254I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0);
2255
2256struct i40e_aqc_tunnel_key_structure {
2257        u8      key1_off;
2258        u8      key2_off;
2259        u8      key1_len;  /* 0 to 15 */
2260        u8      key2_len;  /* 0 to 15 */
2261        u8      flags;
2262#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE     0x01
2263/* response flags */
2264#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS      0x01
2265#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED     0x02
2266#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN   0x03
2267        u8      network_key_index;
2268#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN                0x0
2269#define I40E_AQC_NETWORK_KEY_INDEX_NGE                  0x1
2270#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP      0x2
2271#define I40E_AQC_NETWORK_KEY_INDEX_GRE                  0x3
2272        u8      reserved[10];
2273};
2274
2275I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2276
2277/* OEM mode commands (direct 0xFE0x) */
2278struct i40e_aqc_oem_param_change {
2279        __le32  param_type;
2280#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL   0
2281#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL   1
2282#define I40E_AQ_OEM_PARAM_MAC           2
2283        __le32  param_value1;
2284        __le16  param_value2;
2285        u8      reserved[6];
2286};
2287
2288I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2289
2290struct i40e_aqc_oem_state_change {
2291        __le32  state;
2292#define I40E_AQ_OEM_STATE_LINK_DOWN     0x0
2293#define I40E_AQ_OEM_STATE_LINK_UP       0x1
2294        u8      reserved[12];
2295};
2296
2297I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2298
2299/* Initialize OCSD (0xFE02, direct) */
2300struct i40e_aqc_opc_oem_ocsd_initialize {
2301        u8 type_status;
2302        u8 reserved1[3];
2303        __le32 ocsd_memory_block_addr_high;
2304        __le32 ocsd_memory_block_addr_low;
2305        __le32 requested_update_interval;
2306};
2307
2308I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2309
2310/* Initialize OCBB  (0xFE03, direct) */
2311struct i40e_aqc_opc_oem_ocbb_initialize {
2312        u8 type_status;
2313        u8 reserved1[3];
2314        __le32 ocbb_memory_block_addr_high;
2315        __le32 ocbb_memory_block_addr_low;
2316        u8 reserved2[4];
2317};
2318
2319I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2320
2321/* debug commands */
2322
2323/* get device id (0xFF00) uses the generic structure */
2324
2325/* set test more (0xFF01, internal) */
2326
2327struct i40e_acq_set_test_mode {
2328        u8      mode;
2329#define I40E_AQ_TEST_PARTIAL    0
2330#define I40E_AQ_TEST_FULL       1
2331#define I40E_AQ_TEST_NVM        2
2332        u8      reserved[3];
2333        u8      command;
2334#define I40E_AQ_TEST_OPEN       0
2335#define I40E_AQ_TEST_CLOSE      1
2336#define I40E_AQ_TEST_INC        2
2337        u8      reserved2[3];
2338        __le32  address_high;
2339        __le32  address_low;
2340};
2341
2342I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2343
2344/* Debug Read Register command (0xFF03)
2345 * Debug Write Register command (0xFF04)
2346 */
2347struct i40e_aqc_debug_reg_read_write {
2348        __le32 reserved;
2349        __le32 address;
2350        __le32 value_high;
2351        __le32 value_low;
2352};
2353
2354I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2355
2356/* Scatter/gather Reg Read  (indirect 0xFF05)
2357 * Scatter/gather Reg Write (indirect 0xFF06)
2358 */
2359
2360/* i40e_aq_desc is used for the command */
2361struct i40e_aqc_debug_reg_sg_element_data {
2362        __le32 address;
2363        __le32 value;
2364};
2365
2366/* Debug Modify register (direct 0xFF07) */
2367struct i40e_aqc_debug_modify_reg {
2368        __le32 address;
2369        __le32 value;
2370        __le32 clear_mask;
2371        __le32 set_mask;
2372};
2373
2374I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2375
2376/* dump internal data (0xFF08, indirect) */
2377
2378#define I40E_AQ_CLUSTER_ID_AUX          0
2379#define I40E_AQ_CLUSTER_ID_SWITCH_FLU   1
2380#define I40E_AQ_CLUSTER_ID_TXSCHED      2
2381#define I40E_AQ_CLUSTER_ID_HMC          3
2382#define I40E_AQ_CLUSTER_ID_MAC0         4
2383#define I40E_AQ_CLUSTER_ID_MAC1         5
2384#define I40E_AQ_CLUSTER_ID_MAC2         6
2385#define I40E_AQ_CLUSTER_ID_MAC3         7
2386#define I40E_AQ_CLUSTER_ID_DCB          8
2387#define I40E_AQ_CLUSTER_ID_EMP_MEM      9
2388#define I40E_AQ_CLUSTER_ID_PKT_BUF      10
2389#define I40E_AQ_CLUSTER_ID_ALTRAM       11
2390
2391struct i40e_aqc_debug_dump_internals {
2392        u8      cluster_id;
2393        u8      table_id;
2394        __le16  data_size;
2395        __le32  idx;
2396        __le32  address_high;
2397        __le32  address_low;
2398};
2399
2400I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2401
2402struct i40e_aqc_debug_modify_internals {
2403        u8      cluster_id;
2404        u8      cluster_specific_params[7];
2405        __le32  address_high;
2406        __le32  address_low;
2407};
2408
2409I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2410
2411#endif /* _I40E_ADMINQ_CMD_H_ */
2412
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.