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26#ifndef __RTL92C_PHY_H__
27#define __RTL92C_PHY_H__
28
29
30
31
32#define MAX_TX_COUNT 4
33
34#define MAX_PRECMD_CNT 16
35#define MAX_RFDEPENDCMD_CNT 16
36#define MAX_POSTCMD_CNT 16
37
38#define MAX_DOZE_WAITING_TIMES_9x 64
39
40#define RT_CANNOT_IO(hw) false
41#define HIGHPOWER_RADIOA_ARRAYLEN 22
42
43#define IQK_ADDA_REG_NUM 16
44#define IQK_BB_REG_NUM 9
45#define MAX_TOLERANCE 5
46#define IQK_DELAY_TIME 10
47#define INDEX_MAPPING_NUM 15
48
49#define APK_BB_REG_NUM 5
50#define APK_AFE_REG_NUM 16
51#define APK_CURVE_REG_NUM 4
52#define PATH_NUM 2
53
54#define LOOP_LIMIT 5
55#define MAX_STALL_TIME 50
56#define ANTENNADIVERSITYVALUE 0x80
57#define MAX_TXPWR_IDX_NMODE_92S 63
58#define RESET_CNT_LIMIT 3
59
60#define IQK_ADDA_REG_NUM 16
61#define IQK_MAC_REG_NUM 4
62
63#define RF6052_MAX_PATH 2
64
65#define CT_OFFSET_MAC_ADDR 0X16
66
67#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
68#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
69#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
70#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
71#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
72
73#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
74#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
75
76#define CT_OFFSET_CHANNEL_PLAH 0x75
77#define CT_OFFSET_THERMAL_METER 0x78
78#define CT_OFFSET_RF_OPTION 0x79
79#define CT_OFFSET_VERSION 0x7E
80#define CT_OFFSET_CUSTOMER_ID 0x7F
81
82#define RTL92C_MAX_PATH_NUM 2
83
84enum swchnlcmd_id {
85 CMDID_END,
86 CMDID_SET_TXPOWEROWER_LEVEL,
87 CMDID_BBREGWRITE10,
88 CMDID_WRITEPORT_ULONG,
89 CMDID_WRITEPORT_USHORT,
90 CMDID_WRITEPORT_UCHAR,
91 CMDID_RF_WRITEREG,
92};
93
94struct swchnlcmd {
95 enum swchnlcmd_id cmdid;
96 u32 para1;
97 u32 para2;
98 u32 msdelay;
99};
100
101enum hw90_block_e {
102 HW90_BLOCK_MAC = 0,
103 HW90_BLOCK_PHY0 = 1,
104 HW90_BLOCK_PHY1 = 2,
105 HW90_BLOCK_RF = 3,
106 HW90_BLOCK_MAXIMUM = 4,
107};
108
109enum baseband_config_type {
110 BASEBAND_CONFIG_PHY_REG = 0,
111 BASEBAND_CONFIG_AGC_TAB = 1,
112};
113
114enum ra_offset_area {
115 RA_OFFSET_LEGACY_OFDM1,
116 RA_OFFSET_LEGACY_OFDM2,
117 RA_OFFSET_HT_OFDM1,
118 RA_OFFSET_HT_OFDM2,
119 RA_OFFSET_HT_OFDM3,
120 RA_OFFSET_HT_OFDM4,
121 RA_OFFSET_HT_CCK,
122};
123
124enum antenna_path {
125 ANTENNA_NONE,
126 ANTENNA_D,
127 ANTENNA_C,
128 ANTENNA_CD,
129 ANTENNA_B,
130 ANTENNA_BD,
131 ANTENNA_BC,
132 ANTENNA_BCD,
133 ANTENNA_A,
134 ANTENNA_AD,
135 ANTENNA_AC,
136 ANTENNA_ACD,
137 ANTENNA_AB,
138 ANTENNA_ABD,
139 ANTENNA_ABC,
140 ANTENNA_ABCD
141};
142
143struct r_antenna_select_ofdm {
144 u32 r_tx_antenna:4;
145 u32 r_ant_l:4;
146 u32 r_ant_non_ht:4;
147 u32 r_ant_ht1:4;
148 u32 r_ant_ht2:4;
149 u32 r_ant_ht_s1:4;
150 u32 r_ant_non_ht_s1:4;
151 u32 ofdm_txsc:2;
152 u32 reserved:2;
153};
154
155struct r_antenna_select_cck {
156 u8 r_cckrx_enable_2:2;
157 u8 r_cckrx_enable:2;
158 u8 r_ccktx_enable:4;
159};
160
161struct efuse_contents {
162 u8 mac_addr[ETH_ALEN];
163 u8 cck_tx_power_idx[6];
164 u8 ht40_1s_tx_power_idx[6];
165 u8 ht40_2s_tx_power_idx_diff[3];
166 u8 ht20_tx_power_idx_diff[3];
167 u8 ofdm_tx_power_idx_diff[3];
168 u8 ht40_max_power_offset[3];
169 u8 ht20_max_power_offset[3];
170 u8 channel_plan;
171 u8 thermal_meter;
172 u8 rf_option[5];
173 u8 version;
174 u8 oem_id;
175 u8 regulatory;
176};
177
178struct tx_power_struct {
179 u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
180 u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
181 u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
182 u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
183 u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
184 u8 legacy_ht_txpowerdiff;
185 u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
186 u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
187 u8 pwrgroup_cnt;
188 u32 mcs_original_offset[4][16];
189};
190
191enum _ANT_DIV_TYPE {
192 NO_ANTDIV = 0xFF,
193 CG_TRX_HW_ANTDIV = 0x01,
194 CGCS_RX_HW_ANTDIV = 0x02,
195 FIXED_HW_ANTDIV = 0x03,
196 CG_TRX_SMART_ANTDIV = 0x04,
197 CGCS_RX_SW_ANTDIV = 0x05,
198};
199
200u32 rtl88e_phy_query_bb_reg(struct ieee80211_hw *hw,
201 u32 regaddr, u32 bitmask);
202void rtl88e_phy_set_bb_reg(struct ieee80211_hw *hw,
203 u32 regaddr, u32 bitmask, u32 data);
204u32 rtl88e_phy_query_rf_reg(struct ieee80211_hw *hw,
205 enum radio_path rfpath, u32 regaddr,
206 u32 bitmask);
207void rtl88e_phy_set_rf_reg(struct ieee80211_hw *hw,
208 enum radio_path rfpath, u32 regaddr,
209 u32 bitmask, u32 data);
210bool rtl88e_phy_mac_config(struct ieee80211_hw *hw);
211bool rtl88e_phy_bb_config(struct ieee80211_hw *hw);
212bool rtl88e_phy_rf_config(struct ieee80211_hw *hw);
213void rtl88e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
214void rtl88e_phy_get_txpower_level(struct ieee80211_hw *hw,
215 long *powerlevel);
216void rtl88e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
217void rtl88e_phy_scan_operation_backup(struct ieee80211_hw *hw,
218 u8 operation);
219void rtl88e_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
220void rtl88e_phy_set_bw_mode(struct ieee80211_hw *hw,
221 enum nl80211_channel_type ch_type);
222void rtl88e_phy_sw_chnl_callback(struct ieee80211_hw *hw);
223u8 rtl88e_phy_sw_chnl(struct ieee80211_hw *hw);
224void rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
225void rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw);
226void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
227bool rtl88e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
228 enum radio_path rfpath);
229bool rtl88e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
230bool rtl88e_phy_set_rf_power_state(struct ieee80211_hw *hw,
231 enum rf_pwrstate rfpwr_state);
232
233#endif
234
