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34#ifndef _MEGARAID_SAS_FUSION_H_
35#define _MEGARAID_SAS_FUSION_H_
36
37
38#define MEGASAS_CHAIN_FRAME_SZ_MIN 1024
39#define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
40#define MEGASAS_MAX_CHAIN_SHIFT 5
41#define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK 0x400000
42#define MEGASAS_MAX_CHAIN_SIZE_MASK 0x3E0
43#define MEGASAS_256K_IO 128
44#define MEGASAS_1MB_IO (MEGASAS_256K_IO * 4)
45#define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
46#define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
47#define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1
48#define MEGASAS_LOAD_BALANCE_FLAG 0x1
49#define MEGASAS_DCMD_MBOX_PEND_FLAG 0x1
50#define HOST_DIAG_WRITE_ENABLE 0x80
51#define HOST_DIAG_RESET_ADAPTER 0x4
52#define MEGASAS_FUSION_MAX_RESET_TRIES 3
53#define MAX_MSIX_QUEUES_FUSION 128
54
55
56#define MPI2_TYPE_CUDA 0x2
57#define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000
58#define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00
59#define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10
60#define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80
61#define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8
62
63
64#define MR_PROT_INFO_TYPE_CONTROLLER 0x8
65#define MEGASAS_SCSI_VARIABLE_LENGTH_CMD 0x7f
66#define MEGASAS_SCSI_SERVICE_ACTION_READ32 0x9
67#define MEGASAS_SCSI_SERVICE_ACTION_WRITE32 0xB
68#define MEGASAS_SCSI_ADDL_CDB_LEN 0x18
69#define MEGASAS_RD_WR_PROTECT_CHECK_ALL 0x20
70#define MEGASAS_RD_WR_PROTECT_CHECK_NONE 0x60
71
72#define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C)
73#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
74
75
76
77
78
79#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
80#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
81enum MR_RAID_FLAGS_IO_SUB_TYPE {
82 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
83 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
84};
85
86
87
88
89#define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7
90#define MEGASAS_REQ_DESCRIPT_FLAGS_MFA 0x1
91#define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2
92#define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1
93
94#define MEGASAS_FP_CMD_LEN 16
95#define MEGASAS_FUSION_IN_RESET 0
96#define THRESHOLD_REPLY_COUNT 50
97#define JBOD_MAPS_COUNT 2
98
99enum MR_FUSION_ADAPTER_TYPE {
100 THUNDERBOLT_SERIES = 0,
101 INVADER_SERIES = 1,
102};
103
104
105
106
107
108
109struct RAID_CONTEXT {
110#if defined(__BIG_ENDIAN_BITFIELD)
111 u8 nseg:4;
112 u8 Type:4;
113#else
114 u8 Type:4;
115 u8 nseg:4;
116#endif
117 u8 resvd0;
118 __le16 timeoutValue;
119 u8 regLockFlags;
120 u8 resvd1;
121 __le16 VirtualDiskTgtId;
122 __le64 regLockRowLBA;
123 __le32 regLockLength;
124 __le16 nextLMId;
125 u8 exStatus;
126 u8 status;
127 u8 RAIDFlags;
128 u8 numSGE;
129 __le16 configSeqNum;
130 u8 spanArm;
131 u8 priority;
132 u8 numSGEExt;
133 u8 resvd2;
134};
135
136#define RAID_CTX_SPANARM_ARM_SHIFT (0)
137#define RAID_CTX_SPANARM_ARM_MASK (0x1f)
138
139#define RAID_CTX_SPANARM_SPAN_SHIFT (5)
140#define RAID_CTX_SPANARM_SPAN_MASK (0xE0)
141
142
143
144
145enum REGION_TYPE {
146 REGION_TYPE_UNUSED = 0,
147 REGION_TYPE_SHARED_READ = 1,
148 REGION_TYPE_SHARED_WRITE = 2,
149 REGION_TYPE_EXCLUSIVE = 3,
150};
151
152
153#define MPI2_FUNCTION_IOC_INIT (0x02)
154#define MPI2_WHOINIT_HOST_DRIVER (0x04)
155#define MPI2_VERSION_MAJOR (0x02)
156#define MPI2_VERSION_MINOR (0x00)
157#define MPI2_VERSION_MAJOR_MASK (0xFF00)
158#define MPI2_VERSION_MAJOR_SHIFT (8)
159#define MPI2_VERSION_MINOR_MASK (0x00FF)
160#define MPI2_VERSION_MINOR_SHIFT (0)
161#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
162 MPI2_VERSION_MINOR)
163#define MPI2_HEADER_VERSION_UNIT (0x10)
164#define MPI2_HEADER_VERSION_DEV (0x00)
165#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
166#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
167#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
168#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
169#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
170 MPI2_HEADER_VERSION_DEV)
171#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
172#define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
173#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
174#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
175#define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
176#define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
177#define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
178#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00)
179#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
180#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x03)
181#define MPI2_REQ_DESCRIPT_FLAGS_FP_IO (0x06)
182#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
183#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
184#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
185#define MPI2_SCSIIO_CONTROL_READ (0x02000000)
186#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
187#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
188#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
189#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
190#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
191#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
192#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
193#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
194#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
195#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
196#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
197#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
198
199struct MPI25_IEEE_SGE_CHAIN64 {
200 __le64 Address;
201 __le32 Length;
202 __le16 Reserved1;
203 u8 NextChainOffset;
204 u8 Flags;
205};
206
207struct MPI2_SGE_SIMPLE_UNION {
208 __le32 FlagsLength;
209 union {
210 __le32 Address32;
211 __le64 Address64;
212 } u;
213};
214
215struct MPI2_SCSI_IO_CDB_EEDP32 {
216 u8 CDB[20];
217 __be32 PrimaryReferenceTag;
218 __be16 PrimaryApplicationTag;
219 __be16 PrimaryApplicationTagMask;
220 __le32 TransferLength;
221};
222
223struct MPI2_SGE_CHAIN_UNION {
224 __le16 Length;
225 u8 NextChainOffset;
226 u8 Flags;
227 union {
228 __le32 Address32;
229 __le64 Address64;
230 } u;
231};
232
233struct MPI2_IEEE_SGE_SIMPLE32 {
234 __le32 Address;
235 __le32 FlagsLength;
236};
237
238struct MPI2_IEEE_SGE_CHAIN32 {
239 __le32 Address;
240 __le32 FlagsLength;
241};
242
243struct MPI2_IEEE_SGE_SIMPLE64 {
244 __le64 Address;
245 __le32 Length;
246 __le16 Reserved1;
247 u8 Reserved2;
248 u8 Flags;
249};
250
251struct MPI2_IEEE_SGE_CHAIN64 {
252 __le64 Address;
253 __le32 Length;
254 __le16 Reserved1;
255 u8 Reserved2;
256 u8 Flags;
257};
258
259union MPI2_IEEE_SGE_SIMPLE_UNION {
260 struct MPI2_IEEE_SGE_SIMPLE32 Simple32;
261 struct MPI2_IEEE_SGE_SIMPLE64 Simple64;
262};
263
264union MPI2_IEEE_SGE_CHAIN_UNION {
265 struct MPI2_IEEE_SGE_CHAIN32 Chain32;
266 struct MPI2_IEEE_SGE_CHAIN64 Chain64;
267};
268
269union MPI2_SGE_IO_UNION {
270 struct MPI2_SGE_SIMPLE_UNION MpiSimple;
271 struct MPI2_SGE_CHAIN_UNION MpiChain;
272 union MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
273 union MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
274};
275
276union MPI2_SCSI_IO_CDB_UNION {
277 u8 CDB32[32];
278 struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
279 struct MPI2_SGE_SIMPLE_UNION SGE;
280};
281
282
283
284
285
286
287struct MPI2_SCSI_TASK_MANAGE_REQUEST {
288 u16 DevHandle;
289 u8 ChainOffset;
290 u8 Function;
291 u8 Reserved1;
292 u8 TaskType;
293 u8 Reserved2;
294 u8 MsgFlags;
295 u8 VP_ID;
296 u8 VF_ID;
297 u16 Reserved3;
298 u8 LUN[8];
299 u32 Reserved4[7];
300 u16 TaskMID;
301 u16 Reserved5;
302};
303
304
305
306struct MPI2_SCSI_TASK_MANAGE_REPLY {
307 u16 DevHandle;
308 u8 MsgLength;
309 u8 Function;
310 u8 ResponseCode;
311 u8 TaskType;
312 u8 Reserved1;
313 u8 MsgFlags;
314 u8 VP_ID;
315 u8 VF_ID;
316 u16 Reserved2;
317 u16 Reserved3;
318 u16 IOCStatus;
319 u32 IOCLogInfo;
320 u32 TerminationCount;
321 u32 ResponseInfo;
322};
323
324struct MR_TM_REQUEST {
325 char request[128];
326};
327
328struct MR_TM_REPLY {
329 char reply[128];
330};
331
332
333struct MR_TASK_MANAGE_REQUEST {
334
335 struct MR_TM_REQUEST TmRequest;
336 union {
337 struct {
338#if defined(__BIG_ENDIAN_BITFIELD)
339 u32 reserved1:30;
340 u32 isTMForPD:1;
341 u32 isTMForLD:1;
342#else
343 u32 isTMForLD:1;
344 u32 isTMForPD:1;
345 u32 reserved1:30;
346#endif
347 u32 reserved2;
348 } tmReqFlags;
349 struct MR_TM_REPLY TMReply;
350 };
351};
352
353
354
355#define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
356#define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02)
357#define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
358#define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
359#define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
360#define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
361#define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08)
362#define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09)
363#define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT (0x0A)
364
365
366
367#define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00)
368#define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02)
369#define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04)
370#define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05)
371#define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08)
372#define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09)
373#define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG (0x0A)
374#define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80)
375
376
377
378
379
380struct MPI2_RAID_SCSI_IO_REQUEST {
381 __le16 DevHandle;
382 u8 ChainOffset;
383 u8 Function;
384 __le16 Reserved1;
385 u8 Reserved2;
386 u8 MsgFlags;
387 u8 VP_ID;
388 u8 VF_ID;
389 __le16 Reserved3;
390 __le32 SenseBufferLowAddress;
391 __le16 SGLFlags;
392 u8 SenseBufferLength;
393 u8 Reserved4;
394 u8 SGLOffset0;
395 u8 SGLOffset1;
396 u8 SGLOffset2;
397 u8 SGLOffset3;
398 __le32 SkipCount;
399 __le32 DataLength;
400 __le32 BidirectionalDataLength;
401 __le16 IoFlags;
402 __le16 EEDPFlags;
403 __le32 EEDPBlockSize;
404 __le32 SecondaryReferenceTag;
405 __le16 SecondaryApplicationTag;
406 __le16 ApplicationTagTranslationMask;
407 u8 LUN[8];
408 __le32 Control;
409 union MPI2_SCSI_IO_CDB_UNION CDB;
410 struct RAID_CONTEXT RaidContext;
411 union MPI2_SGE_IO_UNION SGL;
412};
413
414
415
416
417struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR {
418 u32 RequestFlags:8;
419 u32 MessageAddress1:24;
420 u32 MessageAddress2;
421};
422
423
424struct MPI2_DEFAULT_REQUEST_DESCRIPTOR {
425 u8 RequestFlags;
426 u8 MSIxIndex;
427 __le16 SMID;
428 __le16 LMID;
429 __le16 DescriptorTypeDependent;
430};
431
432
433struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
434 u8 RequestFlags;
435 u8 MSIxIndex;
436 __le16 SMID;
437 __le16 LMID;
438 __le16 Reserved1;
439};
440
441
442struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
443 u8 RequestFlags;
444 u8 MSIxIndex;
445 __le16 SMID;
446 __le16 LMID;
447 __le16 DevHandle;
448};
449
450
451struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
452 u8 RequestFlags;
453 u8 MSIxIndex;
454 __le16 SMID;
455 __le16 LMID;
456 __le16 IoIndex;
457};
458
459
460struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
461 u8 RequestFlags;
462 u8 MSIxIndex;
463 __le16 SMID;
464 __le16 LMID;
465 __le16 Reserved;
466};
467
468
469union MEGASAS_REQUEST_DESCRIPTOR_UNION {
470 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
471 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
472 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
473 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
474 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
475 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;
476 union {
477 struct {
478 __le32 low;
479 __le32 high;
480 } u;
481 __le64 Words;
482 };
483};
484
485
486struct MPI2_DEFAULT_REPLY_DESCRIPTOR {
487 u8 ReplyFlags;
488 u8 MSIxIndex;
489 __le16 DescriptorTypeDependent1;
490 __le32 DescriptorTypeDependent2;
491};
492
493
494struct MPI2_ADDRESS_REPLY_DESCRIPTOR {
495 u8 ReplyFlags;
496 u8 MSIxIndex;
497 __le16 SMID;
498 __le32 ReplyFrameAddress;
499};
500
501
502struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
503 u8 ReplyFlags;
504 u8 MSIxIndex;
505 __le16 SMID;
506 __le16 TaskTag;
507 __le16 Reserved1;
508};
509
510
511struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
512 u8 ReplyFlags;
513 u8 MSIxIndex;
514 __le16 SMID;
515 u8 SequenceNumber;
516 u8 Reserved1;
517 __le16 IoIndex;
518};
519
520
521struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
522 u8 ReplyFlags;
523 u8 MSIxIndex;
524 u8 VP_ID;
525 u8 Flags;
526 __le16 InitiatorDevHandle;
527 __le16 IoIndex;
528};
529
530
531struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
532 u8 ReplyFlags;
533 u8 MSIxIndex;
534 __le16 SMID;
535 __le32 Reserved;
536};
537
538
539union MPI2_REPLY_DESCRIPTORS_UNION {
540 struct MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
541 struct MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
542 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
543 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
544 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
545 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
546 RAIDAcceleratorSuccess;
547 __le64 Words;
548};
549
550
551struct MPI2_IOC_INIT_REQUEST {
552 u8 WhoInit;
553 u8 Reserved1;
554 u8 ChainOffset;
555 u8 Function;
556 __le16 Reserved2;
557 u8 Reserved3;
558 u8 MsgFlags;
559 u8 VP_ID;
560 u8 VF_ID;
561 __le16 Reserved4;
562 __le16 MsgVersion;
563 __le16 HeaderVersion;
564 u32 Reserved5;
565 __le16 Reserved6;
566 u8 Reserved7;
567 u8 HostMSIxVectors;
568 __le16 Reserved8;
569 __le16 SystemRequestFrameSize;
570 __le16 ReplyDescriptorPostQueueDepth;
571 __le16 ReplyFreeQueueDepth;
572 __le32 SenseBufferAddressHigh;
573 __le32 SystemReplyAddressHigh;
574 __le64 SystemRequestFrameBaseAddress;
575 __le64 ReplyDescriptorPostQueueAddress;
576 __le64 ReplyFreeQueueAddress;
577 __le64 TimeStamp;
578};
579
580
581#define MR_PD_INVALID 0xFFFF
582#define MAX_SPAN_DEPTH 8
583#define MAX_QUAD_DEPTH MAX_SPAN_DEPTH
584#define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
585#define MAX_ROW_SIZE 32
586#define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
587#define MAX_LOGICAL_DRIVES 64
588#define MAX_LOGICAL_DRIVES_EXT 256
589#define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
590#define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
591#define MAX_ARRAYS 128
592#define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
593#define MAX_ARRAYS_EXT 256
594#define MAX_API_ARRAYS_EXT (MAX_ARRAYS_EXT)
595#define MAX_PHYSICAL_DEVICES 256
596#define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
597#define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
598#define MR_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102
599#define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC 0x010e8485
600#define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111 0x03200200
601#define MR_DCMD_LD_VF_MAP_GET_ALL_LDS 0x03150200
602
603struct MR_DEV_HANDLE_INFO {
604 __le16 curDevHdl;
605 u8 validHandles;
606 u8 reserved;
607 __le16 devHandle[2];
608};
609
610struct MR_ARRAY_INFO {
611 __le16 pd[MAX_RAIDMAP_ROW_SIZE];
612};
613
614struct MR_QUAD_ELEMENT {
615 __le64 logStart;
616 __le64 logEnd;
617 __le64 offsetInSpan;
618 __le32 diff;
619 __le32 reserved1;
620};
621
622struct MR_SPAN_INFO {
623 __le32 noElements;
624 __le32 reserved1;
625 struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
626};
627
628struct MR_LD_SPAN {
629 __le64 startBlk;
630 __le64 numBlks;
631 __le16 arrayRef;
632 u8 spanRowSize;
633 u8 spanRowDataSize;
634 u8 reserved[4];
635};
636
637struct MR_SPAN_BLOCK_INFO {
638 __le64 num_rows;
639 struct MR_LD_SPAN span;
640 struct MR_SPAN_INFO block_span_info;
641};
642
643struct MR_LD_RAID {
644 struct {
645#if defined(__BIG_ENDIAN_BITFIELD)
646 u32 reserved4:5;
647 u32 fpBypassRegionLock:1;
648 u32 tmCapable:1;
649 u32 fpNonRWCapable:1;
650 u32 fpReadAcrossStripe:1;
651 u32 fpWriteAcrossStripe:1;
652 u32 fpReadCapable:1;
653 u32 fpWriteCapable:1;
654 u32 encryptionType:8;
655 u32 pdPiMode:4;
656 u32 ldPiMode:4;
657 u32 reserved5:3;
658 u32 fpCapable:1;
659#else
660 u32 fpCapable:1;
661 u32 reserved5:3;
662 u32 ldPiMode:4;
663 u32 pdPiMode:4;
664 u32 encryptionType:8;
665 u32 fpWriteCapable:1;
666 u32 fpReadCapable:1;
667 u32 fpWriteAcrossStripe:1;
668 u32 fpReadAcrossStripe:1;
669 u32 fpNonRWCapable:1;
670 u32 tmCapable:1;
671 u32 fpBypassRegionLock:1;
672 u32 reserved4:5;
673#endif
674 } capability;
675 __le32 reserved6;
676 __le64 size;
677 u8 spanDepth;
678 u8 level;
679 u8 stripeShift;
680 u8 rowSize;
681 u8 rowDataSize;
682 u8 writeMode;
683 u8 PRL;
684 u8 SRL;
685 __le16 targetId;
686 u8 ldState;
687 u8 regTypeReqOnWrite;
688 u8 modFactor;
689 u8 regTypeReqOnRead;
690 __le16 seqNum;
691
692 struct {
693 u32 ldSyncRequired:1;
694 u32 reserved:31;
695 } flags;
696
697 u8 LUN[8];
698 u8 fpIoTimeoutForLd;
699 u8 reserved3[0x80-0x2D];
700};
701
702struct MR_LD_SPAN_MAP {
703 struct MR_LD_RAID ldRaid;
704 u8 dataArmMap[MAX_RAIDMAP_ROW_SIZE];
705 struct MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
706};
707
708struct MR_FW_RAID_MAP {
709 __le32 totalSize;
710 union {
711 struct {
712 __le32 maxLd;
713 __le32 maxSpanDepth;
714 __le32 maxRowSize;
715 __le32 maxPdCount;
716 __le32 maxArrays;
717 } validationInfo;
718 __le32 version[5];
719 };
720
721 __le32 ldCount;
722 __le32 Reserved1;
723 u8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+
724 MAX_RAIDMAP_VIEWS];
725 u8 fpPdIoTimeoutSec;
726 u8 reserved2[7];
727 struct MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS];
728 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
729 struct MR_LD_SPAN_MAP ldSpanMap[1];
730};
731
732struct IO_REQUEST_INFO {
733 u64 ldStartBlock;
734 u32 numBlocks;
735 u16 ldTgtId;
736 u8 isRead;
737 __le16 devHandle;
738 u64 pdBlock;
739 u8 fpOkForIo;
740 u8 IoforUnevenSpan;
741 u8 start_span;
742 u8 do_fp_rlbypass;
743 u64 start_row;
744 u8 span_arm;
745 u8 pd_after_lb;
746};
747
748struct MR_LD_TARGET_SYNC {
749 u8 targetId;
750 u8 reserved;
751 __le16 seqNum;
752};
753
754#define IEEE_SGE_FLAGS_ADDR_MASK (0x03)
755#define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
756#define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
757#define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
758#define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
759#define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
760#define IEEE_SGE_FLAGS_END_OF_LIST (0x40)
761
762struct megasas_register_set;
763struct megasas_instance;
764
765union desc_word {
766 u64 word;
767 struct {
768 u32 low;
769 u32 high;
770 } u;
771};
772
773struct megasas_cmd_fusion {
774 struct MPI2_RAID_SCSI_IO_REQUEST *io_request;
775 dma_addr_t io_request_phys_addr;
776
777 union MPI2_SGE_IO_UNION *sg_frame;
778 dma_addr_t sg_frame_phys_addr;
779
780 u8 *sense;
781 dma_addr_t sense_phys_addr;
782
783 struct list_head list;
784 struct scsi_cmnd *scmd;
785 struct megasas_instance *instance;
786
787 u8 retry_for_fw_reset;
788 union MEGASAS_REQUEST_DESCRIPTOR_UNION *request_desc;
789
790
791
792
793
794 u32 sync_cmd_idx;
795 u32 index;
796 u8 pd_r1_lb;
797 struct completion done;
798};
799
800struct LD_LOAD_BALANCE_INFO {
801 u8 loadBalanceFlag;
802 u8 reserved1;
803 atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES];
804 u64 last_accessed_block[MAX_PHYSICAL_DEVICES];
805};
806
807
808typedef struct _LD_SPAN_SET {
809 u64 log_start_lba;
810 u64 log_end_lba;
811 u64 span_row_start;
812 u64 span_row_end;
813 u64 data_strip_start;
814 u64 data_strip_end;
815 u64 data_row_start;
816 u64 data_row_end;
817 u8 strip_offset[MAX_SPAN_DEPTH];
818 u32 span_row_data_width;
819 u32 diff;
820 u32 reserved[2];
821} LD_SPAN_SET, *PLD_SPAN_SET;
822
823typedef struct LOG_BLOCK_SPAN_INFO {
824 LD_SPAN_SET span_set[MAX_SPAN_DEPTH];
825} LD_SPAN_INFO, *PLD_SPAN_INFO;
826
827struct MR_FW_RAID_MAP_ALL {
828 struct MR_FW_RAID_MAP raidMap;
829 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
830} __attribute__ ((packed));
831
832struct MR_DRV_RAID_MAP {
833
834
835
836
837 __le32 totalSize;
838
839 union {
840 struct {
841 __le32 maxLd;
842 __le32 maxSpanDepth;
843 __le32 maxRowSize;
844 __le32 maxPdCount;
845 __le32 maxArrays;
846 } validationInfo;
847 __le32 version[5];
848 };
849
850
851 u8 fpPdIoTimeoutSec;
852 u8 reserved2[7];
853
854 __le16 ldCount;
855 __le16 arCount;
856 __le16 spanCount;
857 __le16 reserve3;
858
859 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
860 u8 ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
861 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT];
862 struct MR_LD_SPAN_MAP ldSpanMap[1];
863
864};
865
866
867
868
869
870struct MR_DRV_RAID_MAP_ALL {
871
872 struct MR_DRV_RAID_MAP raidMap;
873 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT - 1];
874} __packed;
875
876
877
878struct MR_FW_RAID_MAP_EXT {
879
880 u32 reserved;
881
882 union {
883 struct {
884 u32 maxLd;
885 u32 maxSpanDepth;
886 u32 maxRowSize;
887 u32 maxPdCount;
888 u32 maxArrays;
889 } validationInfo;
890 u32 version[5];
891 };
892
893 u8 fpPdIoTimeoutSec;
894 u8 reserved2[7];
895
896 __le16 ldCount;
897 __le16 arCount;
898 __le16 spanCount;
899 __le16 reserve3;
900
901 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
902 u8 ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
903 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT];
904 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT];
905};
906
907
908
909
910struct MR_PD_CFG_SEQ {
911 u16 seqNum;
912 u16 devHandle;
913 struct {
914#if defined(__BIG_ENDIAN_BITFIELD)
915 u8 reserved:7;
916 u8 tmCapable:1;
917#else
918 u8 tmCapable:1;
919 u8 reserved:7;
920#endif
921 } capability;
922 u8 reserved[3];
923} __packed;
924
925struct MR_PD_CFG_SEQ_NUM_SYNC {
926 __le32 size;
927 __le32 count;
928 struct MR_PD_CFG_SEQ seq[1];
929} __packed;
930
931struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
932 u64 RDPQBaseAddress;
933 u32 Reserved1;
934 u32 Reserved2;
935};
936
937struct fusion_context {
938 struct megasas_cmd_fusion **cmd_list;
939 dma_addr_t req_frames_desc_phys;
940 u8 *req_frames_desc;
941
942 struct dma_pool *io_request_frames_pool;
943 dma_addr_t io_request_frames_phys;
944 u8 *io_request_frames;
945
946 struct dma_pool *sg_dma_pool;
947 struct dma_pool *sense_dma_pool;
948
949 dma_addr_t reply_frames_desc_phys[MAX_MSIX_QUEUES_FUSION];
950 union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc[MAX_MSIX_QUEUES_FUSION];
951 struct dma_pool *reply_frames_desc_pool;
952
953 u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION];
954
955 u32 reply_q_depth;
956 u32 request_alloc_sz;
957 u32 reply_alloc_sz;
958 u32 io_frames_alloc_sz;
959
960 struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY *rdpq_virt;
961 dma_addr_t rdpq_phys;
962 u16 max_sge_in_main_msg;
963 u16 max_sge_in_chain;
964
965 u8 chain_offset_io_request;
966 u8 chain_offset_mfi_pthru;
967
968 struct MR_FW_RAID_MAP_ALL *ld_map[2];
969 dma_addr_t ld_map_phys[2];
970
971
972 struct MR_DRV_RAID_MAP_ALL *ld_drv_map[2];
973
974 u32 max_map_sz;
975 u32 current_map_sz;
976 u32 drv_map_sz;
977 u32 drv_map_pages;
978 struct MR_PD_CFG_SEQ_NUM_SYNC *pd_seq_sync[JBOD_MAPS_COUNT];
979 dma_addr_t pd_seq_phys[JBOD_MAPS_COUNT];
980 u8 fast_path_io;
981 struct LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT];
982 LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT];
983 u8 adapter_type;
984};
985
986union desc_value {
987 __le64 word;
988 struct {
989 __le32 low;
990 __le32 high;
991 } u;
992};
993
994void megasas_free_cmds_fusion(struct megasas_instance *instance);
995int megasas_ioc_init_fusion(struct megasas_instance *instance);
996u8 megasas_get_map_info(struct megasas_instance *instance);
997int megasas_sync_map_info(struct megasas_instance *instance);
998void megasas_release_fusion(struct megasas_instance *instance);
999void megasas_reset_reply_desc(struct megasas_instance *instance);
1000int megasas_check_mpio_paths(struct megasas_instance *instance,
1001 struct scsi_cmnd *scmd);
1002void megasas_fusion_ocr_wq(struct work_struct *work);
1003
1004#endif
1005
